JPS5255421A - Synchronous retiming system - Google Patents

Synchronous retiming system

Info

Publication number
JPS5255421A
JPS5255421A JP50131649A JP13164975A JPS5255421A JP S5255421 A JPS5255421 A JP S5255421A JP 50131649 A JP50131649 A JP 50131649A JP 13164975 A JP13164975 A JP 13164975A JP S5255421 A JPS5255421 A JP S5255421A
Authority
JP
Japan
Prior art keywords
synchronous
data
retiming
retiming system
economizatin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50131649A
Other languages
Japanese (ja)
Inventor
Takuto Kojima
Michimitsu Hattori
Shinichiro Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP50131649A priority Critical patent/JPS5255421A/en
Publication of JPS5255421A publication Critical patent/JPS5255421A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:The synchronous retiming functions are concentrated, and the data which selected and recorded the center part of data bit from scanning pulse through changing point of the data is selectred for the channel against time division multiple transmission path. Thus, the economizatin can be realized for the data network.
JP50131649A 1975-10-31 1975-10-31 Synchronous retiming system Pending JPS5255421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50131649A JPS5255421A (en) 1975-10-31 1975-10-31 Synchronous retiming system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50131649A JPS5255421A (en) 1975-10-31 1975-10-31 Synchronous retiming system

Publications (1)

Publication Number Publication Date
JPS5255421A true JPS5255421A (en) 1977-05-06

Family

ID=15062984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50131649A Pending JPS5255421A (en) 1975-10-31 1975-10-31 Synchronous retiming system

Country Status (1)

Country Link
JP (1) JPS5255421A (en)

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