JPS5242592B2 - - Google Patents
Info
- Publication number
- JPS5242592B2 JPS5242592B2 JP48028739A JP2873973A JPS5242592B2 JP S5242592 B2 JPS5242592 B2 JP S5242592B2 JP 48028739 A JP48028739 A JP 48028739A JP 2873973 A JP2873973 A JP 2873973A JP S5242592 B2 JPS5242592 B2 JP S5242592B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- ing And Chemical Polishing (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP48028739A JPS5242592B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1973-03-12 | 1973-03-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP48028739A JPS5242592B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1973-03-12 | 1973-03-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS49118373A JPS49118373A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1974-11-12 |
| JPS5242592B2 true JPS5242592B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1977-10-25 |
Family
ID=12256781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP48028739A Expired JPS5242592B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1973-03-12 | 1973-03-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5242592B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51118974A (en) * | 1975-04-11 | 1976-10-19 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| JPS5373086A (en) * | 1976-12-11 | 1978-06-29 | Fujitsu Ltd | Formation of multilayer wiring structure |
| US4249968A (en) * | 1978-12-29 | 1981-02-10 | International Business Machines Corporation | Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers |
-
1973
- 1973-03-12 JP JP48028739A patent/JPS5242592B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS49118373A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1974-11-12 |