JPS5233410A - Receiving level automatic adjusting system - Google Patents

Receiving level automatic adjusting system

Info

Publication number
JPS5233410A
JPS5233410A JP10897075A JP10897075A JPS5233410A JP S5233410 A JPS5233410 A JP S5233410A JP 10897075 A JP10897075 A JP 10897075A JP 10897075 A JP10897075 A JP 10897075A JP S5233410 A JPS5233410 A JP S5233410A
Authority
JP
Japan
Prior art keywords
adjusting system
automatic adjusting
receiving level
level automatic
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10897075A
Other languages
Japanese (ja)
Inventor
Kozo Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10897075A priority Critical patent/JPS5233410A/en
Publication of JPS5233410A publication Critical patent/JPS5233410A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/023—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse amplitude modulation

Abstract

PURPOSE:To improve the error rate by controlling the input level of A-D convertion of a receiving system and by giving a specific input to lower bits of the input of D-A convertors.
JP10897075A 1975-09-10 1975-09-10 Receiving level automatic adjusting system Pending JPS5233410A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10897075A JPS5233410A (en) 1975-09-10 1975-09-10 Receiving level automatic adjusting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10897075A JPS5233410A (en) 1975-09-10 1975-09-10 Receiving level automatic adjusting system

Publications (1)

Publication Number Publication Date
JPS5233410A true JPS5233410A (en) 1977-03-14

Family

ID=14498257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10897075A Pending JPS5233410A (en) 1975-09-10 1975-09-10 Receiving level automatic adjusting system

Country Status (1)

Country Link
JP (1) JPS5233410A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59108326U (en) * 1983-01-13 1984-07-21 横河電機株式会社 Automatic range switching circuit
JPS60164563A (en) * 1984-02-01 1985-08-27 石川島播磨重工業株式会社 Balance construction method of concrete wall
FR2740286A1 (en) * 1995-10-23 1997-04-25 Inst Eurecom DEVICE AND METHOD FOR HYBRID DIGITAL-ANALOG COMMUNICATION ON A TELEPHONE CHANNEL

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59108326U (en) * 1983-01-13 1984-07-21 横河電機株式会社 Automatic range switching circuit
JPH0224257Y2 (en) * 1983-01-13 1990-07-03
JPS60164563A (en) * 1984-02-01 1985-08-27 石川島播磨重工業株式会社 Balance construction method of concrete wall
JPH0257631B2 (en) * 1984-02-01 1990-12-05 Ishikawajima Harima Jukogyo Kk
FR2740286A1 (en) * 1995-10-23 1997-04-25 Inst Eurecom DEVICE AND METHOD FOR HYBRID DIGITAL-ANALOG COMMUNICATION ON A TELEPHONE CHANNEL
WO1997016008A1 (en) * 1995-10-23 1997-05-01 Motorola Inc. Digital-to-analog communication device and method

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