JPS52166462U - - Google Patents

Info

Publication number
JPS52166462U
JPS52166462U JP1976074831U JP7483176U JPS52166462U JP S52166462 U JPS52166462 U JP S52166462U JP 1976074831 U JP1976074831 U JP 1976074831U JP 7483176 U JP7483176 U JP 7483176U JP S52166462 U JPS52166462 U JP S52166462U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1976074831U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1976074831U priority Critical patent/JPS52166462U/ja
Publication of JPS52166462U publication Critical patent/JPS52166462U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1976074831U 1976-06-09 1976-06-09 Pending JPS52166462U (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1976074831U JPS52166462U (en:Method) 1976-06-09 1976-06-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1976074831U JPS52166462U (en:Method) 1976-06-09 1976-06-09

Publications (1)

Publication Number Publication Date
JPS52166462U true JPS52166462U (en:Method) 1977-12-16

Family

ID=28548359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1976074831U Pending JPS52166462U (en:Method) 1976-06-09 1976-06-09

Country Status (1)

Country Link
JP (1) JPS52166462U (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012222159A (ja) * 2011-04-08 2012-11-12 Denso Corp 半導体装置及び半導体装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4824525U (en:Method) * 1971-07-27 1973-03-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4824525U (en:Method) * 1971-07-27 1973-03-22

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012222159A (ja) * 2011-04-08 2012-11-12 Denso Corp 半導体装置及び半導体装置の製造方法

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