JPS52132754A - Interruption addressable control system - Google Patents

Interruption addressable control system

Info

Publication number
JPS52132754A
JPS52132754A JP3962377A JP3962377A JPS52132754A JP S52132754 A JPS52132754 A JP S52132754A JP 3962377 A JP3962377 A JP 3962377A JP 3962377 A JP3962377 A JP 3962377A JP S52132754 A JPS52132754 A JP S52132754A
Authority
JP
Japan
Prior art keywords
interruption
control system
addressable control
addressable
interruption addressable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3962377A
Other languages
English (en)
Other versions
JPS5653782B2 (ja
Inventor
Yuujin Baanii Richiyaado
Suteiisu Osuboon Uiriamu
Aran Gureibieru Rin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS52132754A publication Critical patent/JPS52132754A/ja
Publication of JPS5653782B2 publication Critical patent/JPS5653782B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Executing Machine-Instructions (AREA)
JP3962377A 1976-04-30 1977-04-08 Interruption addressable control system Granted JPS52132754A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/682,226 US4037207A (en) 1976-04-30 1976-04-30 System for controlling address keys under interrupt conditions

Publications (2)

Publication Number Publication Date
JPS52132754A true JPS52132754A (en) 1977-11-07
JPS5653782B2 JPS5653782B2 (ja) 1981-12-21

Family

ID=24738759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3962377A Granted JPS52132754A (en) 1976-04-30 1977-04-08 Interruption addressable control system

Country Status (9)

Country Link
US (1) US4037207A (ja)
JP (1) JPS52132754A (ja)
AU (1) AU507988B2 (ja)
BR (1) BR7702778A (ja)
CA (1) CA1075366A (ja)
DE (1) DE2717700C2 (ja)
FR (1) FR2349882A1 (ja)
GB (1) GB1557118A (ja)
SE (1) SE417553B (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4408292A (en) * 1979-09-27 1983-10-04 Sharp Kabushiki Kaisha Data print control in an electronic cash register
US4355355A (en) * 1980-03-19 1982-10-19 International Business Machines Corp. Address generating mechanism for multiple virtual spaces
US4587632A (en) * 1980-05-27 1986-05-06 At&T Bell Laboratories Lookahead stack oriented computer
US4575817A (en) * 1983-06-27 1986-03-11 International Business Machines Corporation Switching of programming routine supporting storage stacks
JPH01112450A (ja) * 1987-10-27 1989-05-01 Sharp Corp メモリ管理ユニット
US5287523A (en) * 1990-10-09 1994-02-15 Motorola, Inc. Method for servicing a peripheral interrupt request in a microcontroller
US5548746A (en) * 1993-11-12 1996-08-20 International Business Machines Corporation Non-contiguous mapping of I/O addresses to use page protection of a process

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3566358A (en) * 1968-03-19 1971-02-23 Bevier Hasbrouck Integrated multi-computer system
GB1410631A (en) * 1972-01-26 1975-10-22 Plessey Co Ltd Data processing system interrupt arrangements
US3828327A (en) * 1973-04-30 1974-08-06 Ibm Simplified storage protection and address translation under system mode control in a data processing system
US4037214A (en) * 1976-04-30 1977-07-19 International Business Machines Corporation Key register controlled accessing system

Also Published As

Publication number Publication date
CA1075366A (en) 1980-04-08
SE417553B (sv) 1981-03-23
AU2474377A (en) 1978-11-09
BR7702778A (pt) 1978-02-21
FR2349882B1 (ja) 1979-03-09
DE2717700A1 (de) 1977-11-10
SE7704957L (sv) 1977-10-31
GB1557118A (en) 1979-12-05
DE2717700C2 (de) 1985-05-23
AU507988B2 (en) 1980-03-06
US4037207A (en) 1977-07-19
FR2349882A1 (fr) 1977-11-25
JPS5653782B2 (ja) 1981-12-21

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