JPS52111348A - Fail soft synchronous clock device - Google Patents

Fail soft synchronous clock device

Info

Publication number
JPS52111348A
JPS52111348A JP2617077A JP2617077A JPS52111348A JP S52111348 A JPS52111348 A JP S52111348A JP 2617077 A JP2617077 A JP 2617077A JP 2617077 A JP2617077 A JP 2617077A JP S52111348 A JPS52111348 A JP S52111348A
Authority
JP
Japan
Prior art keywords
synchronous clock
clock device
fail soft
soft synchronous
fail
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2617077A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5637566B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Ansonii Kimuringaa Jiyosefu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of JPS52111348A publication Critical patent/JPS52111348A/ja
Publication of JPS5637566B2 publication Critical patent/JPS5637566B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
JP2617077A 1976-03-12 1977-03-11 Fail soft synchronous clock device Granted JPS52111348A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/666,279 US4021784A (en) 1976-03-12 1976-03-12 Clock synchronization system

Publications (2)

Publication Number Publication Date
JPS52111348A true JPS52111348A (en) 1977-09-19
JPS5637566B2 JPS5637566B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1981-09-01

Family

ID=24673564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2617077A Granted JPS52111348A (en) 1976-03-12 1977-03-11 Fail soft synchronous clock device

Country Status (6)

Country Link
US (1) US4021784A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS52111348A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2709773C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2344072A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1579944A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IT (1) IT1076630B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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JPS6038740B2 (ja) * 1976-04-19 1985-09-03 株式会社東芝 デ−タ処理装置
SE397013B (sv) * 1976-12-17 1977-10-10 Ellemtel Utvecklings Ab Sett och anordning for att overfora datainformationer till tva parallellt arbetande datamaskindelar
US4079456A (en) * 1977-01-24 1978-03-14 Rca Corporation Output buffer synchronizing circuit having selectively variable delay means
US4201885A (en) * 1978-10-26 1980-05-06 Gte Automatic Electric Laboratories Incorporated Routinable clock circuit
US4428044A (en) 1979-09-20 1984-01-24 Bell Telephone Laboratories, Incorporated Peripheral unit controller
US4368514A (en) * 1980-04-25 1983-01-11 Timeplex, Inc. Multi-processor system
US4405898A (en) * 1980-06-30 1983-09-20 International Business Machines Corporation Pseudo synchronous clocking
US4447870A (en) * 1981-04-03 1984-05-08 Honeywell Information Systems Inc. Apparatus for setting the basic clock timing in a data processing system
US4462072A (en) * 1981-04-03 1984-07-24 Honeywell Information Systems Inc. Clock system having a stall capability to enable processing of errors
US4514647A (en) * 1983-08-01 1985-04-30 At&T Bell Laboratories Chipset synchronization arrangement
US4584643A (en) * 1983-08-31 1986-04-22 International Business Machines Corporation Decentralized synchronization of clocks
US4546269A (en) * 1983-12-01 1985-10-08 Control Data Corporation Method and apparatus for optimally tuning clock signals for digital computers
US4569017A (en) * 1983-12-22 1986-02-04 Gte Automatic Electric Incorporated Duplex central processing unit synchronization circuit
US4611273A (en) * 1983-12-30 1986-09-09 International Business Machines Corporation Synchronized microsequencer for a microprocessor
US4827401A (en) * 1984-10-24 1989-05-02 International Business Machines Corporation Method and apparatus for synchronizing clocks prior to the execution of a flush operation
JPS6227813A (ja) * 1985-07-29 1987-02-05 Hitachi Ltd 位相同期方式
US4748588A (en) * 1985-12-18 1988-05-31 International Business Machines Corp. Fast data synchronizer
US4953077A (en) * 1987-05-15 1990-08-28 International Business Machines Corporation Accelerated data transfer mechanism using modified clock cycle
EP0551969A2 (en) * 1987-09-28 1993-07-21 Compaq Computer Corporation Circuit and method for performing clock division and clock synchronisation
JPH0797328B2 (ja) * 1988-10-25 1995-10-18 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン フオールト・トレラント同期システム
US5335337A (en) * 1989-01-27 1994-08-02 Digital Equipment Corporation Programmable data transfer timing
EP0454320B1 (en) * 1990-04-20 1995-12-13 Texas Instruments Incorporated Scan test circuit for use with multiple frequency circuits
JP3451099B2 (ja) 1991-12-06 2003-09-29 株式会社日立製作所 外部記憶サブシステム
US5379415A (en) * 1992-09-29 1995-01-03 Zitel Corporation Fault tolerant memory system
US5418934A (en) * 1993-09-30 1995-05-23 Intel Corporation Synchronizing chained distributed digital chronometers by the use of an echo signal
US6276844B1 (en) * 1993-12-06 2001-08-21 International Business Machines Corporation Clustered, buffered simms and assemblies thereof
US5634116A (en) * 1995-03-30 1997-05-27 International Business Machines Corporation Non-integer multiple clock translator
US6279058B1 (en) * 1998-07-02 2001-08-21 Advanced Micro Devices, Inc. Master isochronous clock structure having a clock controller coupling to a CPU and two data buses
US6260152B1 (en) * 1998-07-30 2001-07-10 Siemens Information And Communication Networks, Inc. Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains
US6993669B2 (en) * 2001-04-18 2006-01-31 Gallitzin Allegheny Llc Low power clocking systems and methods
US6990598B2 (en) * 2001-03-21 2006-01-24 Gallitzin Allegheny Llc Low power reconfigurable systems and methods
JP2002287997A (ja) * 2001-03-23 2002-10-04 Kinji Mori 多重系処理方法
US7057518B2 (en) 2001-06-22 2006-06-06 Schmidt Dominik J Systems and methods for testing wireless devices
US6898721B2 (en) * 2001-06-22 2005-05-24 Gallitzin Allegheny Llc Clock generation systems and methods
DE10148134B4 (de) * 2001-09-28 2007-04-19 Infineon Technologies Ag Verfahren zur Busansteuerung
US7356618B2 (en) * 2003-12-31 2008-04-08 Intel Corporation Method and system for synchronizing platform clocks in a distributed wireless platform
US7197658B2 (en) * 2003-12-31 2007-03-27 Intel Corporation Synchronizing samples of a multimedia stream with a system clock
US7266713B2 (en) * 2004-01-09 2007-09-04 Intel Corporation Apparatus and method for adaptation of time synchronization of a plurality of multimedia streams
US7318165B2 (en) * 2004-01-15 2008-01-08 International Business Machines Corporation Apparatus for managing a cache in a distributed caching environment having an event auditor and a cache auditor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE326321B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1968-11-15 1970-07-20 E Sjoequist
DE2104427C3 (de) * 1971-01-30 1978-09-07 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur Zeitsteuerung von Übertragungsvorgängen
US3715729A (en) * 1971-03-10 1973-02-06 Ibm Timing control for a multiprocessor system
US3896418A (en) * 1971-08-31 1975-07-22 Texas Instruments Inc Synchronous multi-processor system utilizing a single external memory unit
FR2159150A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1972-11-30 1973-06-15 Materiel Telephonique
CH556576A (de) * 1973-03-28 1974-11-29 Hasler Ag Einrichtung zur synchronisierung dreier rechner.
US3919695A (en) * 1973-12-26 1975-11-11 Ibm Asynchronous clocking apparatus
US3934232A (en) * 1974-04-25 1976-01-20 Honeywell Information Systems, Inc. Interprocessor communication apparatus for a data processing system

Also Published As

Publication number Publication date
GB1579944A (en) 1980-11-26
IT1076630B (it) 1985-04-27
JPS5637566B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1981-09-01
DE2709773A1 (de) 1977-09-15
DE2709773C2 (de) 1982-04-15
US4021784A (en) 1977-05-03
FR2344072A1 (fr) 1977-10-07
FR2344072B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1984-03-09

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