JPS5153409A - JOHODEN SOKEI - Google Patents

Abstract

1525604 Supervising interstation signalling SIEMENS AG 4 Sept 1975 [11 Sept 1974] 36380/75 Addition to 1398961 Heading H4L A data transmission system having a monitoring signal of at least one bit interposed at regular intervals into the data, comprises a plurality of sections connected by intermediate stations, wherein if the monitoring signal is incorrect when received the station transmits at least one bit in inverted form back to the preceding station. The inverted bit may effect automatic switch-over to another channel. The receiving and transmitting sections of an intermediate station in a 30 channel PCM system are shown in Figs. 1 and 2 respectively. A first shift register SRI receives data from input PE and link timing pulses from input TE. Read-outs RKL, MWL extract respectively the frame synchronizing word and the message word, timing pulses for RKL, MWL being provided by a first pulse generator TZ1. Bits, 5, 6 and 7 of the message word are supplied to an acknowledge and address analyser RAW. A first timing pulse monitoring unit TU1 produces a high level at ouput A2 in the event of a timing fault. A synchronization monitoring unit SYNC receives bits 2, 3, 4, 6, 7 and 8 of the frame synchronizing word, and bit 2 of the message word, the outputs A1, B1 being high in the event of a fault, e.g. if the frame synchronizing word is incorrect several times consecutively. A gate NOR1 having inputs A1, A2 produces an alarm criterion A which is low for a fault. A second shift register SR2, Fig. 2, receives a frame synchronizing word and a message word from transmitting logic units RKS and MWS respectively, bit 5 of the frame synchronizing word being inverted in the event of a fault by a direct input from A. Inputs from A also control the transmission of frame timing pulses from TZ1 to TZ2 via gate AND1, and the transmission of link timing pulses from TE to TZ2 via gates NAND1 and AND2, the pulses from TE being replaced by pulses from a generator TG if the A input applied to gate OR1 is low. A scrambler SC has its output connected to a gate NOR2 which also receives an A input via a switch U. Scrambler SC produces a high level output while the frame synchronizing and message words are being passed from SR2 to signal output PO, so that these words are not scrambled irrespective of the level at input 1 of NOR2. If the A signal to input 1 of NOR2 is low, or if input 1 of NOR2 is earthed manually by switch U, the output of SC is fed in inverted form to gate EXOR1, so that a scrambled signal is produced at output PO.