JPS5150463A - Konseishusekikairono seizohoho - Google Patents

Konseishusekikairono seizohoho

Info

Publication number
JPS5150463A
JPS5150463A JP12514174A JP12514174A JPS5150463A JP S5150463 A JPS5150463 A JP S5150463A JP 12514174 A JP12514174 A JP 12514174A JP 12514174 A JP12514174 A JP 12514174A JP S5150463 A JPS5150463 A JP S5150463A
Authority
JP
Japan
Prior art keywords
konseishusekikairono
seizohoho
konseishusekikairono seizohoho
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12514174A
Other languages
English (en)
Other versions
JPS5546063B2 (ja
Inventor
Ryozo Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marcon Electronics Co Ltd
Original Assignee
Marcon Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marcon Electronics Co Ltd filed Critical Marcon Electronics Co Ltd
Priority to JP12514174A priority Critical patent/JPS5150463A/ja
Publication of JPS5150463A publication Critical patent/JPS5150463A/ja
Publication of JPS5546063B2 publication Critical patent/JPS5546063B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP12514174A 1974-10-29 1974-10-29 Konseishusekikairono seizohoho Granted JPS5150463A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12514174A JPS5150463A (ja) 1974-10-29 1974-10-29 Konseishusekikairono seizohoho

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12514174A JPS5150463A (ja) 1974-10-29 1974-10-29 Konseishusekikairono seizohoho

Publications (2)

Publication Number Publication Date
JPS5150463A true JPS5150463A (ja) 1976-05-04
JPS5546063B2 JPS5546063B2 (ja) 1980-11-21

Family

ID=14902864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12514174A Granted JPS5150463A (ja) 1974-10-29 1974-10-29 Konseishusekikairono seizohoho

Country Status (1)

Country Link
JP (1) JPS5150463A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429055A (en) * 1977-08-09 1979-03-03 Shindo Denshi Kougiyou Kk Method of making print wiring substrate
JPS60103693A (ja) * 1983-11-11 1985-06-07 株式会社東芝 混成集積回路の製造方法
JP2007266212A (ja) * 2006-03-28 2007-10-11 Kyocera Corp 表面実装モジュールの製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495383A (ja) * 1972-05-01 1974-01-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495383A (ja) * 1972-05-01 1974-01-18

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429055A (en) * 1977-08-09 1979-03-03 Shindo Denshi Kougiyou Kk Method of making print wiring substrate
JPS60103693A (ja) * 1983-11-11 1985-06-07 株式会社東芝 混成集積回路の製造方法
JP2007266212A (ja) * 2006-03-28 2007-10-11 Kyocera Corp 表面実装モジュールの製造方法
JP4684149B2 (ja) * 2006-03-28 2011-05-18 京セラ株式会社 表面実装モジュールの製造方法

Also Published As

Publication number Publication date
JPS5546063B2 (ja) 1980-11-21

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