JPS5129048A - - Google Patents

Info

Publication number
JPS5129048A
JPS5129048A JP49102217A JP10221774A JPS5129048A JP S5129048 A JPS5129048 A JP S5129048A JP 49102217 A JP49102217 A JP 49102217A JP 10221774 A JP10221774 A JP 10221774A JP S5129048 A JPS5129048 A JP S5129048A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP49102217A
Other versions
JPS5517424B2 (ja
Inventor
Masanori Mogi
Keiichiro Uchida
Minoru Etsuno
Takatoshi Muraoka
Shigeru Nagasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10221774A priority Critical patent/JPS5517424B2/ja
Priority to DE19752538329 priority patent/DE2538329A1/de
Priority to US05/609,698 priority patent/US3976866A/en
Priority to FR7527145A priority patent/FR2284151A1/fr
Priority to GB36752/75A priority patent/GB1514320A/en
Publication of JPS5129048A publication Critical patent/JPS5129048A/ja
Publication of JPS5517424B2 publication Critical patent/JPS5517424B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • G06F2207/3836—One's complement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP10221774A 1974-09-05 1974-09-05 Expired JPS5517424B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP10221774A JPS5517424B2 (ja) 1974-09-05 1974-09-05
DE19752538329 DE2538329A1 (de) 1974-09-05 1975-08-28 Additionssteuersystem
US05/609,698 US3976866A (en) 1974-09-05 1975-09-02 Addition control system
FR7527145A FR2284151A1 (fr) 1974-09-05 1975-09-04 Equipement pour l'execution d'une addition
GB36752/75A GB1514320A (en) 1974-09-05 1975-09-05 Number processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10221774A JPS5517424B2 (ja) 1974-09-05 1974-09-05

Publications (2)

Publication Number Publication Date
JPS5129048A true JPS5129048A (ja) 1976-03-11
JPS5517424B2 JPS5517424B2 (ja) 1980-05-12

Family

ID=14321486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10221774A Expired JPS5517424B2 (ja) 1974-09-05 1974-09-05

Country Status (5)

Country Link
US (1) US3976866A (ja)
JP (1) JPS5517424B2 (ja)
DE (1) DE2538329A1 (ja)
FR (1) FR2284151A1 (ja)
GB (1) GB1514320A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57132268A (en) * 1981-02-09 1982-08-16 Victor Co Of Japan Ltd Digital signal processing circuit
US5595700A (en) * 1991-05-02 1997-01-21 Mitsubishi Pencil Kabushiki Kaisha Non-baked color pencil leads and method for preparing same

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4084254A (en) * 1977-04-28 1978-04-11 International Business Machines Corporation Divider using carry save adder with nonperforming lookahead
JPS6068432A (ja) * 1983-09-22 1985-04-19 Hitachi Ltd キヤリセ−ブアダ−の符号生成方式
JPS60144878U (ja) * 1984-03-07 1985-09-26 鈴木　康之 蚊取線香燻し器
JPS62257526A (ja) * 1986-04-30 1987-11-10 Mitsubishi Electric Corp 算術論理演算装置
US5351207A (en) * 1992-08-31 1994-09-27 Intel Corporation Methods and apparatus for subtraction with 3:2 carry-save adders
US5333120A (en) * 1992-11-17 1994-07-26 Gilber T Joseph R Binary two's complement arithmetic circuit
GB2422232B (en) * 2005-01-15 2009-01-07 David Wallace Moncrieff Scott Course and sail-plan predictor
US20060185863A1 (en) * 2005-02-18 2006-08-24 Solbach John M Iii Thistle kicker - an improved plant cultivation tool

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57132268A (en) * 1981-02-09 1982-08-16 Victor Co Of Japan Ltd Digital signal processing circuit
JPS6116110B2 (ja) * 1981-02-09 1986-04-28 Victor Company Of Japan
US5595700A (en) * 1991-05-02 1997-01-21 Mitsubishi Pencil Kabushiki Kaisha Non-baked color pencil leads and method for preparing same

Also Published As

Publication number Publication date
FR2284151A1 (fr) 1976-04-02
JPS5517424B2 (ja) 1980-05-12
US3976866A (en) 1976-08-24
FR2284151B1 (ja) 1978-04-07
DE2538329A1 (de) 1976-03-25
GB1514320A (en) 1978-06-14

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