JPS5128980B2 - - Google Patents
Info
- Publication number
- JPS5128980B2 JPS5128980B2 JP47129561A JP12956172A JPS5128980B2 JP S5128980 B2 JPS5128980 B2 JP S5128980B2 JP 47129561 A JP47129561 A JP 47129561A JP 12956172 A JP12956172 A JP 12956172A JP S5128980 B2 JPS5128980 B2 JP S5128980B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP47129561A JPS5128980B2 (cs) | 1972-12-26 | 1972-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP47129561A JPS5128980B2 (cs) | 1972-12-26 | 1972-12-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4989481A JPS4989481A (cs) | 1974-08-27 |
| JPS5128980B2 true JPS5128980B2 (cs) | 1976-08-23 |
Family
ID=15012523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP47129561A Expired JPS5128980B2 (cs) | 1972-12-26 | 1972-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5128980B2 (cs) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3984620A (en) * | 1975-06-04 | 1976-10-05 | Raytheon Company | Integrated circuit chip test and assembly package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4512536Y1 (cs) * | 1967-07-19 | 1970-06-01 |
-
1972
- 1972-12-26 JP JP47129561A patent/JPS5128980B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4989481A (cs) | 1974-08-27 |