JPS5120266B2 - - Google Patents
Info
- Publication number
- JPS5120266B2 JPS5120266B2 JP3367372A JP3367372A JPS5120266B2 JP S5120266 B2 JPS5120266 B2 JP S5120266B2 JP 3367372 A JP3367372 A JP 3367372A JP 3367372 A JP3367372 A JP 3367372A JP S5120266 B2 JPS5120266 B2 JP S5120266B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Element Separation (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3367372A JPS5120266B2 (nl) | 1972-04-03 | 1972-04-03 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3367372A JPS5120266B2 (nl) | 1972-04-03 | 1972-04-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS48102582A JPS48102582A (nl) | 1973-12-22 |
JPS5120266B2 true JPS5120266B2 (nl) | 1976-06-23 |
Family
ID=12392959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3367372A Expired JPS5120266B2 (nl) | 1972-04-03 | 1972-04-03 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5120266B2 (nl) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5243385A (en) * | 1975-10-01 | 1977-04-05 | Hitachi Ltd | Process for production of semiconductor integrated circuit |
US4526631A (en) * | 1984-06-25 | 1985-07-02 | International Business Machines Corporation | Method for forming a void free isolation pattern utilizing etch and refill techniques |
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1972
- 1972-04-03 JP JP3367372A patent/JPS5120266B2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS48102582A (nl) | 1973-12-22 |