JPS51121461U - - Google Patents
Info
- Publication number
- JPS51121461U JPS51121461U JP3871575U JP3871575U JPS51121461U JP S51121461 U JPS51121461 U JP S51121461U JP 3871575 U JP3871575 U JP 3871575U JP 3871575 U JP3871575 U JP 3871575U JP S51121461 U JPS51121461 U JP S51121461U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3871575U JPS51121461U (ja) | 1975-03-22 | 1975-03-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3871575U JPS51121461U (ja) | 1975-03-22 | 1975-03-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS51121461U true JPS51121461U (ja) | 1976-10-01 |
Family
ID=28161212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3871575U Pending JPS51121461U (ja) | 1975-03-22 | 1975-03-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS51121461U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59201433A (ja) * | 1983-04-30 | 1984-11-15 | Fujitsu Ltd | 半導体装置の製造方法 |
-
1975
- 1975-03-22 JP JP3871575U patent/JPS51121461U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59201433A (ja) * | 1983-04-30 | 1984-11-15 | Fujitsu Ltd | 半導体装置の製造方法 |