JPS51120669A - Package for electronic circuits and method of making the same - Google Patents

Package for electronic circuits and method of making the same

Info

Publication number
JPS51120669A
JPS51120669A JP51032697A JP3269776A JPS51120669A JP S51120669 A JPS51120669 A JP S51120669A JP 51032697 A JP51032697 A JP 51032697A JP 3269776 A JP3269776 A JP 3269776A JP S51120669 A JPS51120669 A JP S51120669A
Authority
JP
Japan
Prior art keywords
package
making
same
electronic circuits
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP51032697A
Other languages
English (en)
Japanese (ja)
Inventor
Emu Chitoutsudo Furetsudo
Efu Rorinsu Pooru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of JPS51120669A publication Critical patent/JPS51120669A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP51032697A 1975-03-26 1976-03-26 Package for electronic circuits and method of making the same Pending JPS51120669A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US56232875A 1975-03-26 1975-03-26

Publications (1)

Publication Number Publication Date
JPS51120669A true JPS51120669A (en) 1976-10-22

Family

ID=24245832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51032697A Pending JPS51120669A (en) 1975-03-26 1976-03-26 Package for electronic circuits and method of making the same

Country Status (5)

Country Link
JP (1) JPS51120669A (fr)
BE (1) BE840018A (fr)
DE (1) DE2611871A1 (fr)
FR (1) FR2305914A1 (fr)
GB (1) GB1504097A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4489364A (en) * 1981-12-31 1984-12-18 International Business Machines Corporation Chip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surface
US4799128A (en) * 1985-12-20 1989-01-17 Ncr Corporation Multilayer printed circuit board with domain partitioning
DE3810486A1 (de) * 1988-03-28 1989-10-19 Kaleto Ag Verfahren zum herstellen kundenspezifischer elektrischer schaltungen, insbesondere gedruckter schaltungen
FR2640457B1 (fr) * 1988-12-09 1991-01-25 Thomson Csf Dispositif de raccordement de composants et module fonctionnel l'utilisant
US5410107A (en) 1993-03-01 1995-04-25 The Board Of Trustees Of The University Of Arkansas Multichip module
FR3105084B1 (fr) * 2019-12-19 2021-12-31 Saint Gobain Vitrage feuilleté à couche chauffante au même niveau de la structure feuilletée que le masque des amenées de courant électrique de la couche chauffante

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3491197A (en) * 1966-12-30 1970-01-20 Texas Instruments Inc Universal printed circuit board
JPS4876059A (fr) * 1972-01-14 1973-10-13

Also Published As

Publication number Publication date
DE2611871A1 (de) 1976-10-07
FR2305914A1 (fr) 1976-10-22
FR2305914B1 (fr) 1979-03-23
BE840018A (fr) 1976-07-16
GB1504097A (en) 1978-03-15

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