JPS5068749A - - Google Patents

Info

Publication number
JPS5068749A
JPS5068749A JP49120429A JP12042974A JPS5068749A JP S5068749 A JPS5068749 A JP S5068749A JP 49120429 A JP49120429 A JP 49120429A JP 12042974 A JP12042974 A JP 12042974A JP S5068749 A JPS5068749 A JP S5068749A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP49120429A
Other languages
Japanese (ja)
Other versions
JPS5619648B2 (cg-RX-API-DMAC7.html
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS5068749A publication Critical patent/JPS5068749A/ja
Publication of JPS5619648B2 publication Critical patent/JPS5619648B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Complex Calculations (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Error Detection And Correction (AREA)
  • Processing Of Color Television Signals (AREA)
JP12042974A 1973-10-20 1974-10-21 Expired JPS5619648B2 (cg-RX-API-DMAC7.html)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2352686A DE2352686B2 (de) 1973-10-20 1973-10-20 Dezimaler Parallel-Addierer/Substrahierer

Publications (2)

Publication Number Publication Date
JPS5068749A true JPS5068749A (cg-RX-API-DMAC7.html) 1975-06-09
JPS5619648B2 JPS5619648B2 (cg-RX-API-DMAC7.html) 1981-05-08

Family

ID=5895971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12042974A Expired JPS5619648B2 (cg-RX-API-DMAC7.html) 1973-10-20 1974-10-21

Country Status (6)

Country Link
US (1) US3935438A (cg-RX-API-DMAC7.html)
JP (1) JPS5619648B2 (cg-RX-API-DMAC7.html)
CH (1) CH577711A5 (cg-RX-API-DMAC7.html)
DE (1) DE2352686B2 (cg-RX-API-DMAC7.html)
FR (1) FR2248552B3 (cg-RX-API-DMAC7.html)
GB (1) GB1484149A (cg-RX-API-DMAC7.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50152632A (cg-RX-API-DMAC7.html) * 1974-05-27 1975-12-08
JPS59128633A (ja) * 1983-01-13 1984-07-24 Seiko Epson Corp １チツプマイクロコンピユ−タ
JP2015143949A (ja) * 2014-01-31 2015-08-06 富士通株式会社 演算プログラム、演算装置および演算方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2460897C3 (de) * 1974-12-21 1978-10-05 Olympia Werke Ag, 2940 Wilhelmshaven Parallel-Rechenwerk für Addition und Subtraktion
US4172288A (en) * 1976-03-08 1979-10-23 Motorola, Inc. Binary or BCD adder with precorrected result
US4245328A (en) * 1979-01-03 1981-01-13 Honeywell Information Systems Inc. Binary coded decimal correction apparatus for use in an arithmetic unit of a data processing unit
FR2463452B1 (fr) * 1979-08-10 1985-10-11 Sems Dispositif additionneur et soustracteur, comportant au moins un operateur binaire, et operateur decimal comportant un tel dispositif
DE3172895D1 (en) * 1980-07-10 1985-12-19 Int Computers Ltd Digital adder circuit
US4644489A (en) * 1984-02-10 1987-02-17 Prime Computer, Inc. Multi-format binary coded decimal processor with selective output formatting
JPS6381143U (cg-RX-API-DMAC7.html) * 1986-11-14 1988-05-28
US4805131A (en) * 1987-07-09 1989-02-14 Digital Equipment Corporation BCD adder circuit
JPH04500572A (ja) * 1988-09-09 1992-01-30 シーメンス アクチエンゲゼルシヤフト Ｂｃｄコードまたはデユアルコードでコード化された被演算数の加算または減算のための回路装置
US6546411B1 (en) * 1999-12-03 2003-04-08 International Business Machines Corporation High-speed radix 100 parallel adder
HK1046756B (zh) * 1999-12-23 2004-12-03 Intel Corporation 进行单循环加法或减法及於冗余形式运算中进行比较的方法及仪器
US6826588B2 (en) 1999-12-23 2004-11-30 Intel Corporation Method and apparatus for a fast comparison in redundant form arithmetic
US6813628B2 (en) 1999-12-23 2004-11-02 Intel Corporation Method and apparatus for performing equality comparison in redundant form arithmetic
US7299254B2 (en) * 2003-11-24 2007-11-20 International Business Machines Corporation Binary coded decimal addition
US9128759B2 (en) * 2012-11-27 2015-09-08 International Business Machines Corporation Decimal multi-precision overflow and tininess detection

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL276777A (cg-RX-API-DMAC7.html) * 1961-04-04
US3629565A (en) * 1970-02-13 1971-12-21 Ibm Improved decimal adder for directly implementing bcd addition utilizing logic circuitry
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system
US3752394A (en) * 1972-07-31 1973-08-14 Ibm Modular arithmetic and logic unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50152632A (cg-RX-API-DMAC7.html) * 1974-05-27 1975-12-08
JPS59128633A (ja) * 1983-01-13 1984-07-24 Seiko Epson Corp １チツプマイクロコンピユ−タ
JP2015143949A (ja) * 2014-01-31 2015-08-06 富士通株式会社 演算プログラム、演算装置および演算方法

Also Published As

Publication number Publication date
GB1484149A (en) 1977-08-24
CH577711A5 (cg-RX-API-DMAC7.html) 1976-07-15
DE2352686B2 (de) 1978-05-11
FR2248552A1 (cg-RX-API-DMAC7.html) 1975-05-16
DE2352686A1 (de) 1975-04-30
FR2248552B3 (cg-RX-API-DMAC7.html) 1977-07-29
JPS5619648B2 (cg-RX-API-DMAC7.html) 1981-05-08
US3935438A (en) 1976-01-27

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