JPS5039975B1 - - Google Patents
Info
- Publication number
- JPS5039975B1 JPS5039975B1 JP44018099A JP1809969A JPS5039975B1 JP S5039975 B1 JPS5039975 B1 JP S5039975B1 JP 44018099 A JP44018099 A JP 44018099A JP 1809969 A JP1809969 A JP 1809969A JP S5039975 B1 JPS5039975 B1 JP S5039975B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1968J0035962 DE1574666B2 (de) | 1968-03-19 | 1968-03-19 | Schaltungsanordnung zur bildung komplexer logischer verknuepfungen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5039975B1 true JPS5039975B1 (de) | 1975-12-20 |
Family
ID=7205590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP44018099A Pending JPS5039975B1 (de) | 1968-03-19 | 1969-03-11 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5039975B1 (de) |
| DE (1) | DE1574666B2 (de) |
| FR (1) | FR1602785A (de) |
| GB (1) | GB1236339A (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB8621357D0 (en) * | 1986-09-04 | 1986-10-15 | Mcallister R I | Hinged barrier semiconductor integrated circuits |
-
1968
- 1968-03-19 DE DE1968J0035962 patent/DE1574666B2/de active Granted
- 1968-12-30 FR FR1602785D patent/FR1602785A/fr not_active Expired
-
1969
- 1969-03-11 JP JP44018099A patent/JPS5039975B1/ja active Pending
- 1969-03-18 GB GB1401369A patent/GB1236339A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE1574666B2 (de) | 1976-07-22 |
| DE1574666A1 (de) | 1971-06-03 |
| GB1236339A (en) | 1971-06-23 |
| FR1602785A (de) | 1971-01-25 |