JPS50143072A - - Google Patents

Info

Publication number
JPS50143072A
JPS50143072A JP5031074A JP5031074A JPS50143072A JP S50143072 A JPS50143072 A JP S50143072A JP 5031074 A JP5031074 A JP 5031074A JP 5031074 A JP5031074 A JP 5031074A JP S50143072 A JPS50143072 A JP S50143072A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5031074A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5031074A priority Critical patent/JPS50143072A/ja
Publication of JPS50143072A publication Critical patent/JPS50143072A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Landscapes

  • Wire Bonding (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
JP5031074A 1974-05-08 1974-05-08 Pending JPS50143072A (da)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5031074A JPS50143072A (da) 1974-05-08 1974-05-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5031074A JPS50143072A (da) 1974-05-08 1974-05-08

Publications (1)

Publication Number Publication Date
JPS50143072A true JPS50143072A (da) 1975-11-18

Family

ID=12855306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5031074A Pending JPS50143072A (da) 1974-05-08 1974-05-08

Country Status (1)

Country Link
JP (1) JPS50143072A (da)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6157555U (da) * 1984-09-20 1986-04-17
JPS61205145U (da) * 1986-06-12 1986-12-24
JPH0268981A (ja) * 1988-09-02 1990-03-08 Matsushita Electric Works Ltd 金属ベース配線基板
JPH05327152A (ja) * 1992-05-18 1993-12-10 Sanken Electric Co Ltd 配線基板及びその製造方法
JPH07142832A (ja) * 1993-11-12 1995-06-02 Nec Corp プリント基板およびそれを用いた電子回路
JP2012064914A (ja) * 2010-09-16 2012-03-29 Samsung Electro-Mechanics Co Ltd 放熱基板及びその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6157555U (da) * 1984-09-20 1986-04-17
JPH039341Y2 (da) * 1984-09-20 1991-03-08
JPS61205145U (da) * 1986-06-12 1986-12-24
JPH0268981A (ja) * 1988-09-02 1990-03-08 Matsushita Electric Works Ltd 金属ベース配線基板
JPH05327152A (ja) * 1992-05-18 1993-12-10 Sanken Electric Co Ltd 配線基板及びその製造方法
JPH07142832A (ja) * 1993-11-12 1995-06-02 Nec Corp プリント基板およびそれを用いた電子回路
JP2012064914A (ja) * 2010-09-16 2012-03-29 Samsung Electro-Mechanics Co Ltd 放熱基板及びその製造方法

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