JPS4999274A - - Google Patents

Info

Publication number
JPS4999274A
JPS4999274A JP48010452A JP1045273A JPS4999274A JP S4999274 A JPS4999274 A JP S4999274A JP 48010452 A JP48010452 A JP 48010452A JP 1045273 A JP1045273 A JP 1045273A JP S4999274 A JPS4999274 A JP S4999274A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP48010452A
Other languages
Japanese (ja)
Other versions
JPS5236675B2 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP48010452A priority Critical patent/JPS5236675B2/ja
Priority to DE2403641A priority patent/DE2403641A1/de
Publication of JPS4999274A publication Critical patent/JPS4999274A/ja
Publication of JPS5236675B2 publication Critical patent/JPS5236675B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00Charge transfer devices
    • H10D44/40Charge-coupled devices [CCD]
    • H10D44/45Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0198Integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers

Landscapes

  • Manufacturing Of Printed Circuit Boards (AREA)
  • Weting (AREA)
  • ing And Chemical Polishing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
JP48010452A 1973-01-25 1973-01-25 Expired JPS5236675B2 (https=)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP48010452A JPS5236675B2 (https=) 1973-01-25 1973-01-25
DE2403641A DE2403641A1 (de) 1973-01-25 1974-01-25 Verfahren zur herstellung von feinen mustern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP48010452A JPS5236675B2 (https=) 1973-01-25 1973-01-25

Publications (2)

Publication Number Publication Date
JPS4999274A true JPS4999274A (https=) 1974-09-19
JPS5236675B2 JPS5236675B2 (https=) 1977-09-17

Family

ID=11750521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48010452A Expired JPS5236675B2 (https=) 1973-01-25 1973-01-25

Country Status (2)

Country Link
JP (1) JPS5236675B2 (https=)
DE (1) DE2403641A1 (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5133568A (https=) * 1974-07-08 1976-03-22 Siemens Ag
JPS54107675A (en) * 1978-02-10 1979-08-23 Matsushita Electric Ind Co Ltd Manufacture for semicnductor device
JPS5669835A (en) * 1979-11-09 1981-06-11 Japan Electronic Ind Dev Assoc<Jeida> Method for forming thin film pattern
JPS5687326A (en) * 1979-12-17 1981-07-15 Sony Corp Method of forming wiring

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1527894A (en) * 1975-10-15 1978-10-11 Mullard Ltd Methods of manufacturing electronic devices
US4385202A (en) * 1980-09-25 1983-05-24 Texas Instruments Incorporated Electronic circuit interconnection system
DE102006035749A1 (de) * 2006-07-28 2008-01-31 Leonhard Kurz Gmbh & Co. Kg Verfahren zur Herstellung mindestens eines Bauteils sowie Bauteil

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5133568A (https=) * 1974-07-08 1976-03-22 Siemens Ag
JPS54107675A (en) * 1978-02-10 1979-08-23 Matsushita Electric Ind Co Ltd Manufacture for semicnductor device
JPS5669835A (en) * 1979-11-09 1981-06-11 Japan Electronic Ind Dev Assoc<Jeida> Method for forming thin film pattern
JPS5687326A (en) * 1979-12-17 1981-07-15 Sony Corp Method of forming wiring

Also Published As

Publication number Publication date
DE2403641A1 (de) 1974-08-01
JPS5236675B2 (https=) 1977-09-17

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