JPS4950878A - - Google Patents

Info

Publication number
JPS4950878A
JPS4950878A JP47093410A JP9341072A JPS4950878A JP S4950878 A JPS4950878 A JP S4950878A JP 47093410 A JP47093410 A JP 47093410A JP 9341072 A JP9341072 A JP 9341072A JP S4950878 A JPS4950878 A JP S4950878A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP47093410A
Other languages
Japanese (ja)
Other versions
JPS525228B2 (US20070149660A1-20070628-C00105.png
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP47093410A priority Critical patent/JPS525228B2/ja
Publication of JPS4950878A publication Critical patent/JPS4950878A/ja
Publication of JPS525228B2 publication Critical patent/JPS525228B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP47093410A 1972-09-18 1972-09-18 Expired JPS525228B2 (US20070149660A1-20070628-C00105.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP47093410A JPS525228B2 (US20070149660A1-20070628-C00105.png) 1972-09-18 1972-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47093410A JPS525228B2 (US20070149660A1-20070628-C00105.png) 1972-09-18 1972-09-18

Publications (2)

Publication Number Publication Date
JPS4950878A true JPS4950878A (US20070149660A1-20070628-C00105.png) 1974-05-17
JPS525228B2 JPS525228B2 (US20070149660A1-20070628-C00105.png) 1977-02-10

Family

ID=14081513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP47093410A Expired JPS525228B2 (US20070149660A1-20070628-C00105.png) 1972-09-18 1972-09-18

Country Status (1)

Country Link
JP (1) JPS525228B2 (US20070149660A1-20070628-C00105.png)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52157768U (US20070149660A1-20070628-C00105.png) * 1976-05-26 1977-11-30
JPS538565A (en) * 1976-07-12 1978-01-26 Nec Corp Semiconductor device
JPS5371584A (en) * 1976-12-08 1978-06-26 Hitachi Ltd Semiconductor integrated circuit device
JPS5418168U (US20070149660A1-20070628-C00105.png) * 1977-06-06 1979-02-06
JPS5596646A (en) * 1979-01-17 1980-07-23 Nec Corp Semiconductor device
JPS5662352A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor integrated circuit device for acoustic amplification circuit
JPS58194363A (ja) * 1982-05-07 1983-11-12 Hitachi Ltd 半導体集積回路装置
JPS60103631A (ja) * 1983-11-11 1985-06-07 Nec Corp 半導体集積回路装置
JPS622627A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 半導体集積回路
JPS6225445A (ja) * 1985-07-25 1987-02-03 Toshiba Corp 半導体集積回路装置
US7414300B2 (en) 2005-09-26 2008-08-19 Mitsubishi Denki Kabushiki Kaisha Molded semiconductor package

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52157768U (US20070149660A1-20070628-C00105.png) * 1976-05-26 1977-11-30
JPS5823945B2 (ja) * 1976-07-12 1983-05-18 日本電気株式会社 半導体装置
JPS538565A (en) * 1976-07-12 1978-01-26 Nec Corp Semiconductor device
JPS5371584A (en) * 1976-12-08 1978-06-26 Hitachi Ltd Semiconductor integrated circuit device
JPS5418168U (US20070149660A1-20070628-C00105.png) * 1977-06-06 1979-02-06
JPS5596646A (en) * 1979-01-17 1980-07-23 Nec Corp Semiconductor device
JPS5662352A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor integrated circuit device for acoustic amplification circuit
JPS6331105B2 (US20070149660A1-20070628-C00105.png) * 1979-10-26 1988-06-22 Hitachi Ltd
JPS58194363A (ja) * 1982-05-07 1983-11-12 Hitachi Ltd 半導体集積回路装置
JPH0416945B2 (US20070149660A1-20070628-C00105.png) * 1982-05-07 1992-03-25 Hitachi Ltd
JPS60103631A (ja) * 1983-11-11 1985-06-07 Nec Corp 半導体集積回路装置
JPH0241904B2 (US20070149660A1-20070628-C00105.png) * 1983-11-11 1990-09-19
JPS622627A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 半導体集積回路
JPS6225445A (ja) * 1985-07-25 1987-02-03 Toshiba Corp 半導体集積回路装置
US7414300B2 (en) 2005-09-26 2008-08-19 Mitsubishi Denki Kabushiki Kaisha Molded semiconductor package

Also Published As

Publication number Publication date
JPS525228B2 (US20070149660A1-20070628-C00105.png) 1977-02-10

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