JPS49105453A - - Google Patents
Info
- Publication number
- JPS49105453A JPS49105453A JP1530573A JP1530573A JPS49105453A JP S49105453 A JPS49105453 A JP S49105453A JP 1530573 A JP1530573 A JP 1530573A JP 1530573 A JP1530573 A JP 1530573A JP S49105453 A JPS49105453 A JP S49105453A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Landscapes
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1530573A JPS5532019B2 (enExample) | 1973-02-07 | 1973-02-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1530573A JPS5532019B2 (enExample) | 1973-02-07 | 1973-02-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS49105453A true JPS49105453A (enExample) | 1974-10-05 |
| JPS5532019B2 JPS5532019B2 (enExample) | 1980-08-22 |
Family
ID=11885079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1530573A Expired JPS5532019B2 (enExample) | 1973-02-07 | 1973-02-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5532019B2 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS571024U (enExample) * | 1980-05-29 | 1982-01-06 | ||
| CN106298557B (zh) * | 2015-05-22 | 2019-08-02 | 中国科学院苏州纳米技术与纳米仿生研究所 | 一种基于Au/In等温凝固的低温键合方法 |
-
1973
- 1973-02-07 JP JP1530573A patent/JPS5532019B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5532019B2 (enExample) | 1980-08-22 |