JPS4845181A - - Google Patents
Info
- Publication number
- JPS4845181A JPS4845181A JP4251571A JP4251571A JPS4845181A JP S4845181 A JPS4845181 A JP S4845181A JP 4251571 A JP4251571 A JP 4251571A JP 4251571 A JP4251571 A JP 4251571A JP S4845181 A JPS4845181 A JP S4845181A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4251571A JPS5443356B2 (en:Method) | 1971-06-16 | 1971-06-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4251571A JPS5443356B2 (en:Method) | 1971-06-16 | 1971-06-16 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7216078A Division JPS5412276A (en) | 1978-06-16 | 1978-06-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4845181A true JPS4845181A (en:Method) | 1973-06-28 |
| JPS5443356B2 JPS5443356B2 (en:Method) | 1979-12-19 |
Family
ID=12638192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4251571A Expired JPS5443356B2 (en:Method) | 1971-06-16 | 1971-06-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5443356B2 (en:Method) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51114079A (en) * | 1975-03-31 | 1976-10-07 | Fujitsu Ltd | Construction of semiconductor memory device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3475234A (en) * | 1967-03-27 | 1969-10-28 | Bell Telephone Labor Inc | Method for making mis structures |
| US3519901A (en) * | 1968-01-29 | 1970-07-07 | Texas Instruments Inc | Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation |
| JPS5026912A (en:Method) * | 1973-07-12 | 1975-03-20 |
-
1971
- 1971-06-16 JP JP4251571A patent/JPS5443356B2/ja not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3475234A (en) * | 1967-03-27 | 1969-10-28 | Bell Telephone Labor Inc | Method for making mis structures |
| US3519901A (en) * | 1968-01-29 | 1970-07-07 | Texas Instruments Inc | Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation |
| JPS5026912A (en:Method) * | 1973-07-12 | 1975-03-20 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51114079A (en) * | 1975-03-31 | 1976-10-07 | Fujitsu Ltd | Construction of semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5443356B2 (en:Method) | 1979-12-19 |