JPH1198507A - Image coder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high through in a frame memory that stores an input image and a local decode image according to the moving image coding represented by the MPEG2. SOLUTION: The coder is provided with a means 54 sub-sampling an image in a pre-stage where an input image is stored in a memory, with a means 70 that stores a sub sampling image (Ps) with different phases is stored in independent areas and with a means 63 that reads an image only from one area and outputs the Ps in the case that processing such as motion detection is applied to the Ps and synthesizes images read from both the areas and outputs the synthesized image in the case of the processing requiring an original image with one pixel accuracy to reduce an overhead of memory access due to read- out from undesired areas. Furthermore, pixels consisting of one word of the memory are formed into a rectangle and the direction of the short sides and a direction of conducting a fast page access (FA) are set identical to effectively use FA realizing fast access and bank switching in a synchronous DRAM and a decrease in the throghput due to read-out of undesired pixel data is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in storage means for holding the contents of an image, and in particular, it is possible to perform input / output with a high throughput when performing processing in compression and expansion of image data. Image storage device.

[0002]

2. Description of the Related Art In recent years, MPEG2 (ISO / I / I) is expected to be applied to broadcasting, communication, and storage media.
There is a digital video coding technology represented by EC13818).

[0003] As is well known, in moving picture coding by MPEG2, as shown in FIG. 3, a frame or a field to be coded by a method called motion compensation is converted from a past or future frame or a similar part of a field. By predicting and encoding the residual, highly efficient encoding is realized. For this reason, in the encoding and decoding processes according to this method, a memory (frame memory) for storing the encoded or decoded image is essential.

In particular, in an encoding system based on MPEG2 which is assumed to be applied to encoding of a moving image having a resolution of a broadcast level or an HDTV (high definition television) level, the throughput required for the frame memory is very high. Will be higher.

[0005] Against this background, Japanese Patent Application Laid-Open No. 8-12395, which is a technical document as an invention related to this technical field, is provided.
Japanese Patent Application Laid-Open No. 3 (1999) discloses a method for allocating pixels and addresses in a frame memory. In the method disclosed herein, as shown in FIG. 13, a plurality of pixels arranged adjacent to one side of an image of one field to be stored are defined as one word, and adjacent pixels are arranged in a direction orthogonal to the word. The address is located.

In a general DRAM, a high-speed memory access called "first page access" is possible between several hundreds of adjacent addresses. By performing such addressing, writing to a frame memory is performed. In addition, unnecessary overhead required for reading is reduced, and high-speed memory access is enabled.

On the other hand, in the motion detection and motion compensation processing in moving picture coding, processing for obtaining a similar area from a very large number of reference image candidate points is required, and the processing amount tends to be enormous. There is. For this reason, many methods for reducing the processing amount of motion detection have been proposed.

For example, in the technique disclosed in Japanese Patent Application Laid-Open No. 8-317409, motion is detected in a reference image and an encoded image whose pixel density is reduced by subsampling or the like, so that a search candidate point is determined. And the processing load is reduced.

[0009]

However, in the above-described motion detection method for a sub-sampled image, the image is mapped to a frame memory by a method as disclosed in Japanese Patent Application Laid-Open No. H8-123953. In this case, the thinned image is also read at the same time in order to read the sub-sampled image, which may cause a substantial memory throughput to be insufficient for reading unnecessary data.

For this reason, it is necessary to take measures such as reducing the memory throughput required by the coding apparatus by taking measures such as narrowing the area in which the motion is detected, and there is a possibility that the coding efficiency is reduced.

Further, usually, a search candidate point for motion detection and motion compensation is often a rectangular area in a field or a frame as shown in FIG. At this time, if one word of the memory is composed of pixels as shown in FIG. 13 which are adjacent to each other in a single direction of the image, depending on the specification of the rectangular area, many unnecessary pixels may be read in order to read out one pixel. Becomes

That is, in FIG. 13, MEM indicates a memory, 1 indicates image data, 2 indicates a pixel data group constituting one word, and 3 indicates a memory access direction. When data is read, for example, the memory MEM is accessed and read in address order, so that the memory bit configuration for each address is “8 ×
Since it has a word configuration of n ″ bits, image data for a plurality of pixels is stored in one word, depending on the configuration bits of the image data per pixel.
If the word is a 32-bit image memory, 1
If a pixel is 4-bit image data, 8 pixels can be stored. If 1 pixel is 8-bit image data, 4 pixels can be stored, and if 1 pixel is 16-bit image data, 2 pixels. That is, it is possible to store as much as possible (the figure shows a four-pixel configuration for one word).

In the case of the frame memory, the image data is stored in units of at least one screen (one frame). If the rectangular area of interest is a part of the screen, the data at the end of the rectangular area is It is more likely that pixel data outside the rectangular area of interest is also included.

As described above, when one word of the memory is constituted by the pixels as shown in FIG. 13, a large number of unnecessary pixels are read in order to read out one pixel depending on the designation of the rectangular area.

[0015] For example, when a memory is configured with S pixels adjacent in the horizontal direction as one word, the left end of the rectangular area serving as a search candidate point is "8m + 7" th (where m
Is an integer) pixel, from the “8m” th to “8m”
Although the pixels up to the +6 ″ th pixel are read from the memory, they are not actually used as search candidate points. This is a large waste of processing, and the throughput at the time of moving image encoding is mischief. To lower.

This is a major problem that must be solved. The present invention has been made in view of the above points, and an object thereof is to realize a memory access having a substantially high throughput at the time of moving image encoding,
An object of the present invention is to provide an image storage device and a memory access method for the image storage device, which can realize an address assignment method and a one-word configuration method that enable motion detection over a wide range.

[0017]

According to the present invention, in order to achieve the above object, the motion of an input moving image in a frame or field to be encoded is referred to a past or future frame or field. To obtain a motion vector indicating the position, predict the frame or field to be encoded from similar parts of past or future frames or fields based on the motion vector, and code the residual In an image coding apparatus of a motion compensation method, an input image is subsampled to obtain a plurality of subsampled images having different phases so that an image used for motion detection for obtaining a motion vector is set as a subsampled image. Means and storing the obtained sub-sampled images of different phases separately for each phase. When the subsampled image storing means and the motion detecting means perform the motion detection processing on the subsampled image, the subsampled image having a specific phase among the subsampled images separately stored for each phase is preferably In the case of a motion compensation process that requires an original image with one-pixel accuracy, each of the sub-sampled images stored separately for each phase is read and synthesized. And control means for controlling the output so as to be output to the motion compensation means.

According to the present invention, a plurality of sub-sampled images having different phases are obtained by sub-sampling an input image so that an image used for motion detection for obtaining a motion vector is a sub-sampled image. The sub-sampling images of different phases are stored separately in the sub-sampling image storage means separately for each phase, and when the motion detecting means performs the motion detection processing on the sub-sampled images, the independent Out of the stored sub-sampled images, a sub-sampled image of a specific phase is read out and output to be given to the motion detecting means.
In the case of motion compensation processing that requires pixel-accurate original images,
By controlling each sub-sampled image stored separately for each phase to be read, synthesized, output, and provided to the motion compensating means, memory access overhead caused by reading unnecessary areas is reduced. Reduce costs. In addition, pixels constituting one word of the memory are rectangular, and the direction of the short side is the same as the direction of the first page access. By doing this,
It is possible to effectively use the first page access that can realize high-speed access and the bank switching in the synchronous DRAM, and to suppress a decrease in throughput due to unnecessary pixel data reading.

Also, there is provided a means for setting a plurality of adjacent pixels of the sub-sampled image to one word, and when reading and using the image, the sub-sampled image is used to realize motion detection. This can reduce unnecessary reading of pixels in the processing.

Further, according to the present invention, a synchronous DRAM is used as a memory, and an image forming one word of this memory is represented by m × n.
By making the rectangle of pixels (m and n are integers), it is possible to reduce unnecessary pixel reading regardless of the search range at the time of motion detection.

Further, according to the present invention, by arranging the addresses so that the first page can be accessed in a direction parallel to the short side of the rectangle forming one word, a high speed first page can be obtained when accessing the rectangular search area. It is possible to increase the number of words that can be accessed by access, and at the same time, to minimize page switching of a DRAM in which overhead occurs and bank switching of a synchronous DRAM.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention has been made so that when reading out pixel data from an image memory for storing image data for a plurality of pixels in one word, unnecessary pixels in the word need not be read out. To make it possible,
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a detailed configuration of the memory control unit 16 in the system of the present invention, and FIG. 2 is a block diagram showing a configuration of an encoding apparatus as the system of the present invention using the memory control unit 16. It is.

As shown in FIG. 1, the memory controller 16 includes a scan converter 51, byte / word converters 52 and 55,
56, word / byte conversion units 58, 59, address control units 53, 61, 67, subsampling execution unit 54, multiplexers (MUX) 57, 64, SRAMs 60, 62, 6
5, 66, 68, control signal generator 63, memory bus 69
It is composed of Reference numeral 70 denotes an external image memory.

The scan converter 51 scan-converts a given local decoded image. The byte / word converter 52 converts the data output from the scan converter 51 into a byte / word converter. I have to do it. Byte / word converter 52,
Numerals 55 and 56 convert input pixel information (image data) having a predetermined bit configuration into information (data) having a predetermined bit width by a predetermined number of bytes.
Reference numerals 62 and 68 denote memories for temporarily saving data,
It holds data of a predetermined bit width given from the corresponding one of the word conversion units 52, 55, 56.

Multiplexers (MUX) 57 and 64 multiplex and output given data. Of these multiplexers 57 and 64, the multiplexer 64 is an SRAM 6
The data read from 0 and 62 are multiplexed and output, and the multiplexer 57 is for multiplexing and outputting the outputs of the word / byte converters 58 and 59.

The SRAMs 65 and 66 include a multiplexer 64.
The word / byte converters 58 and 59 convert read data from the corresponding one of the SRAMs 65 and 66 from the word configuration to the byte configuration and output the converted data. .

The address control unit 61 includes SRAMs 60 and 62
Address control and read / write (write / read) control.
Is used to control the address of the SRAM 68 and to control the read / write of the SRAM 68.
This is for performing address control and read / write control of M66.

The sub-sampling execution unit 54 converts the input image PIN into two different sub-sampled images Ps
1 and Ps2, one of which is applied to the byte / word converter 55 and the other to the byte / word converter 56. The byte / word conversion units 55 and 56 convert the data output from the sub-sampling unit 54 into byte / word conversions. The control signal generator 63 is for generating a control signal for address control and read / write control of the image memory 70,
The image memory 70 stores and reads data under the control of control signals for address control and read / write control output from the control signal generation unit 63.

As shown in FIG. 2, the coding apparatus according to the present embodiment includes an input image processing unit 11, a memory control unit 16, a motion detection unit 12, a motion compensation unit 13, a coding unit that performs DCT and quantization. It comprises a unit 14, a bit stream output unit 15, a local decoded image generation unit 17 for performing inverse quantization and inverse DCT, and a memory 18 connected to the outside.

Of these, the input image processing unit 11 receives the image data of the moving image as the input image 10 and performs necessary pre-processing on it, and the memory control unit 16
1 has the configuration described with reference to FIG. 1 and is used to perform control for rearranging the preprocessed image data and storing the rearranged data read out from the memory 18 in the memory 18. belongs to. The memory 18 here corresponds to the image memory 70 in FIG.

The motion detecting section 12 searches for a portion where the two images are most similar, and outputs the position to the memory control section 16 as a motion vector. The motion compensating unit 13 receives both the image data of the local decoded image Plc and the encoded image, performs motion detection and motion compensation, obtains the residual, and sends the obtained residual together with the motion vector to the encoding unit 14. It performs the process of passing. The encoding unit 14 converts the data from the motion compensation unit 13 into D
The data is encoded and output by performing processing such as CT (orthogonal transformation) and quantization.
Numeral 5 is for outputting the encoded data as a bit stream.

The local decoded image generating section 17 decodes the bit stream output from the bit stream output section 15 and generates a local decoded image Plc.
It performs CT and the like.

Next, the operation of the present apparatus having the above configuration will be described.
In the above configuration, the input image 10 which is data of a moving image obtained by an imaging device or the like is input to the input image processing unit 11, where necessary preprocessing is performed, and the input image 10 is transmitted to the memory control unit 16. Can be

The memory controller 16 controls the memory 18 so that the preprocessed input image 10 is stored in the memory 18. As a result, the preprocessed input image 10 is stored in the memory 18. The memory control unit 16 also provides the preprocessed input image to the motion detection unit 12.

The image stored in the memory 18 is read out by the reading control by the memory control unit 16 after a lapse of the appearance of several frames in time, and is sent to the motion detecting unit 12.

The motion detector 12 reads the encoded image from which motion is to be detected, and the sub-sampled image written in the memory 18 from the input image processor 11 as a reference image from which the motion is detected. Then, by being provided to the motion detection unit 12, the motion detection unit 12 compares the two types of sub-sampled images read from the memory 18 and searches for a portion where these two images are most similar. , And outputs the position to the memory control unit 16 as motion vector data.

In the memory control unit 16, the motion detection unit 1
The motion vector obtained in 2 is stored in another area of the memory 18 different from the area where the input image is stored. The motion vector data stored in the memory 18 is sent to the motion compensator 13 together with the rectangular area in the image to be coded when actually coding the image.

The local decoding image Plc stored in an area different from the storage area of the input image and the motion vector data in the memory 18 is encoded by the motion compensating unit 13 in order to perform more accurate motion detection. Sent at the same time as the converted image.

The local decoded image Plc is generated by decoding the bit stream of the encoded data output from the encoding unit 14 by the local decoded image generation unit 17 and stored in the memory 18. is there. The local decoded image Plc is stored in an area different from the storage area of the input image and the motion vector data in the memory 18 under the control of the memory control unit 16.

When the local decoded image Plc is provided together with the encoded image, the motion compensator 13 performs highly accurate motion detection and motion compensation, and the residual (difference component) is obtained.
Is obtained, and the obtained residual is sent to the next-stage encoding unit 14 together with the obtained highly accurate motion vector.
The encoding unit 14 performs DCT (orthogonal transformation) processing on both data and quantizes the result. Then, by performing such processing, encoding is performed (acquisition of encoded information).

The coded information thus obtained is sent to the bit stream output unit 15 and, when the image is used as a reference image for another image, to the local decoded image generation unit 17. Then, the local decoded image is generated by decoding the bit stream in the local decoded image generating unit 17.

Since this image is used as a reference image by the motion compensating unit 13, the image is passed through the memory control unit 16 to the memory 18.
Is stored in Here, the above-mentioned memory 18 is, for example, a memory element “TC59S161” manufactured by Toshiba Corporation.
It is constituted by a commercially available synchronous DRAM such as a memory element having a model number called a 6 "series.

"TC59S161" which is a synchronous DRAM
In the 6 "series, one word is composed of 16 bits,
It has a storage capacity of 1,048,576 words. Since this is a synchronous DRAM having a storage capacity of 1,048,576 words, four DRAMs are connected in parallel in this embodiment to realize a bit width of "64 bits".

The synchronous DRAM has two storage areas ("bank 0" and "bank 1") called banks, and gives a command in synchronization with a clock supplied from the outside to give two banks. Memory access can be performed almost independently.

The command given to the synchronous DRAM is "A
"active", "Read" (read),
“Write” (write), “Precharge”
(Pre-holding) and the like are typical. In the case of reading, as shown in a control example in the timing chart of FIG.
By giving these commands alternately to "bank 0" and "bank 1", memory access without page switching overhead can be performed.
However, there is a restriction that each command for the same bank must be issued at intervals of a predetermined time or more. Here, in FIG. 6, “act0” is an “active” command for “bank 0”, and “Read0” is “Rea” for “bank 0”.
d) command, “Pre0” is a “Precharge” command for “bank 0”, and “act0”
“1” is an “active” command for “bank 1”, and “Read1” is a “Reactive” command for “bank 1”.
ad ”command,“ Pre1 ”is a“ Precharge ”command for“ bank 1 ”, and“ D
“x” is “data” output from a memory bank belonging to “bank A”, and “Dy” means “data” output from a memory bank belonging to “bank B”.

As described above, in the case of a synchronous DRAM,
Although there is a restriction that each command for the same bank must be issued at intervals of a predetermined time or more, restrictions on commands given to the synchronous DRAM in this embodiment are described below. 9 clocks between Active and Active in the same bank 3 clocks between Active and Read / Wrote in the same bank 5 clocks between Active and Precharge in the same bank 5 clocks between Precharge and Active in the same bank 3 clocks between different banks 3 clocks between Read / Write → Active and 2 clocks between Active → Active between different banks Therefore, in order to realize a high-throughput memory access in a synchronous DRAM, [1]. By avoiding continuous page switching of the same bank and accessing two banks alternately, overhead at the time of page switching is reduced.

[2]. By increasing the number of words of the first page access in the same bank, overhead at the time of bank switching is reduced. Such a device is required.

In the above configuration, the memory control unit 16
There are two types of images to be input to the device, an input image PIN and a local decoded image Plc. The image information output by the memory control unit 16 includes an encoded image Plc and a reference image that are sub-sampled “2: 1” for the motion detection unit 12 of the image encoding device shown in FIG. Then, for the motion compensation unit 13 of the image encoding device, there is an encoded image with one-pixel accuracy (not sub-sampled) and a local decoded image Plc as a reference image. These are output from the memory control unit 16 to the motion detection unit 12 and the motion compensation unit 13.

The motion compensator 13 also receives, as a result of the motion detection from the motion detector 12, data of a motion vector with two-pixel accuracy. In general, as shown in FIG. 5, an input image PIN as a moving image is input in field units and by raster scan. That is, a video signal (image signal) of the television system is obtained by raster scan of a frame image, but since the raster scan here is performed by interlaced scan and is line sequential,
It has a two-field configuration of an odd field by scanning an odd scanning line position and an even field by scanning an even scanning line position. In FIG. 5, the odd field is the image of the top field, and the even field is the image of the bottom field. Accordingly, as shown in FIG. 5, the input image PIN is changed from “top field” → “bottom field” →
By repeating “top field” → “bottom field” →, the image data obtained in the field unit in the scanning order of the raster scan is input every moment as the input image PIN.

On the other hand, in the image encoding device, the image information output from the memory control unit 16 for the image encoding process is a coarse image (sub-sampled) except for the encoded image supplied to the motion compensation unit 13. (An image decimated by）).

Therefore, the memory control unit 16 of the present embodiment
As shown in FIG. 7, the input image PIN is divided into two kinds of different sub-sampled images Ps1 and Ps2 by its own sub-sampling execution unit 54 shown in FIG. That is,
The input image PIN having one-pixel accuracy is input as image data in the form of a bit stream by raster scan. The image data provided by the bit stream by raster scan is obtained by sampling every other pixel in the scanning progression order. Of the image, a sub-sampled image Ps1 formed by only the odd-numbered pixels and a sub-sampled image Ps2 formed by only the even-numbered pixels
Divide into types.

Each of these sub-sampled images Ps1 and Ps2 in the sub-sampling execution unit 54
Since the image is sequentially thinned out one pixel at a time, the data amount is half of the input image PIN and the accuracy is a rough image of 1/2. I do. On the other hand, since the input image PIN has the original pixel accuracy, it is referred to as one-pixel accuracy in the sense that it is an image maintaining the original accuracy of one pixel unit.

One (for example, Ps1) of the divisions is supplied to a byte / word converter 55, and the other (for example, Ps2) is supplied to a byte / word converter 56. In the byte / word converter 55, the “8-bit” pixel information of the given sub-sampling image Ps 1 is collected into “8-byte” data to form “64-bit” width information. Write.

In the byte / word converter 56, pixel data of "8 bits" for the given sub-sampling image Ps2 is grouped into "8 bytes" to obtain information of "64 bits" width. Memory SRAM60
Write to

When a certain number of words are stored in the SRAM 62 and the SRAM 60, respectively, the address control unit 61 sets the image data of the SRAM 62 as "Ps1 unit group input image data" and the image data of the SRAM 60 with "Ps2 The unit group input image data is written to each of the memory areas in the memory 18 through the memory bus 69. Thus, the memory 18 stores two types of unit group input image data, the Ps1 unit group input image data and the Ps2 unit group input image data.

When the input image is output as a reference image and a coded image for use in the motion detection unit 12, a coarse image may be used since the motion detection itself may be rough, and therefore, the above-mentioned written image is used. One of the two types of data, the Ps1 unit group input image data and the Ps2 unit group input image data, is read out and written to the SRAM 65 or 66 via the memory bus 69, and is provided corresponding to the SRAM 65 or SRAM 66. After word / byte conversion is performed by the word / byte converter 58 or the word / byte converter 59, the word / byte conversion is provided to the motion detection unit 12.

On the other hand, the coded image output to the motion compensating unit 13 is required to have accuracy of one pixel since it is used for motion compensation, so that it needs to have one pixel accuracy. By reading out two types of data, ie, unit group input image data and Ps2 unit group input image data,
One of them is transferred to the SRAM 65 through the memory bus 69,
Then, the other is written into the SRAM 66. That is, the two types of input images read from the two areas are written to the SRAMs 65 and 66 by the same number of words. Then, the information written in the SRAMs 65 and 66 is given to the multiplexer 57 to be multiplexed and output to the motion compensator 13.

On the other hand, by decoding the bit stream of the encoded data output from the encoding unit 14 in the local decoded image generation unit 17, the generated local decoded image Plc is converted into a macro block as shown in FIG. A rectangular area Zn having a size of 16 × 16 pixels is input as a whole and output as a reference image of the motion compensation unit 13 with one-pixel accuracy (Pcel indicates a pixel).

The area (rectangular area Zn) of the reference image of the motion compensator 13 changes with one-pixel accuracy according to the motion vector obtained by the motion detector 12 at the preceding stage. for that reason,
It is necessary to be able to extract (read) the image data of the corresponding area of the reference image in response to the change in the unit of one pixel precision that changes according to the motion vector.

Therefore, in the memory control section 16 of the present embodiment, as shown in FIG.
The local decoded image Plc for each field is converted into a unit of 4 pixels in the horizontal direction and 2 pixels in the vertical direction.
2 and the area of “4 × 2” pixels as one word
Write to 68. That is, the local decoded image Plc
Converts each pixel (Pcel1 to Pcel16) of each odd line into an array of four horizontal pixels and two vertical pixels in order, and arranges them in a 4-row, 4-column arrangement, starting at the upper left and starting at the lower end and reaching the lower end. Then, it is replaced in such a way that it returns to the top again, proceeds from the top to the bottom, returns to the top again, and so on in the order of 4 rows and 4 columns.

For each pixel (Pcel1 to Pcel16) in each even line of the local decoded image Plc,
Each of them is sequentially converted into an array of 4 horizontal pixels and 2 vertical pixels, and the array is returned starting from the upper left position in the arrangement of 4 rows and 4 columns to the lower end and reaching the lower end. 4 in the order of returning upward
Replacement is performed by filling in the arrangement position of row 4 column in order.

The arrangement of the above-mentioned four rows and four columns for the data of the odd-numbered lines is changed to the upper part and the arrangement of the four rows and four columns for the data of the even-numbered lines is arranged below the arrangement. The local decoded image Plc is obtained as the converted local decoded image Plcx in FIG. The local decoded image Plc is written to the SRAM 68 in such a manner.

This is an arrangement having the following advantages. That is, in the macroblock (unit block composed of 16 × 16 pixels), the pixel data of the local decoded image Plc arranged in the raster scan order is such that the pixels of the first line, which is an odd line, are 4 horizontal pixels and 2 vertical pixels. The pixel of the third line, which is an odd line, is converted to a unit and is converted to a unit of four horizontal pixels and two vertical pixels at a position of 100-1 in FIG. A pixel on a certain fifth line is converted into a unit of four horizontal pixels and two vertical pixels, and a pixel on a seventh line, which is an odd line, is converted into a unit of four horizontal pixels and two vertical pixels at the position of 100-3 in FIG. The pixel of the ninth line, which is an odd line, is converted into a unit of four horizontal pixels and two vertical pixels at the position of 100-4 in FIG. 9, and at the position of 100-5 in FIG. 25 lines of pixels Horizontal 4 pixels, is converted into the vertical 2-pixel units the position of 100 - 13 in FIG. 9, ... ... pixel horizontal 4 pixels of the first 31 lines is odd lines, vertical 2
The pixels are converted into pixel units and arranged at positions 100-15 in FIG. 9, respectively, and the pixels of the second line, which is an even-numbered line, are converted into four horizontal pixels and two vertical pixels, and At the position of 100-17, the pixel of the fourth line, which is an even line, is converted into a unit of four horizontal pixels and two vertical pixels, and at the position of 100-18 in FIG. 9, the pixel of the sixth line, which is an even line, is horizontal. The pixel of the eighth line, which is an even-numbered line, is converted into a unit of 4 horizontal pixels and 2 vertical pixels at a position of 100-19 in FIG. At the position, the pixel of the 26th line which is an even line is converted into a unit of 4 horizontal pixels and 2 vertical pixels, and at the position of 100-24 in FIG. FIG. 9 is converted into two vertical pixels. , At the position of 100-28,..., The pixel of the 36th line, which is an even-numbered line, is converted into a unit of 4 pixels in the horizontal direction and 2 pixels in the vertical direction.
Are converted to the converted local decoded image Plcx. As a result, in the converted local decoded image Plcx having a total of 8 rows and 4 columns, the upper 4 rows and 4 columns are the top field Ftop, and the lower 4 rows and 4 columns are the array of the bottom field Fbtm. When the data in the vertical direction (column direction) is extracted, the data is obtained as a data arrangement in the raster scan order, and further, as a pair corresponding to the top field (odd field) and the bottom field (even field) in that order. . This makes it possible to easily select and extract an image data sequence that matches the reference image area no matter where in the field the reference image area comes.

As in the case of the input image PIN, when the number of words in the SRAM exceeds a certain amount, it is written to the memory 70 (corresponding to the memory 18 in FIG. 2) through the memory bus 69. Then, when writing for one field, as shown in FIG. 10, of the “4 × 2” pixels forming one word,
At the same time as arranging addresses so that DRAM first page access is possible in the vertical direction with a small number of pixels,
Different banks are arranged in the horizontal direction.

As a result, when reading a rectangular area in a field requested by the motion compensator 13, the number of words to be read / written by one page access increases, and the overhead due to page switching and bank switching can be suppressed. Become. In addition, by making one word a rectangular area of “4 × 2” pixels, regardless of where the reference image required by the motion compensation unit 13 is located, overhead caused by reading unnecessary pixels is obtained. Can be suppressed.

For example, if the rectangular area of the reference image requested by the motion compensator 13 has a size of “20 × 12” pixels, if one word is “8 × 1” pixels, the number of words required for reading is a maximum. "4 horizontal words x 12 vertical words"
And the total is "48 words".

On the other hand, in the case of this embodiment, the maximum is “horizontal 6 words × vertical 7 words”, and the total is “42 words”.
The same processing can be performed by reading the data. FIG. 11 shows an example of a command to the synchronous DRAM when the direction in which the first page can be accessed is the horizontal direction. FIG. 11 is a timing chart of the control operation required to read 42 words. When the first page access is possible in the horizontal direction, the read control to the synchronous DRAM is performed in such a manner that 42 words are read. It can be seen that 55 clocks are required for this.

On the other hand, in the case of the present embodiment, since the first page access is possible in the vertical direction, the operation is as shown in FIG. 12, and the synchronous DRA in this case is used.
The read control to M is 49 clocks as shown in the figure, and it can be seen that the same processing can be performed with the 49 clocks.

As described above, according to the present invention, in a moving picture coding apparatus represented by MPEG2, in a frame memory for storing an input picture and a local decoded picture,
In order to realize a high throughput, in the present invention, a means for subsampling an image is arranged before storing an input image in a memory, and means for storing subsampling images of different phases in independent areas; When processing such as motion detection is performed on the extracted image, a sub-sampled image is output by reading from only one area, and when processing that requires an original image with one pixel accuracy is required, By combining and outputting the read images, the overhead of memory access caused by reading unnecessary areas is reduced.

Further, the pixels constituting one word of the memory are rectangular, and the direction of the short side thereof is made the same as the direction of the first page access.
In addition to the effective use of the bank switching in the above, the reduction in throughput due to unnecessary pixel data reading is suppressed.

Therefore, the present invention relates to a moving picture coding apparatus represented by MPEG2, which is used in a frame memory for storing an input picture and a local decoded picture.
High throughput can be realized.
Note that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications.

[0073]

As described above, according to the present invention,
In moving image coding, sub-sampling of images to be written is performed in advance, sub-sampling images with different phases are obtained and saved separately, so that processing such as motion detection targeting sub-sampling images can be performed. Thus, the efficiency of reading required images can be increased.

Further, according to the present invention, by setting a rectangular pixel group in an image to be stored to be one word, the readout efficiency in reading out a rectangular area in the image is improved, and the rectangular shape forming one word is improved. By arranging adjacent addresses that can be accessed in the first page in a direction parallel to the short side of the memory, the number of words to be written and read by the first page access is increased, and page switching of the DRAM, which becomes an overhead at the time of memory access, can be performed. It is possible to reduce a decrease in throughput due to switching of banks of the synchronous DRAM.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the present invention, and is a block diagram of a main part configuration showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining the present invention, and is a block diagram of an encoder system using the embodiment of FIG. 1 in the present invention.

FIG. 3 is a diagram for explaining the present invention, showing a concept of motion compensation.

FIG. 4 is a diagram for explaining the present invention, showing an example of a search range for motion detection.

FIG. 5 is a diagram for explaining the present invention, showing the input order of input images in the embodiment of the present invention.

FIG. 6 is a diagram for explaining the present invention, showing an example of read processing in a synchronous DRAM in the system of the present invention.

FIG. 7 is a diagram for explaining the present invention, showing a method for storing an input image in the embodiment of the present invention.

FIG. 8 is a diagram for explaining the present invention, and is a diagram showing an input order of local decoded images in the embodiment of the present invention.

FIG. 9 is a diagram for explaining the present invention, showing a method of storing a locally decoded image in the embodiment of the present invention.

FIG. 10 is a diagram for explaining the present invention, and is a diagram showing address mapping of a locally decoded image in the embodiment of the present invention.

FIG. 11 is a diagram showing a method of accessing a synchronous DRAM when first page access is possible in the horizontal direction.

FIG. 12 is a diagram for explaining the present invention, showing a method of accessing a synchronous DRAM according to the embodiment of the present invention;

FIG. 13 is a diagram showing a method of using a memory in a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pixel data 2 ... Pixel data group which comprises one word 10 ... Input image 11 ... Input image processing part 12 ... Motion detection part 13 ... Motion compensation part 14 ... Encoding part 15 ... Bit stream output part 16 ... Memory control part 17 Local decode image generators 18, 70 Image memory 51 Scan converters 52, 55, 56 Byte / word
d) Converters 53, 61, 67 SRAM address controller 54 Subsampling image generator 57, 64 Data multiplexer 58, 59 Word / byte converters 60, 62, 65, 66 , 68 SRAM SRAM 63 memory control signal generator 69 memory data bus

Claims (2)

[Claims] 1. A motion vector in an encoding target frame or field of an input moving image is detected by referring to a past or future frame or field to obtain a motion vector indicating the position thereof. The frame or field to be encoded based on
In a motion compensation type image encoding device that predicts from a similar portion of a past or future frame or field and encodes the residual, an image used for motion detection to obtain a motion vector is expressed by:
The input image is 1 / n (n
Means for obtaining a plurality of sub-sampled images having different phases by subsampling into integers, sub-sampled image storing means for storing the obtained sub-sampled images having different phases separately for each phase, and When the detecting means performs the motion detection process on the sub-sampled image, the sub-sampled image of a specific phase is read out from the independently stored sub-sampled images classified by phase, and is output to output. In the case of the motion compensation processing in which the original image with one pixel accuracy is given to the detection means, each of the independently stored sub-sampled images divided for each phase is read out, synthesized, and outputted to the motion compensation means. An image encoding apparatus, comprising: control means for performing control so as to provide the image data. 2. The motion of an input moving image in a frame or field to be coded is detected by referring to a past or future frame or field, and a motion vector indicating the position is obtained. The frame or field to be encoded based on
In a motion-compensated image encoding apparatus that predicts from a similar part of a past or future frame or field and encodes the residual, a plurality of pixel data of pixels constituting a field or frame of the moving image Address generation means for generating a single address; and pixel data storage means for storing a plurality of collected pixel data at a predetermined address, wherein the image data storage means can be continuously accessed without overhead. When the memory has a predetermined storage length, the address generation means allocates one address to p pixels in the horizontal direction and q pixels in the vertical direction (p and q are integers),
In the case of p <q, the storage area that can be continuously accessed is expanded in the horizontal direction, and in the case of p> q, the storage area is continuously expanded.
An image encoding apparatus characterized in that image data read by read access according to the storage area expansion can be optimally used as the reference or the similar part.