JPH1198480A - Digital broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To update additional information while minimizing power consumption in the standby state in the case of receiving a digital broadcast whose additional information is periodically updated. SOLUTION: The receiver is provided with a 1st processor 10 that extracts additional information, a storage means 118 that collects the additional information, and a 2nd processor 106 that has a low power consumption mode and a usual power mode and controls a circuit for viewing according to a prescribed program and the additional information. The 1st processor 105 informs the extraction of the additional information to the 2nd processor 106 and the 2nd processor 106 in the low power consumption mode in the standby state changes the mode into the normal power mode upon the receipt of extraction of the additional information from the 1st processor 105 and writes the additional information extracted by the 1st processor 105 to the storage means 118 and changes the mode to the low power consumption mode after the end of write. Thus, the additional information is updated by minimizing the power consumption in the standby state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a digital broadcast receiving device used in a digital broadcast system.

[0002]

2. Description of the Related Art In recent years, video and audio digital signal processing technology has made remarkable progress, and digital broadcasting,
Systems are being actively developed around the world to realize the integration of broadcasting and communications.

[0003] Among these, one of the most important technologies is a video / audio compression technology. As this compression technique, MP
EG, JPEG, H.E. 261 was the main part.
In particular, ISO / IEC13818-1 (Moving Picture
Coding Experts Group (ISO / IEC JTC1 /
The compression method proposed in SC29 / WG11) is being studied for global standardization of broadcasting, communication, and storage media.

In the above ISO / IEC13818-1,
In addition to video compression, program video, audio, and multiplexed bit streams compressed for each data are broadcasted,
The content of the control part for receiving the specified program on the receiver side is also solidified.

[0005] The multiplex control of bit streams for broadcasting and communication according to ISO / IEC13818-1 will be briefly described with reference to FIGS.

FIG. 15 shows a model of one system of video and one system of audio for a packet formation method. First, both video and audio are divided into units of one frame, and a header is attached to each of the frames to form a PES (Packetized E-mail).
lementary stream). This PES is of variable length. Furthermore, in order to time-multiplex video and audio, each PES is basically divided into 184 bytes and packetized, and a 4-byte header is added to each PES to form a 188-byte TP (Transport Packet). FIG. 15 shows a case where multiplexing of video and audio is considered, but in practice, data such as additional data of a program and program information are also TP-converted and time-multiplexed.

Next, a method of forming a bit stream as a broadcast will be described with reference to FIG.

In FIG. 16, programs A and B indicate one program, and ECM (Entit) transmitted by multiplexing devices 1 and 2 for each of two video systems, two audio systems, and each program.
lementControl Messages) 1 system and program
One map table (PMT: ProgramMap Table) is multiplexed and output as TS (A) and TS (B). Here, video, audio, and ECM indicate video data, audio data, and additional information data, respectively, and PMT indicates a packet ID (Packet ID) for distinguishing each of the video data, audio data, and additional information data.
And a description about the program. The multiplexing device 3 adds the program association table (PAT: Pro) to the TS (A) and TS (B) of these programs A and B.
gram Association Table), Network Information Table (NIT)
, Conditional access table (CAT: Condi
National Access Table) and individual user key information (EMM (Entitlement Management Messages) information) sent to individual receivers required to view the program
Are multiplexed and output as TS corresponding to transmission channel data.

In the above-mentioned digital broadcasting system, the individual user key information is regularly updated on the transmitting side in order to facilitate the viewing management of the subscriber. For this reason, it is necessary for the receiving side to monitor the update of the individual user key information so that viewing can be started immediately when the user enters the viewing state from the standby state. In this case, it is possible to cope with the problem by keeping the sub-power supply of a necessary circuit such as a processor for managing the individual user key information always on. However, this consumes power wastefully.

[0010]

As described above, in the digital broadcasting system, when the additional information such as the individual user key information is periodically updated, the receiving side monitors the update of the additional information. If a method is used in which the sub power supply of a necessary circuit is always kept on, power is wasted.

[0011] It is an object of the present invention to update the additional information while receiving the digital broadcast in which the additional information is periodically updated while minimizing the power consumption in the standby state. It is an object of the present invention to provide a digital broadcast receiving apparatus capable of promptly starting viewing at the time of transition to.

[0012]

In order to achieve the above object, a digital broadcast receiving apparatus according to the present invention includes at least information for program viewing or mail information multiplexed from a digital broadcast signal to the signal. A first processor for extracting additional information, storage means for collecting additional information, a low power consumption mode and a normal power mode, and a circuit for viewing and controlling a circuit according to a predetermined program and additional information; The first processor extracts, from the digital broadcast signal, additional information that meets a preset filter condition, and informs the second processor that the additional information has been extracted. Then, the second processor is in a low power consumption mode in its standby state, and is notified that the first processor has extracted additional information. In this case, the mode is changed from the low power consumption mode to the normal power mode, and after the change to the normal power mode, the additional information extracted by the first processor is transferred to the storage unit and written therein. And returning to the low power consumption mode again.

According to this configuration, in the standby state,
When extracting the additional information for viewing the program from the digital broadcast signal, the first processor notifies the second processor that the additional information has been extracted. Then, the second processor is converted from the low power consumption mode to the normal power mode, transfers the additional information from the first processor to the storage means and accumulates the information. After the accumulation is completed, the second processor returns to the low power consumption mode. You will return to the mode.

As a result, in the standby state, the second processor operates in the normal power mode only when the additional information is detected and stored in the storage means, and the additional information is stored in the storage means. The additional information can be updated while minimizing the power consumption, so that the viewing can be started promptly at the transition from the standby state to the viewing state.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of a digital broadcast receiving apparatus according to an embodiment of the present invention. In FIG. 1, a terminal 100 has a BS (Broadcasting Satellite), C
S (Communication Satellite), CATV (Cable Telev
ision), and a digitally modulated broadcast signal such as a terrestrial wave is supplied. The broadcast signal supplied to the terminal 100 is converted into a digital signal by an A / D converter 101, subjected to a demodulation process by a demodulation circuit 102, and
In 3, the FEC is decoded and supplied to the descramble circuit 104. The descrambling circuit 104 descrambles the output of the FEC decoder 103, and its output signal is supplied to a stream depacket processor 105.

This stream depacket processor 1
05 indicates that the output of the descrambling circuit 104 is ISO-
13818-1 and depacket processing of transport packets specified by ETSI. The audio PES signal in the depacketized signal is transmitted to the MPEG audio decoder 107 in accordance with the PID specified by the host processor 106. Will be transferred. The MPEG audio decoder 107 decodes the transferred audio PES signal and converts it into an audio signal. This audio signal is output to a sound reproducing device (not shown) via a terminal 108.

Also, of the signals depacketized by the stream depacket processor 105, the video P
The ES signal is transferred to the MPEG video decoder 109. The video PES signal is output from the MPEG video decoder 10.
9, the decoding process is performed in the same way as the voice, and the NTS
The encoding process is performed in the C encoder 110, and the video signal is output to a monitor (not shown) via a terminal 111 as a video signal. At this time, the SDRAM 112
It is used as a buffer for the data of the PEG audio decoder 107 and the MPEG video decoder 109.

In the stream depacket processor 105, the additional information and the like depacketized are transferred to the host processor 106. When the power is turned on, the host processor 106 downloads a program from the ROM 113, starts various application software 106a, and executes a sub-MPU (Micro Processin
g Unit) The following control is performed based on the information input by the viewer sent from 114 and the additional information sent from the stream depacket processor 105.

(1) High-speed interface 115
Controls the input and output of data.

(2) Create viewing record data and send the modem 1
16 to send the viewing record data to the center of the provider.

(3) When receiving an interactive broadcast such as a questionnaire, data such as an answer is transmitted using the modem 116.

(4) When a pay-per-view (PPV) is used by a viewer, viewing record data is created and stored in the smart card 117.

(5) When a scrambled program is received, key information of the program is transmitted to the smart card 117.
Out of the program so that the program can be viewed.

(6) The additional information sent from the stream depacket processor 105 is stored in a DRAM (Dynamic R).
andom Access Memory) 118.

(7) The stream depacket processor 105 is set to execute depacket processing.

(8) MPEG audio decoder 10
7. Perform decoding control of the MPEG video decoder 109.

(9) When the stream depacket processor 105 acquires the EMM and ECM, the version is managed. If the version is up, the EMM and ECM are replaced with old information and personal information is transmitted from the EMM. , E
The program information is extracted from the CM and stored in the smart card 117 as key information.

(10) The period for acquiring the individual EMM is determined based on the transmission period information of the individual EMM and the reception timing of the individual EMM.

The digital broadcast receiving apparatus has a viewing state in which the viewer is watching and a standby state in which viewing is stopped. In the viewing state, the power of all the circuits is turned on to perform an operation that allows viewing (normal operation), and in the standby state, the A / D
From the converter 101 to the stream depacket processor 1
Until 05, the DRAM 118 is turned on in the same manner as the viewing state, and the normal operation state is maintained. At this time, the host processor 106 is in the low power consumption mode, the other parts are in the power-off state, and may be turned on as needed to operate.

The smart card 117 is an ISO7 card.
A card as defined in 816 or equivalent. Key information for viewing a specific program is stored in the smart card 117 in advance. When the specific program is viewed using the key information, the viewing record data of the specific program is stored. Is written.

The low power consumption mode of the host processor 106 means a mode in which the operation of the host processor is partially stopped to reduce power consumption, but a mode in which an external bus release request can be accepted or a mode comparable thereto. I do. Further, the host processor 106 has a built-in timer for executing a periodic process.

Hereinafter, the operations of the stream depacket processor 105 and the host processor 106 in the standby state will be described in different cases.

(1) When notifying the viewing record data to the provider center using the modem 116, the host processor 106 operates as shown in the flowchart of FIG.

First, when a time specified in advance by the timer comes, a data transmission operation is started (step S1).
1) Change from the low power consumption mode to the normal power mode (step S12). Then, the smart card 117 and the modem 116 are turned on to be driven (steps S13 and S14), and the viewing record data is extracted from the smart card 117 (step S15).

Next, a call is made to the modem 116 to connect the above-mentioned center to the communication line (step S16), and the viewing record data extracted from the smart card 117 is transmitted to the center through the modem 116 (step S1).
7). Thereafter, the power supply of the modem 116 and the smart card 117 is turned off (step S18), and the mode is again shifted to the low power consumption mode (step S19).

(2) When the EMM information sent from the stream depacket processor 105 is stored in the DRAM 118, the stream depacket processor 105 and the host processor 106 are used as a countermeasure 1.
Operates as shown in the flowchart of FIG.

First, the stream depacket processor 105 sets an E that matches a preset filter condition.
When the MM information is received (step S21), the host processor 106 is notified that the EMM information has been received (step S22). Upon receiving this notification, the host processor 106 changes from the low power consumption mode to the normal power mode (step S23), and receives EMM information from the stream depacket processor 105 (step S2).
4), write the EMM information into the DRAM 118 (step S25). Thereafter, the process returns to the low power consumption mode (step S26), and the process ends.

As a countermeasure 2, stream depacket processor 105 and host processor 106
May be operated as follows. First, when the receiving apparatus itself is in the standby state, the host processor 106 permits the stream depacket processor 105 to become a bus master and enters the low power consumption mode. When the stream depacket processor 105 receives the EMM information in the standby state, the processor 105 directly transmits the EMM information to the DRAM 118.
Write to. At this time, the host processor 106 maintains the low power consumption mode.

(3) The mail (mail) information transmitted from the stream depacket processor 105 is converted into a DR.
When the data is stored in the AM 118, as a countermeasure 1, the host processor 106 operates as follows.

First, upon receiving a notification that the mail information has been sent from the stream depacket processor 105, the mode is changed from the low power consumption mode to the normal power mode. Then, the stream depacket processor 105
Is written to the DRAM 118, and thereafter returns to the low power consumption mode.

As a countermeasure 2, the stream depacket processor 105 and the host processor 106
May be operated as follows. That is, when the receiving device itself is in a standby state, the host processor 106
The stream depacket processor 105 is permitted to become a bus master, and the low power consumption mode is set. In the standby state, the host processor 106 maintains the low power consumption mode, and the stream depacket processor 105 writes the sent mail information directly to the DRAM 118.

(4) When updating the version of section data specified in ISO-13818-1 and ETSI,
As a coping method 1, the host processor 106 operates as follows.

First, upon receiving a notification from the stream depacket processor 105 that a new version of section data has been received, the mode is immediately changed from the low power consumption mode to the normal power mode. Then, the new version of section data transferred from the stream depacket processor 105 is written to the DRAM 118,
The stream depacket processor 105 is set to depacketize and capture a new version of section data. Thereafter, the mode returns to the low power consumption mode.

As a measure 2, the stream depacket processor 105 and the host processor 106
May be operated as shown in the flowchart of FIG.

First, when the receiving apparatus itself is in the standby state, the host processor 106 permits the stream depacket processor 105 to become a bus master and enters the low power consumption mode (step S27). In the standby state, the stream depacket processor 105
Receives a new version of section data that meets the preset filter conditions (step S
28), the data is written to the DRAM 118, and setting for depacketizing and capturing a new version of section data is performed (step S29). At this time, the host processor 106 maintains the low power consumption mode.

(5) As a special case of the above (4), when updating the version of the event information table (EIT) data specified by the ETSI, the stream depacket processor 105 The host processor 106 operates as shown in the flowchart of FIG.

First, the stream depacket processor 105 updates the SI (System Integr.
ation) information (step S30), and notifies the host processor 106 that the SI information has been received (step S31). Upon receiving this notification, the host processor 106 changes from the low power consumption mode to the normal power mode (step S32).

Then, the stream depacket processor 105 transfers the new version of the SI information to the host processor 106 (step S33). The host processor 106 receives the SI information and
118 and the stream depacket processor 1
After performing setting for depacketizing and capturing a new version of section data for the data 05 (step S34), the process returns to the low power consumption mode (step S3).
5).

As a second measure, the stream depacket processor 105 and the host processor 106
May be operated as shown in the flowchart of FIG.

First, when the receiving apparatus itself is in the standby state, the host processor 106 permits the stream depacket processor 105 to become a bus master, and changes the normal power mode to the low power consumption mode (step). S36). In the standby state, the stream depacket processor 105 outputs a new version of the S matching the preset filter condition every three hours.
The process starts upon receiving the I information (step S37).
Then, the received new version of the SI information is
The data is written into M118 (step S38), and the setting for depacketizing and capturing the new version of section data is performed (step S39). At this time, the host processor 106 maintains the low power consumption mode.

As a third solution, the stream depacket processor 105 and the host processor 106
May be operated as shown in the flowchart of FIG.

First, the host processor 106 shifts from the low power consumption mode to the normal power mode every three hours, and sends a new filter to the stream depacket processor 105 so that the stream depacket processor 105 can acquire ETI information. Set conditions (Step S
40). Receiving the resulting ETI information and DRA
The ETI information held in M118 is updated, and the process returns to the low power consumption mode again (step S41). Thereafter, the stream depacket processor 105 acquires the ETI information based on the set filter conditions, and directly
Writing is performed on 118 (step S42).

As described above, according to the above-described embodiment, in the standby state, the stream depacket processor 105 outputs EMM information or mail for program viewing from a digital broadcast signal including a video signal and an audio signal.
When the information is extracted, the host processor 106 is notified that the EMM information or mail information has been extracted.
Then, the host processor 106 changes from the low power consumption mode to the normal power mode, and transmits the EMM information or the mail information to the stream depacket processor 10.
5 and transferred to the smart card 117 or the DRAM 118 for storage. After the completion of the storage, the mode returns to the low power consumption mode again.

For this reason, in the standby state, the power consumption can be minimized, and the EM required for viewing
Since the M information or the mail information is collected in the smart card 117 or the DRAM 118 during the standby state, the viewing can be promptly started when the user enters the viewing state from the standby state.

In the standby state, the host processor 10
6 is permitted to become the bus master for the stream depacket processor 105 to maintain the low power consumption mode.
By writing the M information or the mail information directly to the DRAM 118, the power consumption of each circuit can be further reduced in the standby state. Further, the same can be applied to updating the version of section data.

When transmitting the viewing recording data stored in the smart card 117 to the center in the standby state, the host processor 106 is changed from the low power consumption mode to the normal power mode, and the modem 116 and the smart card 117 are switched. Set each power supply to ON state,
The viewing record data is read from the smart card 117 and transmitted to the center via the modem 116, and thereafter,
By turning off the power of each of the modem 116 and the smart card 117 and returning to the low power consumption mode, it is possible to transmit the viewing recording data to the center while suppressing the power consumption in the standby state, The center can collectively manage viewing records for programs. Further, the host processor 106 includes a DRAM 118
When viewing record data is stored in the
The viewing record data may be read from 18 and transmitted to the center via the modem 116.

In the above embodiment, EMM information or mail information is described as being stored in the DRAM 118. However, the EMM information or mail information may be stored in the smart card 117. In this case, when the host processor 106 is notified that the EMM information or the mail information has been received from the stream depacket processor 105 during the standby state, the host processor 106 is changed from the low power consumption mode to the normal power mode, and Set the power to ON. Then, the EMM information or the mail information is transferred from the stream depacket processor 105 to the smart card 117 and stored therein. After the storage is completed, the power of the smart card 117 is set to the off state, and then the low power consumption mode is resumed. Return to

By the way, in the configuration of the above embodiment, when the user is not watching the program and the power is off (the AC power input is kept on), the MPEG audio decoder 107 and the MPEG video decoder 10
The signal processing systems before and after the stream depacket processor 105 are operating at full capacity just by turning off the signal processing systems 9 and thereafter, and wastefully consumes electricity. The following embodiment is to solve this problem.

Here, in the following embodiment, in a case where the user is not watching a program and the power is off, the transmitting side transmits the information including the information indicating the transmission cycle of the EMM in the SI information. To On the receiving side, when the user stops watching the program and performs a power-off operation, the host computer 106 receives the next transmitted EMM and updates the information, and then, based on the EMM transmission cycle information described above. Then, a built-in timer is set in accordance with the next EMM acquisition timing, and the power supply of the signal processing system is turned off together with the power supply of the signal processing system to enter a standby state. Then, when an ON command is issued at the timing set by the timer, the power of the signal processing system is turned on together with its own power to start receiving (wake up) and check the EMM version. EMM if the version is updated here
And reset the timer if the version has not changed. Thereafter, power saving is realized by repeating the same operation.

When the sending side does not include the EMM sending cycle information in the SI information, the receiving side obtains the EMM sending cycle while the receiving apparatus is operating, and sets the timer when the standby state is set. If a time shorter than the EMM transmission cycle is set, the efficiency is somewhat reduced, but the EMM can be acquired reliably.

First, in the configuration shown in FIG. 1, when the viewer is watching, all the circuits are turned on, but the viewer stops the viewing and the receiving apparatus enters a standby state. In this case, as shown in FIG.
06 sets the built-in timer immediately before the next EMM acquisition time based on the individual EMM acquisition cycle established when the power is turned on, turns off all the circuits, and enters the standby mode. Then, it wakes up at the set time of the timer, turns on the power from the antenna to the depacket processor 105, obtains the EMM, performs an update process if necessary, sets the built-in timer again, and turns on the power of all circuits. Turn off. Thereafter, this process is repeated until the present receiver is operated.

When the host processor 106 enters the standby mode, the bus for the host processor 106 is open to external circuits. In other words, individual EMM
When the power is temporarily turned on to acquire the data, only the power from the antenna to the depacket processor 105 and the DRAM 118 need to be turned on. When the EMM is received, the depacket processor 105 restarts the host processor 1.
06 interrupts to change from the standby state to the power-on state, checks the acquired EMM version,
If the version has changed, the EMM is updated. If the version has not changed, the newly obtained EMM is discarded, and the host processor 106 returns to the standby state again. After the occurrence of the interrupt, the power of the depacket processor 105 is turned off from the antenna.

As shown in FIG. 8, in order to correct an error in the transmission cycle according to the accuracy of the transmission cycle of the EMM, a time shorter than the detected transmission cycle is set in the timer, and the timer is set. After a lapse of time, the power of the depacket processor 105 is controlled to be turned on from the antenna. If the viewer has turned off the power of the receiving device at the time when the EMM is received, the above process is repeated so that the EMM can always obtain the latest one.
In order to acquire the individual EMM, when the power from the antenna input to the depacket processor 105 and the DRAM 118 is turned on, other various table data is acquired until the acquisition update of the EMM is completed. DR
It may be stored in the AM 118.

FIG. 9 shows an operation in the case where a log viewed during a time other than the time when the timer is set is transmitted to the broadcast station. When sending the watched log, the power of the host processor 106, the modem and the like is also turned on.
M is received. Alternatively, when the receiving apparatus is turned on in a different state from the timer, the same effect can be obtained by setting the remaining time at the time when the receiving apparatus is turned off next in the timer.

The specific processing flow will be described below.

FIG. 10 shows an overall processing flow on the premise that the broadcast station broadcasts the EMM information together with the EMM transmission cycle information. When the service reception is started, the EMM and the EMM transmission cycle information are received (step S51), and after the EMM reception is stopped (step S5).
2) The next EMM acquisition timing (EMM transmission cycle-specified time) is calculated from the EMM transmission cycle and the timing at which the EMM was acquired, and set in the timer (step S5).
3). After the elapse of the time set in the timer, the mobile phone wakes up to start acquiring the EMM (step S54), and returns to the process of step S51.

In the above processing, the EMM reception timing is determined from the EMM reception timing and the EMM transmission cycle information, and the EMM is received from a specified time before the EMM transmission time. It is characterized by the following.

FIG. 11 shows the flow of processing including power control when the receiving apparatus enters a standby state. First, when the receiving apparatus (IRD) is turned on and in a receiving state, it is determined whether or not the viewer has requested a state change to a standby state (step S61). If there is a request, the EMM and the EMM transmission cycle information are received (step S62), and after the EMM reception is stopped (step S6).
3) The next EMM acquisition timing (EMM transmission cycle-specified time) is calculated from the EMM transmission cycle and the timing at which the EMM was acquired, and is set in the timer (step S6).
4). The time set in the timer, the sub CPU 114
Is to operate only the remote control reception function, and the main CPU
(Host processor 106) sets the power saving mode,
The other circuits are turned off except for the memory (DRAM 118) (step S65).

In this state, it is determined whether or not the viewer has changed the IRD to the ON state (step S66). If the IRD has been changed to the ON state, the process returns to step S61. If not, the timer is set. After a lapse of time, the main CPU (host processor 106) turns on the power from the antenna to the depacket processor 105 to acquire the EMM (step S67), and returns to step S62.

The above processing is performed only when the EMM is received while the viewer is in the IRD standby state.
The circuit is characterized in that the entire circuit is energized and the other circuits are not energized except for the circuit that manages the time. In particular, when the IRD is supplying power to the antenna, the antenna should not supply power to the antenna while the viewer is in the standby state, and supply power to the antenna only during reception of the EMM. Features.

FIG. 12 shows a flow of processing in a case where other SI information is acquired at the time of acquiring the EMM in the standby state and the information is retained in addition to the functions shown in FIG. First, when the receiving apparatus (IRD) is turned on and in the receiving state, it is determined whether or not the viewer has requested a state change to the standby state (step S71). When there is a request, acquisition and updating of SI information other than the EMM are performed (step S72), and it is determined whether the reception of the EMM and the EMM transmission cycle information is completed (step S73).

If the reception has not been completed, the process returns to step S72. If the reception has been completed, after the EMM reception has been stopped (step S74), the EMM transmission cycle and the next EMM acquisition timing (E
MM transmission cycle-specified time) is calculated and set in the timer (step S75). During the time set in the timer, the sub CPU 114 operates only the remote control reception function, the main CPU (host processor 106) sets the power saving mode, and the other circuits use the memory (DRAM 11).
The power is turned off except for step 8) (step S76).

In this state, it is determined whether or not the viewer has changed the IRD to the ON state (step S77). If the IRD has been changed to the ON state, the process returns to step S71. If not, the timer is set. After the elapse of the time, the main CPU (host processor 106) turns on the power from the antenna to the depacket processor 105 to acquire the EMM (step S78), and returns to step S72.

The above processing is performed only when the EMM is received when the viewer is in the IRD standby state.
It is characterized in that the entire circuit is energized, and other SI information is also acquired and stored in a memory holding the information until the EMM is acquired.

FIG. 13 shows another processing example.
When RD is turned on and in the receiving state, EMM and EMM
After receiving the transmission cycle information (step S81) and stopping the EMM reception (step S82), the EMM transmission cycle and the next EMM acquisition timing (E
(MM transmission cycle-specified time) is calculated and set in the timer (step S83).

Here, it is determined whether or not the viewer has changed the IRD to the standby state (step S84). If there is no change, the process returns to step S81.
After the timer time set at the time of the power-on state elapses, the main CPU (host processor 106) turns on the power from the antenna to the depacket processor to acquire the EMM (step S85). In this state, the EMM and the EMM transmission cycle information are received (step S86), and E
After the MM reception is stopped (step S87), the next EMM acquisition timing (EMM transmission cycle-specified time) is calculated from the EMM transmission cycle and the timing at which the EMM was acquired, and set to the timer (step S88). During the time set in the timer, the sub CPU 114 operates only the remote control reception function and the main CPU (host processor 10).
6) is set to the power saving mode, and the other circuits are stored in the memory (DR)
Power is turned off except for AM118) (step S8)
9).

In this state, it is determined whether or not the viewer has changed the IRD to the on state (step S90). If the viewer has changed the IRD to the on state, the process returns to step S81; otherwise, the timer is set. After the elapse of the time, the main CPU (host processor 106) turns on the power from the antenna to the depacket processor 105 to acquire the EMM (step S91), and returns to step S86.

The above processing is performed even when the viewer is viewing using the IRD.
In the case where the IRD is turned off after turning on the power of the IRD once, for example, by downloading the viewing record from the broadcasting station side, the EMM is repeated during the M transmission cycle. Is obtained.

FIG. 14 shows still another processing example. First, when the IRD is turned on and in the receiving state, the EMM
And EMM transmission cycle information (step S10).
1) After stopping the EMM reception (step S102), the EMM
From the transmission cycle and the timing at which the EMM was acquired, the next EMM
The acquisition timing (EMM transmission cycle-specified time) is calculated and set in a timer (step S103).

Here, it is determined whether or not the viewer has changed the IRD to the standby state (step S104). If there is no change, the process returns to step S101. Calculate the remaining time of the timer time set at the time when you set it, reset the timer again,
After the timer time elapses, the main CPU
(Host processor 106) turns on the power from the antenna to the depacket processor (step S105).

In this state, the EMM and the EMM transmission cycle information are received (step S106), and after the EMM reception is stopped (step S107), the next EMM acquisition timing (EMM transmission cycle-designation) is determined based on the EMM transmission cycle and the timing at which the EMM was acquired. Time) is calculated and set in a timer (step S108). During the time set in the timer, the sub CPU 114 operates only the remote control reception function,
The main CPU (host processor 106) sets the power saving mode, and the other circuits turn off the power except for the memory (DRAM 118) (step S109).

In this state, it is determined whether or not the viewer has changed the IRD to the ON state (step S110). If the IRD has been changed to the ON state, the process returns to step S101. If not, the timer is set. EMM
Main CPU (host processor 106) for acquisition
Turns on the power from the antenna to the depacket processor 105 (step S111), and returns to step S106.

The above processing can be performed even when the viewer is viewing using the IRD.
In the case where the viewer changes the IRD to the standby state, or in response to the change, when the broadcaster side turns on the IRD once, for example, by downloading the viewing record, and then turns the IRD off again, The EMM is acquired by appropriately changing the time for setting the timer from the timing of turning off the IRD and the cycle of receiving the EMM. At this time, the IRD is turned on, and thereafter, a timer time is set based on the reception timing of the EMM and the transmission cycle information of the EMM, and after the set time has elapsed, the EMM is received. Do not energize circuits other than the ones under management.

The present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the scope of the present invention.

[0086]

As described in detail above, according to the present invention,
When receiving a digital broadcast in which the additional information is updated periodically, the additional information can be updated while minimizing power consumption in a standby state. A digital broadcast receiving device that can be started can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital broadcast receiving apparatus according to the present invention.

FIG. 2 is an exemplary flowchart illustrating an example of the operation of the host processor when the viewing record information stored in the smart card is transmitted to the center in the embodiment.

FIG. 3 is an exemplary flowchart showing an example of the operation of the host processor when the EMM information sent from the stream depacket processor in the embodiment is held in a DRAM.

FIG. 4 is an exemplary flowchart showing an example of the operation of the stream depacket processor when updating the version of section data in the embodiment;

FIG. 5 is an exemplary flowchart showing an example of the operation of the host processor when updating the version of the event information table data in the embodiment.

FIG. 6 is an exemplary flowchart illustrating an example of the operation of the stream depacket processor when updating the version of event information table data in the embodiment.

FIG. 7 is an exemplary flowchart illustrating an operation example of the stream depacket processor and the host processor when updating the version of the event information table data in the embodiment.

FIG. 8 is a timing chart showing a flow of processing of a receiving apparatus for a bit stream as another embodiment that further saves power.

FIG. 9 is a timing chart showing a flow of processing of a receiving apparatus when a log is transmitted in a standby state in the other embodiment.

FIG. 10 is a flowchart showing an overall processing flow in the other embodiment.

FIG. 11 is a flowchart showing a specific processing flow in the other embodiment.

FIG. 12 is a flowchart showing the flow of another specific process in the other embodiment.

FIG. 13 is a flowchart showing the flow of another specific process in the other embodiment.

FIG. 14 is a flowchart showing the flow of another specific process in the other embodiment.

FIG. 15 is a diagram showing a packet configuration of a system layer of ISO / IEC13818-1.

FIG. 16 is a block circuit diagram showing a configuration of a system layer of ISO / IEC13818-1.

[Explanation of symbols]

105 ... stream depacket processor, 106 ...
Host processor, 106a application software, 113 ROM, 114 Sub-MPU, 1
16: Modem, 117: Smart card, 118: DR
AM.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Natsuki Koshiro 8th, Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Multimedia Technology Research Laboratories (72) Eiichiro Asanaga, Shin-Sugita-cho, Isogo-ku, Yokohama-shi, Kanagawa No. 8 Inside Toshiba Multimedia Technology Research Laboratories (72) Inventor Tsukasa Kudo No. 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Pref.

Claims (12)

[Claims] A first processor for extracting, from a digital broadcast signal, additional information including at least information for viewing a program or mail information multiplexed on the signal or update information for selecting a program; A first storage unit for collecting information or the update information, a low power consumption mode and a normal power mode, and a circuit control for viewing according to a predetermined program and the additional information or the update information; A second processor, wherein the first processor extracts the additional information or the update information that meets a preset filter condition from the digital broadcast signal, and extracts the second information. Notifying means for notifying the processor that the additional information or the update information has been extracted, the second processor Becomes a low power consumption mode in the standby state of the apparatus, the first
When the processor has been notified that the additional information or the update information has been extracted, the low power consumption mode is changed to the normal power mode, and after the change to the normal power mode, the information is extracted by the first processor. The apparatus further comprises a standby control unit for transferring the additional information or the update information to the first storage unit and writing the same, and returning to the low power consumption mode after the completion of the writing of the additional information or the update information. A digital broadcast receiving apparatus characterized by the above-mentioned. 2. The first storage means is a memory used for watching a program, and when the second processor is set to a normal power mode, power is supplied by the second processor. 2. The digital broadcast receiving apparatus according to claim 1, wherein on / off control is selectively performed, and the additional information or the update information can be written in an on state. 3. The apparatus further comprises: a second storage unit for holding the viewing record information; and a transmitting unit for transmitting the viewing record information to a center, wherein the standby control unit of the second processor comprises: In the standby state of the apparatus, when transmitting the viewing record information to the center, the mode is changed from the low power consumption mode to the normal power mode, the power of the transmission unit is set to the ON state, and The power supply of the transmission means is set to an off state after reading the viewing record information and transmitting the information to the center via the transmission means, and thereafter returning to the low power consumption mode again. 2. The digital broadcast receiving device according to 1. 4. The second storage means is a memory card holding the viewing record information, and the second storage means stores the viewing record information in a state where the second processor is set to a normal power mode.
When the power is selectively turned on / off by the processor and the viewing record information is transmitted to the center, the viewing record information is set to the ON state, the viewing record information is read out, and transmitted to the center. The digital broadcast receiving apparatus according to claim 1, wherein the digital broadcast receiving apparatus is set to: 5. A first processor for extracting, from a digital broadcast signal, additional information including at least information for viewing a program or mail information multiplexed on the signal or update information for selecting a program, A first storage unit for collecting additional information or the update information; a low power consumption mode and a normal power mode; and a predetermined program and a circuit control for viewing according to the additional information or the update information. A second processor that performs writing of the additional information or the update information to the first processor when the device itself is in a standby state, thereby reducing power consumption. A standby mode processing unit to be in a power mode, wherein the first processor is provided with the second processor provided by the second processor. Accessing the first storage means by permitting writing to the storage means, and transferring and writing the additional information or the update information extracted from the digital broadcast signal to the first storage means. A digital broadcast receiving apparatus characterized by the above-mentioned. 6. The digital broadcast receiving apparatus according to claim 5, wherein said first storage means is a semiconductor memory capable of writing said additional information or said update information. 7. Additional information including at least program viewing information or mail information periodically multiplexed from a digital broadcast signal to the signal, or update information for selecting a program, and such information are transmitted. A first processor for extracting the received timing information, a first storage unit for collecting the additional information or the update information, a low power consumption mode and a normal power mode, and a predetermined program; A second processor that performs circuit control for viewing according to the additional information or the update information, wherein the first processor meets a preset filter condition from the digital broadcast signal. The additional information or the update information and the timing information are extracted, and the additional information is sent to the second processor. Notifies the second processor that the update information has been extracted, and sends the timing information to the second processor. The second processor includes a timer that notifies that a set time has elapsed since the second processor was turned off. Calculate the time when the next additional information or update information is sent from the timing information obtained in the operation state of the own device, set the time to the timer, and receive the notification of the elapse of the set time by the timer, Digital broadcast reception characterized by repeatedly executing a process of calculating the time at which the next additional information or update information is sent after obtaining the additional information or update information, and setting the time in the timer. apparatus. 8. When the own device is in a standby state, the second device
The processor, in a period during which the additional information or the update information is received, a circuit that performs the reception is turned on,
8. The digital broadcast receiving apparatus according to claim 7, wherein in a period other than the period, parts other than a part for managing time are set to a non-energized state. 9. When the apparatus is in a standby state, the second
8. The processor according to claim 7, wherein the processor supplies power to an antenna for receiving the additional information or the update information during a period during which the additional information or the update information is received, and sets the antenna to a non-power-supplying state during other periods. Digital broadcast receiver. 10. When the own device is in a standby state, the second processor acquires other service information within a period for receiving the additional information or the update information, and obtains the first storage means. 8. The information is recorded in
The digital broadcast receiving device according to the above. 11. A second apparatus for holding viewing record information.
Storage means, and transmission means for transmitting the viewing record information to a center, wherein the second processor, when extracting a viewing record information request signal included in the additional information, performs the second recording 8. The digital broadcast receiving apparatus according to claim 7, wherein a time set in said timer is calculated in consideration of a period in which the viewing record information is read from the means and transmitted to the center through the transmitting means. 12. When the own device is in a standby state, the second processor sets the second recording unit and the transmission unit to an energized state only during a transmission period of the viewing record information, and sets the other unit to a non-energized state otherwise. The digital broadcast receiving apparatus according to claim 11, wherein: