KR19990014052A - Digital broadcasting receiver - Google Patents

Abstract

The present invention makes it possible to update the supplementary information while receiving a digital broadcast in which the supplementary information is regularly updated, while minimizing power consumption in the standby state.

The present invention has a first processor 105 for extracting additional information, a storage means 118 for collecting additional information, a low power consumption mode and a normal power mode, and a circuit for viewing in accordance with a predetermined program and additional information. A second processor 106 that performs control is provided. The first processor 105 notifies the second processor 106 that the additional information has been extracted, and the second processor 106 notifies that the additional information has been extracted from the first processor 105 in the low power consumption mode in the standby state. If so, the mode is changed to the normal power mode, the additional information extracted by the first processor 105 is recorded in the storage means 118, and after the end of recording, the mode is changed to the low power consumption mode. This makes it possible to update the additional information while suppressing low power consumption in the standby state.

Description

Digital broadcasting receiver

The present invention relates to an improvement of a digital broadcast receiving apparatus used in a digital broadcast system.

In recent years, the digital signal processing technology of video and audio has made remarkable progress, and along with it, the system has been actively developed in various countries for the realization of the convergence of digital broadcasting, broadcasting and communication.

Among these, one of the most important technologies is video and audio compression technology. As this compression technique, MPEG, JPEG, and H.261 were typical. In particular, the compression method proposed by the Moving Picture Coding Experts Group (ISO / IEC JTC1 / SC29 / WG11) is being examined for global standardization of broadcasting, communication, and storage media.

In the ISO / IEC13818-1, not only the video compression but also the control part for multiplexing and broadcasting a compressed bit stream for each video, audio, and data of a program, and the receiver side, the contents are firmly established.

Multiple control of the bit stream for broadcasting and communication of ISO / IEC13818-1 will be briefly described with reference to FIGS. 15 and 16.

Fig. 15 shows a model of a video system and an audio system for a packet forming method. First, both video and audio are divided into units for each frame, and headers are formed to construct PES (Packetized Elementary Stream). do. This PES is of variable length. Furthermore, in order to time-multiplex video and audio, each PES is basically divided into packets every 184 bytes, and 4 bytes of headers are attached to each other to form 188 bytes of TP (Transport Packet). Although FIG. 15 shows a case where multiplexing of video and audio is considered, in practice, data such as additional data of a program or program information is also TPized and time-multiplexed.

Next, a method of configuring a bit stream as a broadcast will be described with reference to FIG.

In Fig. 16, programs A and B represent one program, and both of two video systems, two audio systems, one ECM (Entitlement Control Messages) system transmitted by each of the multiple devices 1 and 2, and the program · One system of map table (PMT: Program Map Table) is multiplexed and output as TS (A) and TS (B). Here, the video, audio, and ECM represent video data, audio data, and additional information data, respectively, whereas the PMT includes a packet ID or a packet ID for identifying each piece of information of the video data, audio data, and additional information data. Technology is included. The TS (A) and TS (B) of these programs A and B include a program association table (PAT: Program Association Table), a network information table (NIT), and a conditioner in multiple devices (3). Null access table (CAT) and individual user key information (EMM (Entitlement Management Messages) information) transmitted to individual receivers required to watch the program are multiplexed. It is output as TS corresponding to.

By the way, in the digital broadcasting system, the individual user key information is periodically updated by the transmitting side in order to facilitate the viewing management of subscribers. For this reason, it is necessary for the receiving side to monitor the update of the individual user key information so that the viewing can be started quickly when entering the viewing state from the standby state. In this case, it is possible to cope by keeping the sub power supply of a necessary circuit such as a processor managing individual user key information always on, but this consumes power unnecessarily.

As described above, when additional information such as individual user key information is regularly updated in the digital broadcasting system, a method of keeping the sub-power of a circuit necessary for monitoring the updating of the additional information on the receiving side is always on. Doing so consumes power.

SUMMARY OF THE INVENTION An object of the present invention is to update additional information while minimizing power consumption in the standby state when receiving digital broadcasts in which the additional information is regularly updated, whereby the viewing information can be quickly viewed upon transition from the standby state to the viewing state. The present invention provides a digital broadcast receiving apparatus capable of initiating a broadcast.

1 is a block diagram showing an embodiment of a digital broadcast receiving apparatus according to the present invention.

Fig. 2 is a flowchart showing an example of the operation of the host processor in the case of transmitting the viewing record information stored in the smart card to the center in the embodiment;

Fig. 3 is a flowchart showing an example of the operation of the host processor in the case of holding in the DRAM the EMM information transmitted from the stream depacket processor in the embodiment;

Fig. 4 is a flowchart showing an example of the operation of the processor for stream depacketing when updating the version of the section data in the embodiment.

Fig. 5 is a flowchart showing an example of the operation of the host processor in the case of updating the version of the event information table data in the embodiment.

Fig. 6 is a flowchart showing an example of the operation of the stream depacketization processor in the case of updating the version of the event information table data in the embodiment.

Fig. 7 is a flowchart showing an example of operations of a stream depacket processor and a host processor in the case of updating a version of event information table data in the embodiment.

8 is a timing diagram showing a flow of processing of a receiving apparatus for a bit stream as another embodiment for further power saving.

Fig. 9 is a timing diagram showing the flow of processing by a receiving device in the case of performing log sending in the standby state according to the other embodiment.

Fig. 10 is a flowchart showing an overall process flow in the other embodiment.

Fig. 11 is a flowchart showing the flow of specific processing in the other embodiment.

Fig. 12 is a flowchart showing another specific processing flow in the other embodiment.

Fig. 13 is a flowchart showing another specific processing flow in the other embodiment.

Fig. 14 is a flowchart showing another specific processing flow in the other embodiment.

Fig. 15 shows the packet structure of the system layer of ISO / IEC13818-1.

Fig. 16 is a block circuit diagram showing the configuration of the system layer of ISO / IEC13818-1.

<Explanation of symbols for main parts of drawing>

105: processor for stream depacket

106: host processor

106a: Application Software

113: ROM

114: sub-MPU

116: modem

117: smart card

118: DRAM

In order to achieve the above object, a digital broadcast receiving apparatus according to the present invention includes a first processor for extracting additional information including at least information for viewing a program or mail information multiplexed with a corresponding signal from a digital broadcast signal, and additional information. An apparatus comprising a storage means for collecting and a second processor having a low power consumption mode and a normal power mode, and for performing circuit control for viewing in accordance with a predetermined program and additional information, wherein the first processor is configured in advance from a digital broadcast signal. Notify that the second processor extracts the additional information that meets the set filter condition and extracts the additional information, and the second processor enters a low power consumption mode in a standby state of its own device, and notifies that the additional information is extracted by the first processor. Change from low power consumption mode to normal power mode And further characterized in that after switching to the normal power mode returning to a low power consumption mode again after the end of recording of the additional information transmitted by the record in the storage means, and the additional information extracted by the first processor.

According to this configuration, in the standby state, when the first processor extracts additional information for viewing a program from the digital broadcast signal, it notifies the second processor that the additional information is extracted. Then, the second processor is converted from the low power consumption mode to the normal power mode, and transfers and accumulates the additional information from the first processor to the storage means, and after completion of the accumulation, the second processor returns to the low power consumption mode again.

As a result, in the standby state, the second processor detects the additional information and operates in the normal power mode only when it accumulates in the storage means, and stores the additional information in the storage means, thereby updating the additional information while minimizing power consumption. In this way, it is possible to quickly start viewing upon the transition from the standby state to the viewing state.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail with reference to drawings.

1 shows a configuration of a digital broadcast receiving apparatus according to an embodiment of the present invention. 1, the terminal 100 is supplied with a digitally modulated broadcast signal such as a broadcasting satellite (BS), a communication satellite (CS), a cable television (CATV), and a terrestrial wave. The broadcast signal supplied to the terminal 100 is digitally signaled in the A / D converter 101, demodulated by the demodulation circuit 102, and decoded by the FEC in the FEC decoder 103, It is supplied to the descramble circuit 104. This descramble circuit 104 descrambles the output of the FEC decoder 103, and the output signal is supplied to the processor 105 for stream depacketing.

The stream depacket processor 105 performs depacket processing of the transport packets specified in ISO-13818-1 and ETSI to the output of the descramble circuit 104, and the audio PES signal in the depacketized signal. Is transmitted to the MPEG audio decoder 107 in accordance with the PID specified by the host processor 106. The MPEG audio decoder 107 decodes the transmitted audio PES signal and converts it into an audio signal. The audio signal is output to a sound reproduction apparatus (not shown) via the terminal 108.

The video PES signal is transmitted to the MPEG video decoder 109 among the signals depacketized by the stream depacketization processor 105. The video PES signal is decoded in the same way as audio in the MPEG video decoder 109, and is encoded in the NTSC encoder 110, and output as a video signal to a monitor (not shown) via the terminal 111. At this time, the SDRAM 112 is used as a buffer of data of the MPEG audio decoder 107 and the MPEG video decoder 109.

In the stream depacket processor 105, the depacketed additional information and the like are transmitted to the host processor 106. The host processor 106 downloads a program from the ROM 113 at power-on, activates various application software 106a, and inputs a viewer input from the Sub-MPU (Micro Processing Unit) 114. The control shown below is performed based on the information and the additional information transmitted from the stream depacket processor 105.

(1) The input / output of the data of the high speed interface 115 is controlled.

(2) The audience record data is created, and the audience record data is sent to the center of the provider using the modem 116.

(3) When receiving an interactive broadcast such as a questionnaire, the modem 116 is used to transmit data such as an answer.

(4) When the viewer uses the paper view PPV, the viewing record data is created and held in the smart card 117.

(5) When receiving a scrambled program, key information of the program is extracted from the smart card 117 so that the program can be viewed.

(6) The additional information transmitted from the stream depacket processor 105 is held in a DRAM (Dy namic random access memory) 118.

(7) The stream depacket processor 105 is configured to execute a depacket process.

(8) Decode processing control of the MPEG audio decoder 107 and the MPEG video decoder 109 is performed.

(9) When the stream depacketization processor 105 acquires the EMM and the ECM, the version is managed, and when the version is up, the personal information is replaced by the EMM and the program information is replaced by the ECM. Is extracted and stored in the smart card 117 as key information.

(10) The period for acquiring the individual EMM is determined based on the delivery period information of the individual EMM and the timing received by the individual EMM.

The digital broadcast receiving apparatus has a viewing state that the viewer is watching and a standby state where the viewing is stopped. In the viewing state, all the circuits are turned on to perform viewing operation (normal operation). In the waiting state, the A / D converter 101 to the stream depacket processor 105 and the DRAM 118 are connected to the viewing state. Similarly, the power is turned on to maintain the normal operating state. At this time, the host processor 106 is in a low power consumption mode and the other parts are in a power off state, and may be in an on state as necessary.

The smart card 117 means a card defined in ISO7816 or a card equivalent thereto. In the smart card 117, key information for viewing a particular program is stored in advance. When viewing the particular program using this key information, the viewing record data of the particular program is recorded.

In addition, the low power consumption mode of the host processor 106 refers to a mode in which the operation of the host processor is partially stopped to reduce power consumption, but a mode in which a request for bus release from the outside is received or comparable thereto. In addition, the host processor 106 has a built-in timer for executing periodic processing.

Hereinafter, operations of the stream depacket processor 105 and the host processor 106 in the standby state will be described in each case.

(1) When notifying the provider's center of the viewing record data by using the modem 116, the host processor 106 operates as shown in the flowchart of FIG.

First, when a predetermined time is reached by the timer, the data sending operation is started (step S11) and the mode is changed from the low power consumption mode to the normal power mode (step S12). Then, the smart card 117 and the modem 116 are turned on to be driven (steps S13 and S14), and the viewing record data is extracted from the smart card 117 (step S15).

Subsequently, a call is made to the modem 116, a communication line is connected to the center described above (step S16), and the viewing record data extracted from the smart card 117 is transmitted to the center side via the modem 116 (step S17). Thereafter, the power supply of the modem 116 and the smart card 117 is turned off (step S18) to move to the low power consumption mode again (step S19).

(2) In the case where the EMM information transmitted from the stream depacket processor 105 is retained in the DRAM 118, as a countermeasure 1, the stream depacket processor 105 and the host processor 106 are described in the flowchart of FIG. It works as shown.

First, when the stream depacket processor 105 receives the EMM information meeting the preset filter condition (step S21), it notifies the host processor 106 that the EMM information has been received (step S22). The host processor 106 receives this notification, changes from the low power consumption mode to the normal power mode (step S23), receives the EMM information from the stream depacket processor 105 (step S24), and stores the EMM information in the DRAM ( 118) (step S25). After that, the processing returns to the low power consumption mode (step S26).

As a coping method 2, the stream depacket processor 105 and the host processor 106 may be operated as follows. First, when the receiving device itself is in the standby state, the host processor 106 permits the stream depacket processor 105 to be the bus master, thereby entering the low power consumption mode. When the stream depacket processor 105 receives the EMM information in the standby state, the stream depacket processor 105 writes the EMM information directly to the DRAM 118. At this time, the host processor 106 maintains a low power consumption mode.

(3) In the case where the mail information transmitted from the stream depacket processor 105 is retained in the DRAM 118, the host processor 106 operates as follows.

First, upon receiving a notification that the mail information has been transmitted from the stream depacket processor 105, the mode changes from the low power consumption mode to the normal power mode. Then, the mail information transmitted from the stream depacket processor 105 is recorded in the DRAM 118 and then returned to the low power consumption mode.

As a coping method 2, the stream depacket processor 105 and the host processor 106 may be operated as follows. In other words, when the receiving device itself is in the standby state, the host processor 106 permits the stream depacket processor 105 to be the bus master, thereby entering the low power consumption mode. In the standby state, the host processor 106 maintains the low power consumption mode and the stream depacket processor 105 writes the transmitted mail information directly to the DRAM 118.

(4) In case of updating the version of the section data defined in ISO-13818-1 and ETSI As a countermeasure 1, the host processor 106 operates as follows.

First, upon receipt of a notification that a new version of section data has been received from the stream depacket processor 105, it immediately changes from the low power consumption mode to the normal power mode. Then, the new version of the section data transmitted from the stream depacket processor 105 is written to the DRAM 118, and the setting for depacking and importing the new version section data to the stream depacket processor 105 is made. Do it. Thereafter, the flow returns to the low power consumption mode.

As the coping method 2, the stream depacket processor 105 and the host processor 106 may operate as shown in the flowchart of FIG.

First, when the receiving device itself is in the standby state, the host processor 106 permits the stream depacket processor 105 to be the bus master to enter the low power consumption mode (step S27). In the standby state, the stream depacket processor 105 receives the new version of the section data meeting the preset filter condition (step S28) and writes the data to the DRAM 118 and furthermore, the new version of the section data. Setting to depacket and accept the section data is made (step S29). At this time, the host processor 106 maintains a low power consumption mode.

(5) As a special example in the case of (4) above, when updating the version of the event information table (EIT) data defined in the ETSI, as a countermeasure 1, the processor 105 for stream depacketing and the host processor ( 106 operates as shown in the flowchart of FIG.

First, the stream depacket processor 105 receives a new version of SI (System Integration) information that meets a preset filter condition, for example, every three hours (step S30), and the SI for the host processor 106 is received. Notify that the information has been received (step S31). The host processor 106 receives this notification and changes from the low power consumption mode to the normal power mode (step S32).

Then, the stream depacket processor 105 transmits a new version of SI information to the host processor 106 (step S33). The host processor 106 receives this SI information, stores it in the DRAM 118, and sets a setting for depacking and importing a new version of section data to the processor 105 for stream depacketing (step S34). Return to the low power consumption mode (step S35).

In addition, as a coping method 2, the stream depacket processor 105 and the host processor 106 may operate as shown in the flowchart of FIG.

First, when the receiving device itself is in the standby state, the host processor 106 permits the stream depacket processor 105 to be the bus master and changes from the normal power mode to the low power consumption mode (step S36). In the standby state, the stream depacket processor 105 receives a new version of SI information that satisfies a preset filter condition every three hours and starts processing (step S37). Then, the received new version SI information is recorded in the DRAM 118 (step S38), and a setting for depacking and importing the new version section data is made (step S39). At this time, the host processor 106 maintains a low power consumption mode.

In addition, as a coping method 3, the stream depacket processor 105 and the host processor 106 may operate as shown in the flowchart of FIG.

First, the host processor 106 transitions from the low power consumption mode to the normal power mode every three hours, and adds a new filter to the stream depacket processor 105 so as to obtain ETI information from the stream depacket processor 105. The condition is set (step S40). The resulting ETI information is received to update the ETI information held in the DRAM 118, and the process returns to the low power consumption mode again (step S41). Thereafter, the stream depacket processor 105 acquires the ETI information based on the set filter condition and writes directly to the DRAM 118 (step S42).

As described above, according to the above embodiment, in the standby state, the stream depacket processor 105 extracts EMM information or mail information for program viewing from a digital broadcast signal including a video signal, an audio signal, and the like. The host processor 106 is notified that the EMM information or the mail information has been extracted. The host processor 106 then changes from the low power consumption mode to the normal power mode and transfers the corresponding EMM information or mail information from the stream depacket processor 105 to the smart card 117 or DRAM 118 to accumulate and accumulate. After the end, it returns to the low power consumption mode again.

For this reason, in the standby state, power consumption can be extremely suppressed, and the viewing state in the standby state is collected by collecting the EMM information or mail information necessary for viewing in the smart card 117 or the DRAM 118 in the standby state. When we entered, we can start seeing immediately.

Also, in the standby state, the host processor 106 is allowed to be the bus master for the processor 105 for stream depacking to maintain a low power consumption mode, and the processor for stream depacket 105 directly sends EMM information or mail information. By writing to the DRAM 118, it is possible to further reduce power consumption of each circuit in the standby state. Furthermore, the same can be done when updating the version of the section data.

In the standby state, when transmitting the viewing record data accumulated in the smart card 117 to the center, the host processor 106 is changed from the low power consumption mode to the normal power mode, and the modem 116 and the smart card 117 are used. Set the power of each of the &lt; RTI ID = 0.0 &gt;), read the viewing and recording data from the smart card 117, transmit it to the center via the modem 116, and then power each of the modem 116 and the smart card 117. Is set to the off state to return to the low power consumption mode, so that the viewing record data can be transmitted to the center while the power consumption is suppressed in the standby state, and the viewing record for the program can be collectively managed in the center. The host processor 106 may read out the viewing record data from the DRAM 118 and transmit it to the center via the modem 116 when the viewing record data is accumulated in the DRAM 118.

In the above embodiment, the EMM information or the mail information is stored in the DRAM 118. However, the smart card 117 may be stored. In this case, when the host processor 106 is notified that the EMM information or the mail information is received from the stream depacket processor 105 in the standby state, the host processor 106 changes from the low power consumption mode to the normal power mode, and the smart card 117 Set the power to ON. Then, the EMM information or the mail information is transferred from the stream depacket processor 105 to the smart card 117 and accumulated. After the accumulation ends, the power of the smart card 117 is set to the off state, and then again in the low power consumption mode. Return to

By the way, in the structure of the above embodiment, in the state where the user is not watching a program and the power is off (AC power input is supplied as it is), the signal processing after the MPEG audio decoder 107 and after the MPEG video decoder 109 is performed. Just by turning off the system, the signal processing system before the stream depacket processor 105 is fully operational and consumes electricity unnecessarily. The following embodiment is for solving this problem.

In the following embodiment, the transmission side includes information indicating the EMM transmission cycle in the SI information for transmission when the user is in a power-off state in which the user is not watching a program. In addition, on the receiving side, when the user stops watching a program and performs a power-off operation, the host computer 106 receives the next transmitted EMM and updates the information, and then, based on the above-described EMM delivery cycle information, the internal timer Is set in accordance with the next EMM acquisition timing, and its power is turned off together with the power of the signal processing system to be in a standby state. When the on command is issued from the timer at the set timing, the power of the signal processing system is turned on together with its own power supply, wakes up, and checks the version of the EMM. If the version is updated, update the EMM. If the version does not change, set the timer again. Thereafter, power savings are realized by repeating the same operation.

When the transmitting side does not include the EMM sending cycle information in the SI information, the receiving side obtains an EMM sending cycle while the receiving apparatus is operating and sets a timer shorter than the EMM sending cycle when the receiver is set to the standby state. If set, the efficiency will be somewhat deteriorated, but the acquisition of the EMM can be ensured.

First, in the configuration shown in FIG. 1, when all the circuits are turned on when the viewer is watching, but the viewer stops watching and the receiver enters the standby state, as shown in FIG. 8, the host On the basis of the individual EMM acquisition period established when the processor 106 is powered on, the built-in timer is set just before the next EMM acquisition time to turn off all the circuits to enter standby mode. Then, the controller wakes up at the set time of the timer, turns on the power from the antenna to the depacketization processor 105, acquires the EMM, updates it as necessary, and sets the built-in timer again to turn off all the circuits. Subsequently, this process is repeated until the present receiving device is operated.

When the host processor 106 enters the standby mode, the bus in charge of the host processor 106 is open to external circuits. In other words, when power is temporarily turned on for acquiring an individual EMM, only the depacket processor 105 and the DRAM 118 need to be powered on. When the EMM is received, the depacket processor 105 rehosts the host. The processor 106 checks the version of the acquired EMM by interrupting the power-on state from the standby state, updates the EMM if the version is changed, and discards the newly acquired EMM if it is not changed, and the host processor 106 Returns to the standby state again. After the interrupt is generated, the depacket processor 105 is powered off from the antenna.

In addition, as shown in FIG. 8, in order to correct an error in the transmission cycle according to the accuracy of the transmission cycle of the EMM, a timer is set to have a time shorter than the detected transmission cycle. Control the power of 105). When the viewer turns off the power of the receiver when the EMM is received, the EMM can always obtain the latest one by repeating the above process. In order to acquire the individual EMM, when the depacket processor 105 and the power supply of the DRAM 118 are in the ON state, various other table data are also acquired between the acquisition of the EMM until the acquisition update of the EMM is completed. 118) may be stored.

Fig. 9 shows an operation in the case where a watched log is transmitted to the broadcasting station side other than the time when the timer is set. When sending the viewed log, the power of the host processor 106 and the modem is also turned on. At this time, the timer is not reset and the cycle is kept to receive the next EMM. Alternatively, when the present receiver is turned on under a different situation from the timer, the same effect can be obtained by setting the remaining time at the time when the next main receiver is turned off in the timer.

The flow of a specific process is demonstrated below.

Fig. 10 shows the overall processing flow on the premise that the broadcasting station broadcasts the EMM information together with the EMM information of the transmission period. When service reception is started, EMM and EMM transmission cycle information are received (step S51), and after the EMM reception stops (step S52), the next EMM acquisition timing (EMM transmission cycle-designated time) is calculated from the EMM transmission cycle and the timing at which the EMM is acquired. To set the timer (step S53). After the elapse of the time set in the timer, the device wakes up to start acquisition of the EMM (step S54), and the process returns to step S51.

The subsequent processing is characterized in that the reception timing of the EMM is determined from the timing at which the EMM is received and the transmission period information of the EMM, so that the EMM is received from a specified time before the time when the EMM is transmitted.

Fig. 11 shows the flow of the process including control of the power supply when the present receiving apparatus is in the standby state. First, it is determined whether or not the viewer is requesting a state change to the standby state when the present reception device IRD is on and in the reception state (step S61). If there is a request, the EMM and the EMM transmission cycle information are received (step S62) and after the EMM reception stops (step S63), the next EMM acquisition timing (EMM transmission cycle-designated time) is calculated from the EMM transmission cycle and the timing at which the EMM is acquired. To set the timer (step S64). At the time set in the timer, the sub CPU 114 activates only the remote control receiving function, sets the main CPU (host processor 106) to the power saving mode, and other circuits except memory (DRAM 118). Then, the power is turned off (step S65).

In this state, it is determined whether or not the viewer has changed the IRD to the on state (step S66). If the viewer changes to the on state, the process returns to step S61. The main CPU (host processor 106) turns on the power from the antenna to the depacket processor 105 (step S67), and returns to step S62.

In the above process, when the viewer puts the IRD in a standby state, the entire circuit of the IRD is in the power supply state only during the period in which the EMM is received, and no power is supplied other than the circuits that manage time. It features. In particular, when the IRD is supplying power to the antenna, the period during which the viewer puts the IRD in the standby state is characterized by supplying power to the antenna only during the period in which the EMM is received without supplying power to the antenna.

In addition to the function shown in FIG. 11, FIG. 12 shows the flow of processing in the case of acquiring other SI information at the time of EMM acquisition in a standby state, and holding that information. First, when the present reception device IRD is on and in the reception state, it is judged whether or not the viewer is requesting a state change to the standby state (step S71). If there is a request, acquisition and change of SI information other than the EMM are performed (step S72), and it is judged whether or not reception of the EMM and EMM transmission cycle information is completed (step S73).

Here, if the reception is not completed, the process returns to step S72. If the reception is completed, after the EMM reception stops (step S74), the next EMM acquisition timing (EMM transmission cycle-specified time) at the EMM transmission cycle and the timing at which the EMM is acquired. Is calculated and set in the timer (step S75). The time set in the timer, the sub CPU 114 activates only the remote control reception function, sets the main CPU (host processor 106) to the power saving mode, and other circuits except memory (DRAM 118). The power is turned off (step S76).

In this state, it is determined whether or not the viewer has changed the IRD to the on state (step S77). If the viewer changes to the on state, the process returns to step S71. If there is no change, the viewer obtains the EMM after the time set in the timer. The main CPU (host processor 106) turns on the power from the antenna to the depacket processor 105 (step S78), and returns to step S72.

In the above process, when the viewer is in the standby state of the IRD, only the period during which the EMM is received, the entire circuit of the IRD is in the power supply state, and the time until the acquisition of the EMM is also acquired and other information is retained. It is characterized by storing in the memory.

Fig. 13 shows another example of processing, in which, when the IRD is on and in the receiving state, EMM and EMM transmission cycle information is received (step S81), and after EMM reception stops (step S82), the EMM transmission cycle and EMM The next EMM acquisition timing (EMM sending cycle-specified time) is calculated from the timing at which the signal is obtained and set in the timer (step S83).

Here, it is determined whether or not the viewer has changed the IRD to the standby state (step S84), and if there is no change, the process returns to step S81, and if there is a change, after the timer time set at the time of power-on state, In order to acquire the EMM, the main CPU (host processor 106) turns on the power from the antenna to the processor for depacketing (step S85). In this state, the EMM and the EMM transmission cycle information are received (step S86), and after the EMM reception stops (step S87), the next EMM acquisition timing (EMM transmission cycle-designated time) is calculated from the EMM transmission cycle and the timing at which the EMM is acquired. The timer is set (step S88). The time set in the timer, the sub CPU 114 activates only the remote control reception function, sets the main CPU (host processor 106) to the power saving mode, and other circuits except memory (DRAM 118). The power is turned off (step S89).

In this state, it is determined whether or not the viewer has changed the IRD to the ON state (step S90). If the viewer changes to the ON state, the process returns to step S81. If there is no change, the viewer returns to the main unit for acquiring the EMM after the time set in the timer. The CPU (host processor 106) turns on the power from the antenna to the depacket processor 105 (step S91), and returns to step S86.

The above processing is performed repeatedly in the EMM transmission cycle in which the EMM reception is extracted even when the viewer is watching using the IRD, and the viewer puts the IRD in a standby state, and reflects the viewing record from the broadcasting station. In the case where the power supply of the IRD is turned on once and then turned off again, the EMM is acquired in the on cycle.

FIG. 14 shows another embodiment, first receiving EMM and EMM transmission cycle information when the IRD is on and in the receiving state (step S101), and after stopping EMM reception (step S102), the EMM transmission cycle and the EMM are received; From the acquired timing, the next EMM acquisition timing (EMM sending cycle-specified time) is calculated and set in a timer (step S103).

Here, it is determined whether or not the viewer has changed the IRD to the standby state (step S104). If there is no change, the process returns to step S101. After calculating and resetting the timer again, after the timer time has elapsed, the main CPU (host processor 106) turns on the power from the antenna to the processor for depacketing to acquire the EMM (step S105).

In this state, the EMM and the EMM transmission cycle information are received (step S106) and after the EMM reception stops (step S107), the next EMM acquisition timing (EMM transmission cycle-specified time) is calculated from the EMM transmission cycle and the timing at which the EMM is acquired, and the timer (Step S108). The time set in the timer, the sub CPU 114 activates only the remote control reception function, sets the main CPU (host processor 106) to the power saving mode, and other circuits except memory (DRAM 118). The power is turned off (step S109).

In this state, it is determined whether or not the viewer has changed the IRD to the on state (step S110). If the viewer changes to the on state, the process returns to step S101. The CPU (host processor 106) turns on the power from the antenna to the depacket processor 105 (step S111), and returns to step S106.

The above processing is performed repeatedly in the EMM transmission cycle in which the EMM reception is extracted even when the viewer is watching by using the IRD, and when the viewer changes the IRD to the standby state or accompanies the change, the broadcasting station watches. In the case where the power supply of the IRD is turned off after turning on the IRD once due to reflection of recording, the EMM is obtained by appropriately changing the timer time from the timing of turning off the IRD and the period of receiving the EMM. At this time, the IRD is set to the power supply state, and after that, a timer time is set based on the reception timing of the EMM and the transmission cycle information of the EMM, and after the set time has elapsed, the EMM is received. Do not supply power except the circuit under control.

In addition, this invention is not limited to the said embodiment, Of course, other deformation | transformation can be implemented in the range which does not deviate from the summary of this invention.

As described in detail above, according to the present invention, when receiving a digital broadcast in which the additional information is regularly updated, the additional information can be updated while minimizing power consumption in the standby state, and thereby the viewing state in the standby state. It is possible to provide a digital broadcast receiving apparatus capable of promptly starting viewing at the time of transition to a network.

Claims (12)

A first processor for extracting, from the digital broadcast signal, additional information including at least information for viewing a program or mail information multiplexed with the corresponding signal, or update information for selecting a program; First storage means for collecting said additional information or update information; A second processor having a low power consumption mode and a normal power mode, and performing circuit control for viewing in accordance with a predetermined program and the additional information or update information; The first processor includes notification means for notifying the second processor that the additional information or the update information has been extracted by extracting the additional information or update information that meets a predetermined filter condition from the digital broadcast signal, The second processor enters a low power consumption mode in the standby state of its own device, and changes from the low power consumption mode to the normal power mode when notified of extraction of the additional information or update information by the first processor, and the normal power mode. After the change to the control, the standby control to transfer the additional information or update information extracted by the first processor to the first storage means for recording, and to return to the low power consumption mode again after the recording of the additional information or update information is finished. And a means for digital broadcast reception. 2. The power supply of claim 1, wherein the first storage means is a memory used for viewing a program, and power is selectively turned on and off by the second processor while the second processor is set to a normal power mode. And the recording of the additional information or the update information in the controlled state. 2. The apparatus according to claim 1, further comprising second storage means for holding viewing record information, and transmitting means for transmitting the viewing record information to a center; The standby control means of the second processor changes from the low power consumption mode to the normal power mode and sets the power of the transmission means to the on state when transmitting the viewing record information to the center in the standby state of the own device, Digital broadcasting, characterized in that the viewing record information is read out from the second storage means and transmitted to the center via the transmitting means, the power of the transmitting means is turned off, and then returned to the low power consumption mode again. Receiving device. 4. The power supply of claim 1 or 3, wherein the second storage means is a memory card holding the viewing record information, and power is selectively selected by the second processor while the second processor is set to a normal power mode. And on / off control, and set to the on state when the viewing record information is transmitted to the center, and set to the off state after the viewing record information is read and transmitted to the center. A first processor for extracting, from the digital broadcast signal, additional information including at least information for viewing a program or mail information multiplexed with the corresponding signal, or update information for selecting a program; First storage means for collecting said additional information or update information; A second processor having a low power consumption mode and a normal power mode, and performing circuit control for viewing in accordance with a predetermined program and the additional information or update information; The second processor includes standby processing means for granting a recording permission of the additional information or update information to the first processor when the device is in the standby state, and entering a low power consumption mode; The first processor accesses the first storage means by permission to write to the first storage means provided by the second processor, and extracts the additional information or update information extracted from the digital broadcast signal. A digital broadcast receiving device characterized by being transmitted to a storage means for recording. 6. The digital broadcast receiver as claimed in claim 5, wherein the first storage means is a semiconductor memory capable of recording the additional information or update information. A first processor for extracting from the digital broadcast signal additional information including program information or mail information, which is periodically multiplexed with the corresponding signal, update information for selecting a program, and timing information from which the information is transmitted; Wow, First storage means for collecting said additional information or update information; A second processor having a low power consumption mode and a normal power mode, and performing circuit control for viewing in accordance with a predetermined program and the additional information or update information; The first processor extracts the additional information or update information and timing information corresponding to a preset filter condition from the digital broadcast signal, notifying the second processor of the extraction of the additional information or update information, and at the same time, the timing. Send information to the second processor, The second processor includes a timer for notifying that the set time has elapsed since being turned off, and calculating a time for which the next additional information or update information is transmitted from the timing information obtained in the operating state of the own device, and calculating the time. Set to the timer, receive notification of the elapsed setting time by the timer, acquire the additional information or update information, calculate a time for which the next additional information or update information is transmitted, and set the time to the timer; A digital broadcast receiver, characterized in that the process is repeatedly executed. 8. The circuit according to claim 7, wherein, when the own device is in the standby state, the second processor sets the circuit which performs the reception in the period of receiving the additional information or the update information to the power supply state, and the time in other periods. A digital broadcast receiving device, characterized in that the power supply other than the portion that manages the state. 8. The method according to claim 7, wherein when the device itself is in a standby state, the second processor supplies power to the antenna for performing the reception in the period of receiving the additional information or the update information, and in other periods of time. A digital broadcast receiving device, characterized in that the power is not supplied. 8. The second processor according to claim 7, wherein, when the own device is in the standby state, the second processor acquires other service information and records it in the first storage means within a period of receiving the additional information or the update information. Digital broadcast receiving device. 8. The apparatus according to claim 7, further comprising: second storage means for holding viewing record information, and transmitting means for transmitting the viewing record information to a center; When the second processor extracts the viewing record information request signal included in the additional information, the second processor sets the timer in consideration of a period of reading the viewing record information from the second recording means and transmitting the viewing record information to the center through the transmitting means. Digital broadcast receiving device, characterized in that to calculate the time. 12. The apparatus according to claim 11, wherein, when the own device is in the standby state, the second processor makes the second recording means and the transmission means in the power supply state for the transmission period of the viewing record information, and otherwise in the non-power supply state. Digital broadcast receiving device, characterized in that.