JPH1198208A - Demodulator for digital radio communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain miniaturization and low power consumption by converting a frequency-modulated or phase-modulated signal into an intermediate frequency signal, detecting the phase, sampling the phase information and detecting the intermediate frequency signal from an over-sampled signal so as to operate a counter and to reduce the intermediate frequency, without accompanying deterioration in the reception characteristic. SOLUTION: A sampling means 5 consists of an amplitude-limiting means 12 that limits the amplitude of an intermediate frequency reception signal outputted from a frequency conversion means 3 and consists of a latch means 13. The latch means 21 is realized by, e.g. a D-type flip-flop, its D input terminal is connected to an output terminal of a counter means 11, and its CLK input terminal is connected to the output terminal of the amplitude limit means 12. The output of the sampling means 5 is fed to an oversampling means 6. One or more samples are generated from a phase component adjacent timewise among discrete phase components and the discrete phase component is given to a detection means 7 to be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device used in a base station or a terminal station of a radio communication system for performing communication using a signal that has been frequency-modulated or phase-modulated by a digital signal.

[0002]

2. Description of the Related Art In recent years, expectations for digital car / mobile phone systems for multimedia applications such as effective use of frequency resources and speeding up of data transmission have been further increasing. This is because the digital transmission system uses error detection and error correction technology to achieve high transmission quality, high reliability,
It is easy to realize high confidentiality, and because it does not need to reproduce faithful transmission waveforms and spectra like analog transmission, it is suitable for narrowing and multiplexing.In addition, it integrates voice, image, data, etc. It can be handled seamlessly. In addition, the rapid spread of information access services using personal computers and the decrease in communication fees, such as those seen on the Internet and the Internet over the past few years, have further accelerated the spread of digital car / mobile phone systems. Users are expected to continue to increase in the future.

[0003] By the way, at present, among mobile telephone terminals represented by PHS and PDC, quite small ones having a size of 100 cc or less and a weight of 100 g or less have appeared. Such miniaturization of terminals is approaching the limit in existing digital transmission systems.

[0004] In general, a quadrature demodulation method as shown in FIG. 13 is employed in a demodulator of a base station and a terminal station of a radio communication system that performs communication using a signal that has been frequency-modulated or phase-modulated by a digital signal. In the quadrature demodulation type demodulator, a signal received by an antenna 81 is orthogonally converted to a baseband signal (in-phase component) by a frequency conversion unit 82, a mixer 83, a π / 2 phase shifter 90, and a local oscillator 89. And quadrature phase components), and for each phase (channel), a low-frequency leak detector (LP
F) 84, an AD converter (ADC) 85, a root roll-off filter (RROF) 86, a delay detector 87, and a decision / demodulation processing unit 88 for AD conversion, band limitation, and detection demodulation. The scale becomes large.

[0005] In particular, in the case of the differential modulation method (π / 4 shift differential QPSK) employed in PHS and PDC, a complex multiplication process for differentially detecting a quadrature baseband signal is performed. As shown in FIG. 14, usually, it is necessary to prepare four multipliers 92 and two adders 93 in the delay detector 87, and the overall circuit size and power consumption also increase. Under such circumstances, adoption of the quadrature demodulation method in mobile phones is being shunned. Also, a software receiver using a DSP, which has recently attracted attention, consumes a lot of instructions in the delay detection processing, which results in pressure on other functions that should be accommodated in the DSP.

[0006] In view of the above, an IF demodulation system for directly extracting a phase component from a received signal in an intermediate frequency band (IF band) and performing a detection process instead of the quadrature demodulation system has been actively employed. At present, instead of the most basic quadrature demodulation system as described above, an IF demodulation system (or IF detection system) for directly extracting a phase component from an intermediate frequency band (IF band) and performing detection and demodulation has begun to be adopted. I have. This detection method can also be called a polar coordinate demodulation method as compared to the quadrature demodulation method, and can be employed for detection and demodulation of a modulation signal having no information in the amplitude direction such as frequency modulation or phase modulation. The advantages of this demodulation scheme are as follows.

(1) No need for baseband frequency conversion IF signal distributors, mixers (×
2), functional components such as a π / 2 phase shifter, a local oscillator, and a low-pass filter (× 2) become unnecessary.

(2) No AD converter is required. AD converters for the in-phase channel and the quadrature-phase channel of the baseband signal, which are indispensable for the orthogonal demodulation method, become unnecessary.

(3) No need for digital filter A digital low-pass filter (root roll-off filter) × 2 for the in-phase channel and the quadrature-phase channel of the baseband signal, which is indispensable for the quadrature demodulation method, is not required.
However, although an equivalent filter is required in the IF band, the number of filters may be one, and the size and power consumption can be reduced.

(4) No Complex Delay Detector (Differential Detector) is Necessary In the quadrature demodulation method, a base band signal is equivalently treated as a complex number signal, and therefore, a complex number multiplication is required for the delay detection process. The multiplication of complex numbers includes four multiplications and two additions, and performing this with a digital signal quantized by multiple bits is against the miniaturization and low power consumption of the device. If only the phase difference is extracted from the frequency-modulated or phase-modulated signal, the differential detection processing can be realized by one subtraction processing.

(5) Rough quantization accuracy is sufficient In the orthogonal demodulation method, since the amplitude of the orthogonally decomposed received signal is handled, a wide dynamic range, that is, multi-bit, is required for handling a received signal which has been subjected to distortion such as fading. Requires quantization. On the other hand, in the IF demodulation method, since only the phase component of the polar coordinates is handled, the range (dynamic range) that must be represented falls within a closed interval of 0 to 2π. In order to quantize this closed section, about 5 to 6 bits is sufficient even if the deterioration amount is taken into consideration.

As described above, the IF demodulation system has a great advantage as compared with the conventional quadrature demodulation system, and is becoming a core technology not only for a car / portable telephone terminal but also for a personal communication terminal in the future.

However, the IF demodulation system still has the following problem. In the IF demodulation method, the reception performance is determined by the operation frequency of the counter and the phase component extracted from the IF reception signal depending on the IF frequency. Generally, the operation frequency of the counter is 10 (MHz) or more, and the IF frequency is several. 100 (kHz
z). However, since the counter operates at all times and the current consumption increases in proportion to the operation speed, it is desired to lower the operating frequency of the counter to achieve low power consumption. . Also, I
The reduction of the F frequency realizes the incorporation of an IF filter, which has conventionally been provided in an external connection form, into an LSI, thereby contributing to downsizing.

Further, the application of the conventional IF demodulation system is not suitable for the realization of a software receiver using a DSP or the like which has recently attracted attention. The reason is that the operating fundamental frequency is high as described above. Input / output with DSP (I
If the / O) is reduced as much as possible, the performance (efficiency) of the DSP as a whole is improved. Therefore, it is necessary to operate the counter at a low frequency and a low IF frequency.

[0015]

As described above, in a transceiver of a wireless communication system that performs communication using a signal that has been frequency-modulated or phase-modulated by a digital signal, miniaturization and low power consumption are achieved by applying various new technologies. Is planned,
Demands for extension of call / standby time as well as lower prices are gradually being met. However, these requirements for transceivers are expanding further in order to support multimedia communications in the future, and there is a need for a reduction in the processing amount of a modulation unit and a demodulation unit in the transceiver and further improvement of the processing method. .

At present, the IF demodulation system as described above is employed to meet these demands. In this IF demodulation system, the operation of a counter for extracting a phase component is performed in order to avoid unnecessary deterioration of reception characteristics. The frequency and IF frequency must be set high. Since the power consumption of the counter increases in proportion to the operation speed, this is a major obstacle to reducing the power consumption. Setting a high IF frequency requires an external IF filter, which hinders downsizing. Further, when realizing a software receiver using a DSP or the like, it is increasingly necessary to reduce the operating frequency and the IF frequency of the counter in order to reduce the frequency of input / output (I / O) with the DSP. Become.

However, lowering the frequency of the counter operation directly leads to deterioration of the phase component extraction accuracy (quantization accuracy), and lowering the IF frequency deteriorates the symbol phase synchronization accuracy (time accuracy). Directly leads to deterioration of reception characteristics (bit error rate characteristics and the like). Therefore, these circumstances prevent the operation of the counter and the realization of a lower IF frequency.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem, and a demodulation device of a base station or a terminal station of a radio communication system for performing communication using a signal which is frequency-modulated or phase-modulated by a digital signal, It is an object of the present invention to provide a digital radio communication demodulator capable of realizing a counter operation and a lower IF frequency without deteriorating reception characteristics, thereby realizing miniaturization and low power consumption.

[0019]

In order to achieve the above object, a demodulator for digital radio communication according to the present invention comprises: a receiving means for receiving a signal frequency-modulated or phase-modulated by a digital signal; Frequency converting means for converting the converted intermediate frequency signal, a phase detecting means for detecting the phase of the converted intermediate frequency signal, a sampling means for sampling the detected phase information, a sampled by the sampling means Oversampling means for increasing the number of sampling points of the phase information of the received signal, detecting means for detecting the intermediate frequency signal from the output of the oversampling means, and demodulation for demodulating transmission information from the output of the detecting means. Means.

According to the present invention, the operating frequency and the IF frequency of the phase component extraction counter can be suppressed without deteriorating the reception characteristics, and low power consumption can be reduced. In addition, since a low IF frequency can be used, an externally mounted IF filter can be easily integrated into an IC, and the demodulation device can be downsized.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a demodulation apparatus for digital radio communication according to an embodiment of the present invention, that is, a demodulation apparatus applied to a base station or a terminal station of a radio communication system for performing communication using a signal phase-modulated by a digital signal. FIG. 3 is a diagram illustrating a configuration.

As shown in FIG. 1, the demodulation device 1 comprises a receiving antenna 2, frequency conversion means 3, phase detection means 4, sampling means 5, oversampling means 6, detection means 7, and demodulation means 8. I have. The phase-modulated signal received by the receiving antenna 2 connected to the demodulation device 1 is converted by the frequency conversion means 3 into a signal of a predetermined intermediate frequency. Although omitted in the figure, the frequency conversion means 3 includes, for example, a local, a mixer, a band limiting filter,
It is composed of an amplifier and the like. The intermediate frequency received signal whose frequency has been converted by the frequency conversion means 3 is input to the sampling means 5.

As shown in FIG. 2, the phase detecting means 4 includes a reference clock generator 14 for generating a clock faster than the intermediate frequency, and a counting means operated by the reference clock generated by the reference clock generator 14. 11 is comprised. A predetermined counting cycle is set in the counting means 11, and the counting means 11 counts the reference clock while repeating the reset at the set counting cycle, and outputs the count value to the sampling means 5. The counting means 11 may perform counting in free run.

The sampling means 5 samples the output signal of the phase detection means 4 based on the intermediate frequency reception signal input from the frequency conversion means 3 to obtain phase information of the intermediate frequency reception signal. As shown in FIG. 2, the sampling means 5 includes an amplitude limiting means 12 for limiting the amplitude of the intermediate frequency reception signal output from the frequency converting means 3.
And holding means 13. The holding unit 13 can be realized by, for example, a D-type flip-flop. The D input terminal of this D type flip-flop is connected to the output terminal of the counting means 11 and the CLK input terminal is connected to the output terminal of the amplitude control means 12. That is,
The intermediate frequency reception signal output from the frequency conversion means 3 is shaped like a rectangular wave by being limited to a constant amplitude by the amplitude limiting means 12, and the modulation component of the intermediate frequency reception signal is converted into a PWM signal. . The D-type flip-flop (holding unit 13) holds the phase component of the intermediate frequency reception signal output from the counting unit 11 for each rising edge of the output signal of the amplitude limiting unit 10.

The output of the sampling means 5 is input to an oversampling means 6 for increasing the apparent sampling speed. Oversampling means 6
Generates one or more samples at time points between the temporally adjacent phase components of the discrete phase components sampled by the sampling means 5. The discrete phase components of the received signal whose number of samples has been increased by the oversampling means 6 are input to the detection means 7, where the detection according to the modulation method is performed. The received signal detected by the detection means 7 is input to the demodulation means 8 and is demodulated.
Performs predetermined processing such as demapping processing and parallel-serial conversion on the detected received signal to reconstruct a transmission information sequence.

With such a configuration, the frequency of the phase detecting means 4 (counter) and the sampling means 5 can be reduced, the number of analog parts can be reduced, and the number of analog components can be reduced to one chip (the IF filter is built in the LSI). Therefore, the demodulation device for digital wireless communication can be reduced in size and power consumption can be reduced.

FIG. 3 is a diagram showing a specific configuration example of the oversampling means 6. The oversampling unit 6 performs double oversampling by calculating a sample at an intermediate time between two adjacent times in the time series sample obtained by the sampling unit 5 by a moving average process.

In the figure, the output of the sampling means 5 is input to a delay means 21 and an addition means 22, respectively. The delay unit 21 delays the output of the sampling unit 5 by a half cycle of the intermediate frequency reception signal and inputs the delayed output to the addition unit 22.
The adding means 22 adds the phase component signal directly input from the sampling means 5 and the delayed phase component signal input from the delay means 21 and outputs the result to the correcting means 23.

The oversampling means 6 is connected to the output of the counting means 11 of the phase detecting means 4 and the amplitude limiting means 12.
And a discontinuous phase detecting means 24 for detecting the presence or absence of a discontinuous phase in the output of the phase detecting means 4 from the intermediate frequency reception signal whose amplitude has been limited. Correction means 23
Performs correction on the output of the adding means 22 when the discontinuous phase is detected by the discontinuous phase detecting means 24.

Next, the effect of oversampling and its effect will be described with reference to FIG. The count value of the counting means 11 of the phase detecting means 4 repeats a numerical value within a predetermined range in the free-run state as shown in FIG. The holding unit 13 holds the count value at the rising edge of the output of the amplitude limiting unit 12. In this example, the output of the counting means 11 is repeated every fixed period of the reference intermediate frequency, so that the count value held in the holding means 13 differs for each sample depending on the modulation state. In such a case, a difference appears in the number of discontinuous portions of the count value of the counting means 11 included in two adjacent sample periods, whereby the addition result deviates from the true value by π. This means that the phase component is 0
This is caused by degeneracy between ２2π. For example,
In FIG. 4, the correction processing by the correction unit 23 is unnecessary in state 1 and state 4, but in state 2 and state 4.
In state 3 or the like, appropriate correction processing (rotation processing of the phase π) by the correction means 23 is required.

By performing such a correction processing, discontinuity is eliminated in the detected phase samples at two adjacent times, and oversampling of a true value can be realized.

FIG. 5 is a diagram showing a configuration example of the discontinuous phase detecting means 24 in the oversampling means 6.

As shown in the figure, the discontinuous phase detecting means 24 is a part of the output of the phase detecting means 4 (for example, car
ry signal) is input as a count signal (clock) to perform a counting operation, and a second counter 31 is reset based on the output of the amplitude limiting means 12. The output of the second counter 31 is input to the discontinuity detection flag setting unit 32,
The discontinuity detection flag setting unit 32 determines whether the stat
The state e2 and the state 3 are detected, that is, when the number of discontinuous points is 2 or 0, and the detection result is output to the correction means 23.

The second counter 31 is a general-purpose counter IC
Or a frequency dividing circuit using D-type flip-flops. FIG. 6 shows an implementation example of the second counter 31 using the counter IC 41. This second counter 3
1 is L of the counter IC 41 when the number of discontinuous points is 2 or 0.
The sign of SB becomes L level, and this is output to the correction means 23 as a detection result. FIG. 7 shows an implementation example of the second counter 31 using the D-type flip-flop 42. Also in this case, when the number of discontinuities is 2 or 0, the output of the Q terminal of the D-type flip-flop 42 becomes L level, and the detection result can be similarly given to the correction means 23.

By using such a discontinuous phase detecting means 24, it is possible to reliably detect the discontinuous phase, and to perform appropriate correction processing by the correcting means 23. And oversampling of the true value can be realized.

FIG. 8 is a diagram showing a configuration example of the correction means 23 in the oversampling means 6.

As shown in FIG.
A second adding means 51 that adds either 0 or a predetermined value to the output of the adding means 22 and outputs the result to the detection means 7, and an added value to be given to the second adding means 51 is 0 (53) and a predetermined value ( 5
4) and an AND gate for performing an AND operation on the inverted signal of the detection result from the discontinuous phase detecting means 24 and the output from the amplitude limiting means 12, and controlling the switching means 52 based on the result. 55.

That is, the AND gate 55 detects when the output of the discontinuous phase detecting means 24 is at the L level and the output of the amplitude limiting means 12 is at the H level as a period in which the correction process is to be performed. An H level signal is output. The switch means 52 is connected to the predetermined value (54) while the output of the AND gate 55 is at the H level,
A predetermined value is given to the second adding means 51, and an AND gate 55
0 (53) is added to the adding means 2 during the period when the output of
Give to 2.

FIG. 9 is a timing chart of the oversampling process according to this embodiment. As shown in the figure, the output of the sampling means 5 changes at the rising edge of the amplitude limiting means 12. In addition, the output of the sampling means 5 is delayed by the delay means 21 by substantially half a cycle of the output of the amplitude limiting means 12. As a result, the output of the adding means 22 is “A + A”, “A + B”, “B + B”, “B + C”, “C + C”
... Originally, it is desirable to set the output of the adding means 22 to a value of １ ／, but there is no problem in detection as long as the value is doubled. Also, here "A + B"
Samples such as “B + C” and “C + D” obtained by adding the information of the phase components at two adjacent times from the sampling unit 5 are the samples that can be subjected to the correction processing. Therefore, the H level period of the output of the amplitude limiter 12 is set only when the discontinuous phase is detected by the discontinuous phase detector 24 as described above.
Correction is performed by selecting a predetermined value at 2 and providing it to the second adding means 51. Thereby, it is possible to perform appropriate correction processing.

FIG. 10 shows a specific example of the demodulation device of the present embodiment described above. However, in the figure, the receiving antenna 2, the frequency conversion means 3, and the demodulation means 8 are omitted.

Here, the frequency of the intermediate frequency reception signal is f _IF
And The frequency of the clock counted by the phase detection counter 61 is _IF × 2 ^m, which is higher than f _IF . The count value of the phase detection counter 61 is a D-type flip-flop (DF
F) It is input to the D input terminal 62. The D-type flip-flop (DFF) 62 holds (samples) the count value of the phase detection counter 61 at the rising edge of the intermediate frequency reception signal from the amplitude limiter (limiter) 72 input from the CLK input terminal. The D-type flip-flop (DFF) 62 inputs the sampled data (the phase component of the intermediate frequency reception signal) to the adding means 63 and the D-type flip-flop (DFF) 66 as the delay means.

A D-type flip-flop (DFF) 66, which is a delay means, receives a signal at the rising edge of a signal obtained by inverting the output of an amplitude limiter (limiter) 72 by an inverter 70.
By holding the output of the type flip-flop (DFF) 62, the output of the D-type flip-flop (DFF) 62 is delayed by a half cycle of the intermediate frequency reception signal and input to the adding means 63.

The output of the phase detection counter 61 is given to a frequency divider 73 which is a discontinuous point detecting means having a structure which is reset at the rising edge of the intermediate frequency reception signal whose amplitude is limited by the amplitude limiter 72. The frequency divider 73 counts discontinuous points of the output count value of the phase detection counter 61 during the rising edge period of two adjacent intermediate frequency reception signals. The output of the frequency divider 73 is held by a D-type flip-flop (DFF) 74, and AND
The gate 71 performs an AND operation with the intermediate frequency reception signal. During the period when the output of the AND gate 71 is at the H level, a predetermined value (= 2 ^m ) is selected by the switch 67 and given to the adding means 64, and the output of the preceding adding means 63 is given by the adding means 64. The value (= 2 ^m ) is added, and the addition result is sent to the detection means 65.

FIGS. 11 and 12 show the effects of the present method by computer simulation results of the bit error rate characteristics.

FIG. 11 shows an evaluation of the case where the quantization precision of the counting means 11 of the phase detecting means 4 is set to 5 bits. -(Black square)-in the figure is a bit error rate (BER) characteristic when reception is possible at an optimal sampling phase. For example, in order to apply the IF demodulation method to a wireless communication system having a transmission rate of 25 (ksymbol / sec) and obtain a reception characteristic equivalent to-(solid square)-, a clock generated by the reference clock generator 14 is required. Frequency 1
0 (MHz) or more, the quantization precision of the counting means 11 must be set to about 7 bits, and the intermediate frequency of the received signal obtained by the frequency conversion means 3 must be set to 500 (kHz) or more. The operation speed of the device is conspicuously high, and low power consumption cannot be realized. Also, as the frequency becomes higher, it becomes difficult to realize elemental components on one chip.

Then, for the same system as the above example,
The generated reference clock is about 2 (MHz), the quantization precision is about 6 bits, and the intermediate frequency is 100 (kHz).
Assuming that the reception is synchronized with the worst sampling phase when it is set to about the same level, the reception characteristic is equivalent to-in Fig. 11, and a deterioration of 1 to 2 (dB) is seen in the practical range. Under this assumption, when the oversampling means of the present invention is added, the reception characteristic becomes equivalent to-▲, and a clear improvement effect is seen.

FIG. 12 shows an evaluation of the case where the quantization precision of the counting means 11 included in the phase detecting means 4 is set to 6 bits. -(Black square)-,-▲-,-
●-is the BER characteristic obtained under the same conditions as in FIG. It can be seen that if the quantization precision is about 6 bits, the deterioration of the reception characteristics due to the decrease in the operation continuity of the demodulation unit is improved to such an extent that it can be almost ignored.

The embodiment in which the present invention is applied to a demodulation device applied to a base station or a terminal station of a radio communication system for performing communication using a signal phase-modulated by a digital signal has been described. The present invention can also be applied to a demodulation device applied to a wireless communication system that performs communication using a signal that has been frequency-modulated (for example, an MSK modulation method) by a signal, and similar effects can be obtained.

[0050]

As described above, according to the present invention, the operating frequency and the IF frequency of the phase component extraction counter can be suppressed without deteriorating the reception characteristics, and the power consumption can be reduced. It becomes possible. Also low IF
Since the frequency can be used, the conventional externally mounted IF filter can be easily integrated into an IC, and the demodulator can be downsized. Further, according to the present invention, when a software receiver such as a DSP is realized, the frequency of input / output (I / O) with the DSP can be reduced.
The effect that coating of the SP program becomes easy is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an entire configuration of a demodulator for digital wireless communication according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a phase detection unit 4 and a sampling unit 5 in the embodiment of FIG.

FIG. 3 is a diagram showing a configuration of an oversampling unit 6 in the embodiment of FIG.

FIG. 4 is a diagram showing a time relationship between an output of a phase detection unit 4 and a sampling unit 5 in the embodiment of FIG.

FIG. 5 is a diagram showing a configuration of a discontinuous phase detecting means 24 in the oversampling means 6 of FIG. 3;

6 is a diagram showing a specific example of the implementation of a second counter 31 in the discontinuous phase detection means 24 of FIG.

FIG. 7 is a diagram showing another example of implementation of the second counter 31.

8 is a diagram showing a configuration of a correction unit 23 in the oversampling unit 6 in FIG.

FIG. 9 is a timing chart of an oversampling process in the embodiment of FIG. 1;

FIG. 10 is a diagram showing a specific configuration example of the embodiment of FIG. 1;

11 is a diagram illustrating simulation results of reception characteristics (in the case of a 5-bit quantization accuracy) for explaining the effect of the embodiment in FIG. 1;

12 is a diagram illustrating a simulation result of reception characteristics (in the case of 6-bit quantization accuracy) for explaining the effect of the embodiment in FIG. 1;

FIG. 13 is a diagram showing a configuration of a demodulator for digital wireless communication using a normal quadrature demodulation method.

FIG. 14 is a diagram illustrating a configuration of a differential detection unit in FIG. 13;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Demodulation device 2 ... Receiving antenna 3 ... Frequency conversion means 4 ... Phase detection means 5 ... Sampling means 6 ... Oversampling means 7 ... Detection means 8 ... Demodulation means 11 ... First count Means 12 Amplitude limiting means 13 Holding means 14 Reference clock generation means 21 Delay means 22 Addition means 23 Correction means 24 Discontinuous phase detection means 31 Second counting means 32 discontinuity detection flag setting means 41 counter IC 42 D-type flip-flop IC 51 second adding means 52 switch means 55 AND gate

Claims (5)

[Claims] A receiving means for receiving a signal frequency-modulated or phase-modulated by a digital signal; a frequency converting means for converting the received signal into a signal of an intermediate frequency; Phase detecting means for detecting; sampling means for sampling the detected phase information; oversampling means for increasing the number of sampling points of the phase information of the received signal sampled by the sampling means; and the oversampling means. And a demodulating means for demodulating transmission information from an output of the detecting means, wherein the demodulating means demodulates transmission information from an output of the detecting means. 2. The demodulator for digital wireless communication according to claim 1, wherein said phase detecting means generates a clock having a frequency higher than said intermediate frequency, and counts a clock generated by said clock generating means. The sampling means, wherein the sampling means limits the amplitude of the converted intermediate frequency signal, and samples the output of the counting means with reference to the amplitude-limited intermediate frequency signal. Means for obtaining phase information of the received signal. A demodulator for digital wireless communication. 3. The demodulator for digital wireless communication according to claim 1, wherein said oversampling means delays phase information of said reception signal obtained from said sampling means by a predetermined time within a cycle of said intermediate frequency reception signal. Delaying means, adding means for adding phase information of the received signal directly input from the sampling means and phase information of the delayed received signal, and a discontinuous phase shift from an output of the sampling means. A demodulator for digital wireless communication, comprising: a discontinuous phase detecting means for detecting; and a correcting means for correcting an output of the adding means when a discontinuous phase shift is detected by the discontinuous phase detecting means. apparatus. 4. The demodulator for digital wireless communication according to claim 3, wherein said discontinuous phase detecting means counts the number of discontinuous phase transitions from an output of said phase detecting means,
A demodulation device for digital radio communication, comprising: a correction presence / absence setting means for setting whether or not correction is to be performed by the correction means based on the counting result of the second counting means. 5. The demodulator for digital wireless communication according to claim 3, wherein the correction means is configured to output the intermediate frequency signal whose amplitude is limited by the amplitude limiting means when the correction execution is set by the correction presence / absence setting means. And a means for adding a predetermined value for a predetermined period with reference to the following.