JPH1197668A - Ccd delaying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To markedly reduce power consumption of a transfer gate electrode by setting a coil inductance so that an LC resonance circuit resonates at the frequency of a drive signal of the transfer gate electrode. SOLUTION: A coil 7 having an inductance L is connected between transfer gate electrodes 2, 3. Here, Cl is a total capacitance of electrode 2, C2 is a total capacitance of electrode 3, J1 is a sinusoidal wave current of clock ϕ1 of a drive circuit, J2 is a sinusoidal wave current of clock ϕ2 of the drive circuit. In order to form an LC resonance circuit which resonates at a frequency f of clocks ϕ1 and ϕ2 with the inductance L and capacitance C of the coil, a value of inductance L is set to L=1/(2πf)<2> .C), where C=Cl.C2/(C1+C2). Therefore, it is sufficiency that the supply currents J1, J2 from the drive circuits 4, 5 be set to 1/Q of the current i flowing through the LC resonance circuit. Thereby, the power supplied from the external circuit can be reduced sharply.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD delay device in which power consumed by the capacitance of a transfer gate electrode is reduced.

[0002]

2. Description of the Related Art A CCD delay device has the following advantages as compared with a SAW device or a dielectric resonator currently used for a high-frequency filter. (A) Since the determinant of time and frequency is a clock signal from an external crystal oscillator or the like, it has high accuracy and low temperature dependence. (B) Higher-speed operation can be expected compared to a SAW device in which the limit of speeding up is seen due to the problem of fine processing accuracy. (C) Even when a large delay is applied, the insertion loss is small and the number of external circuits such as a boost amplifier is small. (D) Since it can be manufactured by a process similar to existing semiconductor devices, it is easy to incorporate external circuits, and it is easy to make the system monolithic. Therefore, application to a next-generation transversal filter and a correlator for spread spectrum communication is expected.

As an example, a configuration of a two-phase CCD delay unit is shown in FIG. Reference numeral 1 denotes a charge transfer section, in which comb-shaped transfer gate electrodes 2 and 3 are arranged on a semiconductor substrate so that the comb-shaped comb-shaped portions enter each other in a non-contact manner and are arranged in parallel at a predetermined pitch. . 4 is a driving circuit for generating a clock φ1 for driving one electrode 2 and 5 is a driving circuit for the other electrode 3
Is a driving circuit for generating a clock φ2 for driving the clocks φ1 and φ2, and these clocks φ1 and φ2 have the same frequency and opposite phases. 6 extracts charge from input signal (sampling)
This is the charge extraction unit that performs the operation.

In this CCD delay device, an input signal is sampled by a charge extracting section 6 and sent to the charge transfer section 1 as charges. In the charge transfer section 1, this charge is sequentially transferred to the subsequent stage in synchronization with the clocks φ1 and φ2 by a change in potential by the electrodes 2 and 3 driven by the clocks φ1 and φ2. The charge transfer unit 1 is provided with detection electrodes (not shown) at several stages, and performs filtering, addition, subtraction, and the like on the delayed charge signal extracted by the detection electrodes. And a device such as a correlator.

[0005]

However, focusing on the transfer gate electrodes 2 and 3, each of the electrodes 2 and 3 has an electrostatic capacitance between the transfer gate electrodes 2 and 3 and an internal channel region via a depletion layer in the semiconductor substrate. Forming a capacitance. Therefore, the drive circuits 4 and 5 must charge and discharge this capacity at high speed, and the clock φ
Power is consumed in proportion to the frequency of 1, φ2 and the number of stages (the number of stages) of this capacity. According to the investigation by the inventors, the power consumption of the CCD delay device is dominant.

Considering the application to a transversal filter, a higher center frequency and a wider band require a higher clock frequency and a larger number of stages, so that a large amount of power is consumed. For example, when a filter having a center frequency of 2 GHz and a band of 25 MHz is configured, the inventors have calculated that 500 mW of power is consumed, which is a great hindrance to practical use.

[0007] The present invention has been made in view of the above points, and an object of the present invention is to provide a CCD delay device in which power consumption in a transfer gate electrode is significantly reduced.

[0008]

According to a first aspect of the present invention, a plurality of transfer gate electrodes are arranged in a charge transfer section in parallel at a predetermined pitch, and are arranged in the plurality of transfer gate electrodes. By sequentially applying the drive signals in the order of
In a CCD delay device for transferring an electric charge of an input signal in the direction in which the gate electrodes are arranged, a coil is connected between adjacent transfer gate electrodes, and a capacitance attached to both transfer gate electrodes and an LC resonance circuit including the coil However, the inductance of the coil is set so as to resonate at the frequency of the drive signal of the transfer gate electrode. The second invention is
In the first invention, a detecting means for detecting a voltage of the LC resonance circuit, and a current level of a drive signal for driving the transfer gate electrode is controlled to be a predetermined value according to the voltage level detected by the detecting means. And control means. A third invention is the CCD delay device according to the first or second invention, wherein the plurality of transfer gate electrodes are driven by two-phase drive signals, wherein the number of coils is one, and A common terminal of the plurality of transfer gate electrodes and a second terminal;
A plurality of transfer gate electrodes of the phase were connected to a common terminal. A fourth invention is the CCD delay device according to the first or second invention, wherein the plurality of transfer gate electrodes are driven by three-phase driving signals,
Between the common terminal of the plurality of transfer gate electrodes of the phase and the common terminal of the transfer gate electrodes of the second phase, and between the common terminal of the transfer gate electrodes of the second phase and the third phase. Between the common terminal of the plurality of transfer gate electrodes of the third phase, and between the common terminal of the plurality of transfer gate electrodes of the third phase and the common terminal of the plurality of transfer gate electrodes of the first phase. , Each connected to form a Δ-type connection. A fifth invention is the CCD delay device according to the first or second invention, wherein the plurality of transfer gate electrodes are driven by a three-phase drive signal, wherein the coil is connected to the plurality of transfer gate electrodes of the first phase. Between the common terminal of the gate electrode and the midpoint, between the common terminal of the plurality of transfer gate electrodes of the second phase and the midpoint,
By connecting the common terminal of the plurality of transfer gate electrodes of the phase and the middle point to each other, they are connected in a Y-shape.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a diagram showing an equivalent circuit of a CCD delay unit according to a first embodiment of the present invention. In the present embodiment, a coil 7 having an inductance L is connected between the transfer gate electrodes 2 and 3 shown in FIG. C1 is the total capacitance of the electrode 2, C2 is the total capacitance of the electrode 3, J1 is the sine wave current (current source) of the clock φ1 of the drive circuit 4, J2
Is a sine wave current (current source) of the clock φ2 of the drive circuit 5.

In this embodiment, the coil 7
Of the clock φ by the inductance L and the capacitances C1 and C2.
1. An LC resonance circuit that resonates at a frequency f of φ2 is formed. For this purpose, the value of the inductance L is set to L = 1 / {(2πf) ² · C} (1) where C = C1 · C2 / (C1 + C2).

Since a resistance component is parasitic in the coil 7, this resistance value is set to R, and clocks φ1,
Let φ2 currents J1 and J2 be J1 = J sin (2πft) (2) J2 = J sin (2πft + π) (3), and 2 (L / C) ^1/2 > R Assume that J is the maximum value of the current.

As described above, the steady-state solution of the current i flowing through the coil 7 is as follows: i = J · {1 / (LC)} · {1 / A} · J sin (2πft + θ) (4) A = R ² / L ² · (2πf) ² + ｛1 / (LC)
- (given by ^{2πf 2} 2 θ = tan -1} [{2πfL-1 / (2πfC)} / R].

At this time, from 2πf = 1 / (LC) ^1/2 , i = (2πfL / R) · J sin (2πft) = Q · J sin (2πft) (5) where Q = 2πfL / R.

As described above, the supply currents J1 and J2 from the drive circuits 4 and 5 need only be set to 1 / Q of the current i flowing through the LC resonance circuit, so that the external supply power can be greatly reduced. I understand.

When calculating with the example of a transversal filter having a center frequency of 2 GHz and a band of 25 MHz shown in the description of the prior art, when Q = 10, the power consumed inside the LC resonance circuit, that is, the resistance component R The power consumed is about 15 mW, and if this power is supplemented from the driving circuits 4 and 5, the normal operation of the circuit is maintained, and the power supplied from the driving circuits 4 and 5 can be reduced. This power reduction can be further enhanced by increasing the value of Q.

[Second Embodiment] FIG. 2 is a diagram showing an equivalent circuit of a CCD delay unit according to a second embodiment. Here, AGC (automatic gain control) is performed on the assumption that the current i flowing through the LC resonance circuit deviates from the design value due to variations in the capacitance components C1 and C2, the inductance L of the coil 7, and the resistance R. It is. That is, the voltage obtained between the electrodes 2 and 3 is detected by the differential amplifier 8, and
By taking this into the control circuit 9, if the detected voltage level or polarity deviates from a desired value (design value) at the timing, the amplitude of the clock currents J1 and J2 of the drive circuits 4 and 5 is controlled ( For example, differential control)
Then, the current i flowing through the LC resonance circuit at the timing is
Is set to a desired value. By performing such control, a stable drive amplitude for charge transfer can be obtained even when L, R, and C deviate from the design values. Note that the voltage may be individually detected at each electrode portion, and the clock current of the drive circuit corresponding to the electrode may be controlled.

[Third Embodiment] In the above description, the two-phase C
Although the CD delay unit has been described, 3
The same can be applied to a phase type CCD delay device. FIG. 3 is a diagram showing an equivalent circuit in the case of this three-phase system, in which coils 7u, 7v and 7w are connected in a Δ-type between the transfer gate electrodes U, V and W of each phase. J
u, Jv, and Jw are 1 for driving the electrodes U, V, and W, respectively.
A clock current source of the same frequency having a phase difference of 20;
Cv and Cw are the capacitances of the respective electrodes U, V and W (since a plurality of electrodes of each phase are connected in parallel, these capacitances are respectively the total value).

At this time, the frequency of the clock is f,
Coils 7u, and 7v, and Luvw the same value inductance of 7w, capacitance Cu, Cv, When Cuvw the same value Cw, Luvw = 1 / {( 2πf) 2 · 3Cuvw} ··· (1 ') By setting the inductance of each coil, the LC resonance circuit can resonate at the clock frequency, and the power supplied as the clock can be reduced.

In the case shown in FIG. 3 as well, by detecting the voltages of the transfer gate electrodes U, V and W and applying AGC to the corresponding current sources by feedback as shown in FIG. The current flowing through the circuit can be controlled to a desired value.

[Fourth Embodiment] FIG. 4 shows a three-phase C
It is a figure which shows another example of a CD delay device. This is because the coils 7x, 7x, Y are formed between the transfer gate electrodes X, Y, Z of each phase.
It is a figure showing the example which connected 7y and 7z. 10 is the middle point. Jx, Jy, Jz are clock current sources of the same frequency having a phase difference of 120 for driving the electrodes X, Y, Z, and Cx, Cy, Cz are the capacitances of the electrodes X, Y, Z (electrodes of each phase). Are connected in parallel, and this capacity is the sum of each of them.

At this time, the frequency of the clock is f,
Assuming that the inductances of the coils 7x, 7y, 7z are Lxyz having the same value and the capacitances Cx, Cy, Cz are Cxyz having the same value, Lxyz = 1 / {(2πf) ² · Cxyz} (1 ″) By setting the inductance of the LC resonance circuit to the above, the LC resonance circuit can resonate at the clock frequency, and the power supplied as the clock can be reduced.

Even in the case shown in FIG. 4, by detecting the voltages of the transfer gate electrodes X, Y and Z and applying AGC to the corresponding current sources by feedback as shown in FIG. The flowing current can be controlled to a desired value.

[0023]

As described above, according to the present invention, a coil is connected between electrodes so as to form an LC resonance circuit with the capacitance of the transfer gate electrode, and the LC resonance circuit resonates at the frequency of the drive signal. Since the inductance of the coil is set as described above, there is a great advantage that the supply power of the drive signal can be reduced and a low power consumption CCD delay device can be realized.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a CCD delay device according to a first embodiment.

FIG. 2 is an equivalent circuit diagram of a CCD delay device according to a second embodiment.

FIG. 3 is an equivalent circuit diagram of a CCD delay device according to a third embodiment.

FIG. 4 is an equivalent circuit diagram of a CCD delay device according to a fourth embodiment.

FIG. 5 is a circuit diagram showing a configuration of a conventional CCD delay unit.

[Explanation of symbols]

1: charge transfer unit, 2, 3, U, V, W, X, Y, Z: transfer gate electrode, 4, 5: drive circuit, 6: charge extraction unit,
7, 7u, 7v, 7w, 7x, 7y, 7z: coil,
8: differential amplifier, 9: control circuit, 10: midpoint.

Claims (5)

[Claims] A plurality of transfer gate electrodes arranged in parallel at a predetermined pitch in a charge transfer section, and drive signals are sequentially applied to the plurality of transfer gate electrodes in the order of arrangement, so that the charge of the input signal is reduced. In a CCD delay device for transferring data in the direction in which the gate electrodes are arranged, a coil is connected between adjacent transfer gate electrodes, a capacitor attached to both transfer gate electrodes, and an LC including the coil.
2. The CCD delay device according to claim 1, wherein an inductance of the coil is set so that a resonance circuit resonates at a frequency of the drive signal of the transfer gate electrode. A detecting means for detecting a voltage of the LC resonance circuit; and a control for controlling a current level of a drive signal for driving the transfer gate electrode to a predetermined value in accordance with the voltage level detected by the detecting means. 2. The CCD delay device according to claim 1, further comprising means. 3. A CCD delay device in which said plurality of transfer gate electrodes are driven by two-phase drive signals, wherein said coil is connected to one of said plurality of transfer gate electrodes.
3. The device according to claim 1, wherein the plurality of transfer gate electrodes are connected between a common terminal of the plurality of transfer gate electrodes of the first phase and a common terminal of the plurality of transfer gate electrodes of the second phase. 4. CCD delay device. 4. A CCD delay device in which said plurality of transfer gate electrodes are driven by a three-phase drive signal, wherein said coil comprises:
Between the common terminal of the transfer gate electrodes of the first phase and the common terminal of the transfer gate electrodes of the second phase, and between the common terminal of the transfer gate electrodes of the second phase and the third terminal. Between the common terminal of the plurality of transfer gate electrodes of the phase and the third
The connection between the common terminal of the plurality of transfer gate electrodes of the phase and the common terminal of the plurality of transfer gate electrodes of the first phase is connected to each other to form a Δ-type connection. Item 3. A CCD delay unit according to item 1 or 2. 5. A CCD delay device in which said plurality of transfer gate electrodes are driven by a three-phase drive signal, wherein said coil comprises:
Between the common terminal of the plurality of transfer gate electrodes of the first phase and the midpoint, between the common terminal of the transfer gate electrodes of the second phase and the midpoint, and 3. The CCD delay device according to claim 1, wherein each of the plurality of transfer gate electrodes is connected in a Y-shape by being connected between a common terminal and the middle point.