JPH1197444A - Barrier layer for semiconductor substrate wiring - Google Patents
Barrier layer for semiconductor substrate wiringInfo
- Publication number
- JPH1197444A JPH1197444A JP27049297A JP27049297A JPH1197444A JP H1197444 A JPH1197444 A JP H1197444A JP 27049297 A JP27049297 A JP 27049297A JP 27049297 A JP27049297 A JP 27049297A JP H1197444 A JPH1197444 A JP H1197444A
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- Prior art keywords
- barrier layer
- wiring
- alloy
- semiconductor substrate
- barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体基板に設けた
配線と該配線に隣接する絶縁膜との間に設けられ、該配
線と該絶縁膜の間で生じる相互拡散を防止するバリア層
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a barrier layer provided between a wiring provided on a semiconductor substrate and an insulating film adjacent to the wiring and for preventing mutual diffusion between the wiring and the insulating film. It is.
【０００２】[0002]
【従来の技術】従来、半導体基板の配線材料には、アル
ミニウム又はアルミニウム合金が用いられている。アル
ミニウム又はアルミニウム合金は電気比抵抗（ρ）が約
３μΩｃｍと大きく、ＩＣの集積密度が高くなると、例
えば１Ｇ以上になると、配線、が細く電流容量が不足す
るという問題があり、ストレスマイグレーション、エレ
クトロニクスマイグレーションが発生、極端な場合は配
線が断線するという問題があった。2. Description of the Related Art Conventionally, aluminum or an aluminum alloy has been used as a wiring material for a semiconductor substrate. Aluminum or an aluminum alloy has a large electric resistivity (ρ) of about 3 μΩcm, and when the integration density of the IC becomes high, for example, when it becomes 1 G or more, there is a problem that wiring becomes thin and current capacity is insufficient. In extreme cases, the wiring is broken.
【０００３】近年、アルミニウム又はアルミニウム合金
より、電気比抵抗（ρ）が小さく（約１．７μΩｃ
ｍ）、且つ耐エレクトロニクスマイグレーション、耐ス
トレスマイグレーションの良好なＣｕが配線材料として
使用されるようになってきた。Ｃｕ材を配線材料として
用いた場合、隣接する絶縁膜、例えばＳｉＯ2と相互拡
散し、配線の電気特性を著しく低下させる。そのため従
来は、この相互拡散を防止するため、配線と絶縁膜の間
にＴｉＮ膜をバリア層として設けている。In recent years, electric resistivity (ρ) is smaller than that of aluminum or aluminum alloy (about 1.7 μΩc).
m) and Cu having good resistance to electronics migration and stress migration has been used as a wiring material. When a Cu material is used as a wiring material, the Cu material interdiffuses with an adjacent insulating film, for example, SiO 2, and significantly reduces the electrical characteristics of the wiring. Therefore, conventionally, in order to prevent this interdiffusion, a TiN film is provided as a barrier layer between the wiring and the insulating film.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記の
ようにバリア層にＴｉＮ材を用いた場合、該ＴｉＮ材は
バリア層を形成した後に形成される配線材料との接合が
弱く、且つ比抵抗（ρ）が高いので、本来の配線として
の材料特性が活用できないという問題があった。However, when a TiN material is used for the barrier layer as described above, the TiN material has a weak junction with a wiring material formed after the formation of the barrier layer and has a specific resistance ( ρ) is high, there is a problem that the material characteristics as the original wiring cannot be utilized.
【０００５】本発明は上述の点に鑑みてなされたもの
で、配線材料との接合が強く、且つ比抵抗（ρ）が低い
材料を用い、絶縁膜の間で生じる相互拡散を防止できる
半導体基板配線のバリア層を提供することを目的とす
る。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and uses a material having a strong bonding with a wiring material and a low specific resistance (ρ) to prevent a semiconductor substrate from interdiffusion occurring between insulating films. It is an object of the present invention to provide a wiring barrier layer.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
請求項１に記載の発明は、半導体基板に設けた配線と該
配線に隣接する絶縁膜との間に設けられ、該配線と該絶
縁膜の間で生じる相互拡散を防止するバリア層であっ
て、該バリア層はＢを含有するＮｉ合金材からなること
を特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a wiring provided on a semiconductor substrate and an insulating film adjacent to the wiring; A barrier layer for preventing interdiffusion between films, wherein the barrier layer is made of a B-containing Ni alloy material.
【０００７】また、請求項２に記載の発明は、請求項１
に記載の半導体基板配線のバリア層において、Ｎｉ合金
材がｆｃｃ結晶構造（最密充填結晶構造）を保持してい
ることを特徴とする。[0007] The invention described in claim 2 is the first invention.
Wherein the Ni alloy material has an fcc crystal structure (closest-packed crystal structure) in the barrier layer of the semiconductor substrate wiring described in (1).
【０００８】また、請求項３に記載の発明は、請求項２
に記載の半導体基板配線のバリア層において、Ｎｉ合金
材のＢの含有率が０．０１ａｔ％〜１０ａｔ％であるこ
とを特徴とする。[0008] Further, the invention described in claim 3 is based on claim 2.
Wherein the content of B in the Ni alloy material is 0.01 at% to 10 at%.
【０００９】また、請求項４に記載の発明は、請求項２
又は３に記載の半導体基板配線のバリア層において、該
バリア層の厚さが１００Å以上であることを特徴とす
る。The invention described in claim 4 is the same as the invention described in claim 2.
Alternatively, in the barrier layer of the semiconductor substrate wiring according to 3, the thickness of the barrier layer is 100 ° or more.
【００１０】また、請求項５に記載の発明は、請求項２
又は３又は４に記載の半導体基板配線のバリア層におい
て、該バリア層は無電解メッキで形成されたことを特徴
とする。The invention described in claim 5 is the same as the claim 2.
Alternatively, in the barrier layer of the semiconductor substrate wiring according to 3 or 4, the barrier layer is formed by electroless plating.
【００１１】また、請求項６に記載の発明は、請求項２
又は３又は４に記載の半導体基板配線のバリア層におい
て、該バリア層は電解メッキで形成されたことを特徴と
する。[0011] The invention described in claim 6 is the invention according to claim 2.
Alternatively, in the barrier layer of the semiconductor substrate wiring according to 3 or 4, the barrier layer is formed by electrolytic plating.
【００１２】また、請求項７に記載の発明は、請求項２
又は３又は４に記載の半導体基板配線のバリア層におい
て、該バリア層はスパッタ法で形成されたことを特徴と
する。The invention described in claim 7 is the same as the invention described in claim 2.
Alternatively, in the barrier layer of the semiconductor substrate wiring according to 3 or 4, the barrier layer is formed by a sputtering method.
【００１３】また、請求項８に記載の発明は、請求項２
又は３又は４に記載の半導体基板配線のバリア層におい
て、該バリア層はＣＶＤ法で形成されたことを特徴とす
る。The invention described in claim 8 is the second invention.
Alternatively, in the barrier layer of the semiconductor substrate wiring according to 3 or 4, the barrier layer is formed by a CVD method.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態例を図
面に基づいて説明する。図１は本発明の半導体基板配線
のバリア層の構成例を示す図である。図示するように、
半導体基板の上に形成した絶縁膜であるＳｉＯ2膜１０
に形成された溝の内面にバリア層１１を形成し、該バリ
ア層１１で囲まれた溝にＣｕ又はＣｕ合金の配線層１２
を形成する。バリア層１１はＢを含有するＮｉ合金材
（Ｎｉ−Ｂ合金材）からなる。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a barrier layer of a semiconductor substrate wiring according to the present invention. As shown
SiO 2 film 10 as an insulating film formed on a semiconductor substrate
A barrier layer 11 is formed on the inner surface of the groove formed in the substrate, and a wiring layer 12 of Cu or Cu alloy is formed in the groove surrounded by the barrier layer 11.
To form The barrier layer 11 is made of a Ni alloy material containing B (Ni-B alloy material).
【００１５】ここで上記Ｎｉ−Ｂ合金材のＢの含有率が
１０ａｔ％とする。Ｂの含有率が１０ａｔ％ではアニー
ル前後においてもＮｉ−Ｂ合金材はｆｃｃの結晶構造を
有し、配線層１２の材料であるＣｕのバリアとしての機
能を有する。ここでＢの含有率を１０ａｔ％以上とする
と、バリア層１１の厚さに関係なく、アニール前後でそ
の構造がｆｃｃの結晶構造でなく（アニール前はアモル
ファス（非晶質）、アニール後は金属間化合物）、Ｃｕ
のバリア材としての機能を有しない。Here, it is assumed that the content of B in the Ni-B alloy material is 10 at%. When the B content is 10 at%, the Ni-B alloy material has a crystal structure of fcc before and after annealing, and has a function as a barrier for Cu as a material of the wiring layer 12. If the B content is 10 at% or more, the structure is not a fcc crystal structure before and after annealing regardless of the thickness of the barrier layer 11 (amorphous before annealing, and metal after annealing). Compound), Cu
Does not function as a barrier material.
【００１６】Ｎｉ−Ｂ合金材とＴｉＮ合金材との比抵抗
（ρ）は下記の通りであり、Ｎｉ−Ｂ合金材の方がＴｉ
Ｎ合金材と比較して小さく、バリア層１１の材料として
適している。 ＴｉＮ １００μΩｃｍ〜２００μΩｃｍ Ｎｉ−Ｂ １０μΩｃｍ〜２０μΩｃｍThe specific resistance (ρ) between the Ni—B alloy material and the TiN alloy material is as follows.
It is smaller than the N alloy material and is suitable as a material for the barrier layer 11. TiN 100μΩcm ~ 200μΩcm Ni-B 10μΩcm ~ 20μΩcm
【００１７】また、Ｎｉ−Ｂ合金材はその構造がｆｃｃ
結晶構造であり、構造が金属間化合物であるＴｉＮ合金
材と比較して、配線材であるＣｕとの接合力が強く、バ
リア層１１を構成する材料として好適である。The structure of the Ni—B alloy material is fcc
It has a crystalline structure, and has a stronger bonding force with Cu as a wiring material than a TiN alloy material as an intermetallic compound, and is suitable as a material forming the barrier layer 11.
【００１８】また、上記Ｎｉ−Ｂ合金材のＢの含有率が
０．０１ａｔ％〜１０ａｔ％であれば、ｆｃｃの結晶構
造を維持し、バリア材として使用できることは確認して
いる。また、上記バリア層１１の厚さは１００Å以上と
し、無電解メッキ、電解メッキ、スパッタリング法、Ｃ
ＶＤ法で形成する。無電解メッキの場合は、例えば、Ｎ
ｉＳｏ4・６Ｈ2Ｏ＋ＤＭＡＢ（ジメチルアミンボラン）
のメッキ液を用い温度８０℃で行う。Further, it has been confirmed that when the B content of the above-mentioned Ni—B alloy material is 0.01 at% to 10 at%, the crystal structure of fcc can be maintained and used as a barrier material. The barrier layer 11 has a thickness of 100 mm or more, and is formed by electroless plating, electrolytic plating, sputtering,
It is formed by the VD method. In the case of electroless plating, for example, N
iSo 4 · 6H 2 O + DMAB ( dimethylamine borane)
And at a temperature of 80.degree.
【００１９】配線層１２は無電解メッキ又は電解メッキ
で形成する。そのメッキ液の元素・イオン、化学種、成
分等の例を図２に示す。なお、図２において、電解メッ
キのメッキ液において、添加剤は非イオン系界面活性剤
であり、塩素イオンは添加剤の分解抑制用である。ま
た、ＥＤＴＡ・４Ｎａ（エチレンジアミン四酢酸ナトリ
ウム）はＣｕと安定するキレート化合物（配位子による
錯化合物）を形成し、電解メッキ液で削除可能である。
また、無電解メッキ液において、ＮａＯＨとホルマリン
は還元剤として供給する。電解メッキ及び無電解メッキ
は図３に示す条件で行う。The wiring layer 12 is formed by electroless plating or electrolytic plating. FIG. 2 shows examples of elements, ions, chemical species, components, and the like of the plating solution. In FIG. 2, in the plating solution for electrolytic plating, the additive is a nonionic surfactant, and the chloride ion is for suppressing the decomposition of the additive. EDTA · 4Na (sodium ethylenediaminetetraacetate) forms a stable chelate compound (complex with a ligand) with Cu, and can be removed with an electrolytic plating solution.
In the electroless plating solution, NaOH and formalin are supplied as reducing agents. The electrolytic plating and the electroless plating are performed under the conditions shown in FIG.
【００２０】図４はＮｉ−Ｂ合金膜のＸ線解析測定結果
を示す図である。図示するように、Ｂの組成が３．２ａ
ｔ％では堆積時（アニール前）及び４００℃のアニール
後共にＮｉ−Ｂ合金のｆｃｃ結晶構造で、バリア性能を
有する。しかし、Ｂの組成が１３．５ａｔ％、２０．０
ａｔ％ではアニール前は非晶質、４００℃でのアニール
後はＮｉ＋Ｎｉ3Ｂ（金属間化合物）となり、共にバリ
ア性を有しない。FIG. 4 is a diagram showing the results of X-ray analysis measurement of the Ni-B alloy film. As shown, the composition of B is 3.2a.
At t%, the Ni-B alloy has an fcc crystal structure at the time of deposition (before annealing) and after annealing at 400 ° C., and has barrier performance. However, the composition of B is 13.5 at%, 20.0 at%.
At at%, it becomes amorphous before annealing and becomes Ni + Ni 3 B (intermetallic compound) after annealing at 400 ° C., and both have no barrier properties.
【００２１】図５乃至図８はそれぞれＮｉ−Ｂ合金膜の
バリア性を確認するための解析結果である。図５はＣｕ
板の上に厚さ０．５８μｍのＡｇ膜を形成し、その上に
Ｂを４．２ａｔ％含有する厚さ０．１８μｍのＮｉ−Ｂ
合金膜を形成したものでの解析結果であり、図５（ａ）
及び（ｂ）はスパッタリング法で表面から順次削り取
り、現れる元素の割合を解析した結果であり、図５
（ｃ）は表面をＡＥＳ（オージエ電子分光分析）で解析
した結果を示す。また、図５（ａ）は堆積時（アニール
前）を、図５（ｂ）及び（ｃ）は４００℃のアニール後
を示す。同図から明らかなように、Ｂを４．２ａｔ％含
有するＮｉ−Ｂ合金膜で被覆した場合は、表面にＣｕが
析出することなく、Ｃｕのバリア材として優れたもので
あることがわかる。FIGS. 5 to 8 show the results of analysis for confirming the barrier properties of the Ni—B alloy film. FIG.
A 0.58 μm thick Ag film is formed on a plate, and 0.18 μm thick Ni—B containing 4.2 at% of B is formed thereon.
FIG. 5 (a) is an analysis result of an alloy film formed.
5A and 5B are the results of analyzing the ratio of the appearing elements by sequentially scraping off the surface by the sputtering method, and FIG.
(C) shows the result of analyzing the surface by AES (Auger electron spectroscopy). FIG. 5A shows the state at the time of deposition (before annealing), and FIGS. 5B and 5C show the state after annealing at 400 ° C. As is clear from the figure, when coated with a Ni-B alloy film containing 4.2 at% of B, Cu is not deposited on the surface, and is excellent as a Cu barrier material.
【００２２】図６はシリコンウエハ基板の上に厚さ０．
２μｍのＣｕ膜を形成し、その上に厚さ０．５μｍのＡ
ｇ膜を形成し、その上にＢを３．２ａｔ％含有する厚さ
０．１８μｍのＮｉ−Ｂ合金膜を形成したものでの解析
結果であり、図６（ａ）及び（ｂ）はスパッタリング法
で表面から順次削り取り、現れる元素の割合を解析した
結果であり、図６（ｃ）は表面をＡＥＳ（オージエ電子
分光分析）で解析した結果を示す。また、図６（ａ）は
堆積時（アニール前）を、図６（ｂ）及び（ｃ）は４０
０℃のアニール後を示す。同図から明らかなように、Ｂ
を３．２ａｔ％含有するＮｉ−Ｂ合金膜で被覆した場合
は、表面にＣｕが析出することなく、Ｃｕのバリア材と
して優れたものであることがわかる。FIG. 6 shows that a silicon wafer having a thickness of 0.
A Cu film having a thickness of 2 μm is formed, and an A film having a thickness of 0.5 μm is formed thereon.
FIG. 6A and FIG. 6B show the results of analysis on the case where a 0.18 μm-thick Ni—B alloy film containing 3.2 at% of B was formed thereon. FIG. 6 (c) shows the result of analyzing the ratio of the appearing elements by sequentially scraping the surface from the surface, and FIG. 6 (c) shows the result of analyzing the surface by AES (Auger electron spectroscopy). 6A shows the state at the time of deposition (before annealing), and FIGS.
Shown after annealing at 0 ° C. As is clear from FIG.
Is covered with an Ni-B alloy film containing 3.2 at%, Cu is not deposited on the surface, and is excellent as a Cu barrier material.
【００２３】図７はシリコンウエハ基板の上に厚さ０．
２μｍのＣｕ膜を形成し、その上に厚さ０．５μｍのＡ
ｇ膜を形成し、その上にＢを１３．５ａｔ％含有する厚
さ０．３３μｍのＮｉ−Ｂ合金膜を形成したものでの解
析結果であり、図７（ａ）及び（ｂ）はスパッタリング
法で表面から順次削り取り、現れる元素の割合を解析し
た結果であり、図７（ｃ）は表面をＡＥＳ（オージエ電
子分光分析）で解析した結果を示す。また、図７（ａ）
は堆積時（アニール前）を、図７（ｂ）及び（ｃ）は４
００℃のアニール後を示す。同図から明らかなように、
Ｂを１３．５ａｔ％含有するＮｉ−Ｂ合金膜で被覆した
場合は、表面にＣｕが析出し、Ｃｕのバリア材として不
適切であることがわかる。FIG. 7 shows the case where the thickness of the silicon wafer is 0.
A Cu film having a thickness of 2 μm is formed, and an A film having a thickness of 0.5 μm is formed thereon.
7 (a) and 7 (b) show the results of analysis on a Ni-B alloy film having a thickness of 0.33 μm containing 13.5 at% of B formed thereon. FIG. 7 (c) shows the results of analysis of the ratio of the appearing elements by successively shaving off the surface by the method. FIG. 7 (c) shows the results of analyzing the surface by AES (Auger electron spectroscopy). FIG. 7 (a)
7 shows the state at the time of deposition (before annealing), and FIGS.
Shown after annealing at 00 ° C. As is clear from the figure,
In the case of coating with a Ni-B alloy film containing 13.5 at% of B, Cu precipitates on the surface, which indicates that it is inappropriate as a Cu barrier material.
【００２４】図８はシリコンウエハ基板の上に厚さ０．
２μｍのＣｕ膜を形成し、その上に厚さ０．５μｍのＡ
ｇ膜を形成し、その上にＢを１２．２ａｔ％含有する厚
さ０．５９μｍのＮｉ−Ｂ合金膜を形成したものでの解
析結果であり、図８（ａ）及び（ｂ）はスパッタリング
法で表面から順次削り取り、現れる元素の割合を解析し
た結果であり、図８（ｃ）は表面をＡＥＳ（オージエ電
子分光分析）で解析した結果を示す。また、図８（ａ）
は堆積時（アニール前）を、図８（ｂ）及び（ｃ）は４
００℃のアニール後を示す。同図から明らかなように、
Ｂを１２．２ａｔ％含有するＮｉ−Ｂ合金膜で被覆した
場合は、表面にＣｕが析出し、Ｃｕのバリア材として不
適切であることがわかる。FIG. 8 shows that a silicon wafer having a thickness of 0.
A Cu film having a thickness of 2 μm is formed, and an A film having a thickness of 0.5 μm is formed thereon.
FIG. 8 (a) and FIG. 8 (b) show the results of analysis in which a 0.59 μm-thick Ni—B alloy film containing 12.2 at% of B was formed thereon. FIG. 8C shows the result of analyzing the ratio of elements appearing by sequentially scraping off the surface by the method, and FIG. 8C shows the result of analyzing the surface by AES (Auger electron spectroscopy). FIG. 8 (a)
8 shows the time of deposition (before annealing), and FIGS.
Shown after annealing at 00 ° C. As is clear from the figure,
In the case of coating with a Ni—B alloy film containing 12.2 at% of B, Cu precipitates on the surface, which is unsuitable as a Cu barrier material.
【００２５】上記のようにＢの含有率が１０ａｔ％
（０．０１ａｔ％〜１０ａｔ％）であるＮｉ−Ｂ合金は
ｆｃｃ結晶構造なので、Ｃｕ配線の被覆材として使用す
ることで、従来のＴｉＮに比べて低抵抗で、Ｃｕ配線と
の接合力が強く、且つＣｕの拡散防止効果を発揮するこ
とが期待できる。従って、例えば半導体デバイスにおい
て、多層配線を形成する場合、上記Ｎｉ−Ｂ合金膜を配
線のバリア材として用いるとバリア材にＴｉＮ合金膜を
用いる従来例に比較し、比抵抗が低い配線を提供でき、
半導体デバイスの高密度化、高速化に貢献することが期
待できる。As described above, the content of B is 10 at%.
(0.01 at% to 10 at%) Ni-B alloy has an fcc crystal structure, and therefore, by using it as a coating material for Cu wiring, has a lower resistance than conventional TiN and a stronger bonding force with Cu wiring. In addition, it can be expected to exhibit a Cu diffusion preventing effect. Therefore, for example, in the case of forming a multilayer wiring in a semiconductor device, when the above-described Ni-B alloy film is used as a wiring barrier material, a wiring having a lower specific resistance can be provided as compared with the conventional example using a TiN alloy film as a barrier material. ,
It can be expected to contribute to higher density and higher speed of semiconductor devices.
【００２６】なお、図１では、ＳｉＯ2の絶縁膜１０に
設けられた溝内面にＮｉ−Ｂ合金膜のバリア層１１を形
成し、該内面がバリア層１１で囲まれた溝内にＣｕから
なる配線層１２を電解メッキ又は無電解メッキにより埋
め込み方式で形成する例を示したが、バリア層１１の形
状はこれに限定されるものではなく、例えば、図９に示
すように配線層１２をバリア層で囲む形状であっても良
い。In FIG. 1, a barrier layer 11 of a Ni—B alloy film is formed on the inner surface of the groove provided in the insulating film 10 of SiO 2 , and the inner surface is formed of Cu in the groove surrounded by the barrier layer 11. Although the example in which the wiring layer 12 is formed in a buried manner by electrolytic plating or electroless plating has been described, the shape of the barrier layer 11 is not limited to this. For example, as shown in FIG. The shape may be surrounded by a barrier layer.
【００２７】[0027]
【発明の効果】以上説明したように本願各請求項に記載
の発明によれば、配線と該配線に隣接する絶縁物の間に
介在させるバリア層にＢを含有するＮｉ合金材を用いる
ので、配線との接合が強く、低比抵抗（ρ）で、配線と
絶縁膜との間で生じる相互拡散を防止でき、半導体デバ
イスの高密度化、高速化に貢献することが期待できる。As described above, according to the invention described in the claims of the present application, the Ni alloy material containing B is used for the barrier layer interposed between the wiring and the insulator adjacent to the wiring. It has a strong junction with the wiring, has a low specific resistance (ρ), can prevent interdiffusion between the wiring and the insulating film, and can be expected to contribute to higher density and higher speed of the semiconductor device.
【図１】本発明の半導体基板配線のバリア層の構成例を
示す図である。FIG. 1 is a diagram showing a configuration example of a barrier layer of a semiconductor substrate wiring according to the present invention.
【図２】Ｃｕ配線を形成するメッキ液の組成例を示す図
である。FIG. 2 is a diagram illustrating a composition example of a plating solution for forming a Cu wiring.
【図３】Ｃｕ配線を形成するメッキ条件例を示す図であ
る。FIG. 3 is a diagram showing an example of plating conditions for forming a Cu wiring.
【図４】Ｎｉ−Ｂ合金膜のＸ線解析測定結果を示す図で
ある。FIG. 4 is a diagram showing an X-ray analysis measurement result of a Ni—B alloy film.
【図５】Ｎｉ−Ｂ合金膜のバリア性を確認するための解
析結果を示す図である。FIG. 5 is a diagram showing an analysis result for confirming a barrier property of the Ni—B alloy film.
【図６】Ｎｉ−Ｂ合金膜のバリア性を確認するための解
析結果を示す図である。FIG. 6 is a diagram showing an analysis result for confirming a barrier property of the Ni—B alloy film.
【図７】Ｎｉ−Ｂ合金膜のバリア性を確認するための解
析結果を示す図である。FIG. 7 is a diagram showing an analysis result for confirming a barrier property of the Ni—B alloy film.
【図８】Ｎｉ−Ｂ合金膜のバリア性を確認するための解
析結果を示す図である。FIG. 8 is a diagram showing an analysis result for confirming a barrier property of the Ni—B alloy film.
【図９】本発明の半導体基板配線のバリア層の他の構成
例を示す図である。FIG. 9 is a diagram showing another configuration example of the barrier layer of the semiconductor substrate wiring of the present invention.
１０ ＳｉＯ2膜 １１ バリア層 １２ 配線層10 SiO 2 film 11 barrier layer 12 interconnect layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 江澤 弘和 神奈川県横浜市磯子区新杉田町８番地 株 式会社東芝横浜事業所内 (72)発明者 宮田 雅弘 神奈川県横浜市磯子区新杉田町８番地 株 式会社東芝横浜事業所内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hirokazu Ezawa 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture Inside Toshiba Yokohama Office (72) Masahiro Miyata 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Toshiba Yokohama Office
Claims (8)
する絶縁膜との間に設けられ、該配線と該絶縁膜の間で
生じる相互拡散を防止するバリア層であって、前記バリ
ア層はＢ（ボロン）を含有するＮｉ（ニッケル）合金材
からなることを特徴とする半導体基板配線のバリア層。A barrier layer provided between a wiring provided on a semiconductor substrate and an insulating film adjacent to the wiring, for preventing mutual diffusion occurring between the wiring and the insulating film; Is a barrier layer for semiconductor substrate wiring, comprising a Ni (nickel) alloy material containing B (boron).
充填結晶構造）を保持していることを特徴とする請求項
１に記載の半導体基板配線のバリア層。2. The barrier layer according to claim 1, wherein the Ni alloy material has an fcc crystal structure (closest-packed crystal structure).
ａｔ％〜１０ａｔ％であることを特徴とする請求項２に
記載の半導体基板配線のバリア層。3. The B content of said Ni alloy material is 0.01
The barrier layer of a semiconductor substrate wiring according to claim 2, wherein the barrier layer is at% to 10 at%.
ることを特徴とする請求項２又は３に記載の半導体基板
配線のバリア層。4. The barrier layer according to claim 2, wherein the thickness of the barrier layer is 100 ° or more.
たことを特徴とする請求項２又は３又は４に記載の半導
体基板配線のバリア層。5. The barrier layer according to claim 2, wherein the barrier layer is formed by electroless plating.
ことを特徴とする請求項２又は３又は４に記載の半導体
基板配線のバリア層。6. The barrier layer according to claim 2, wherein the barrier layer is formed by electrolytic plating.
ことを特徴とする請求項２又は３又は４に記載の半導体
基板配線のバリア層。7. The barrier layer for semiconductor substrate wiring according to claim 2, wherein the barrier layer is formed by a sputtering method.
とを特徴とする請求項２又は３又は４に記載の半導体基
板配線のバリア層。8. The barrier layer according to claim 2, wherein the barrier layer is formed by a CVD method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27049297A JP3554665B2 (en) | 1997-09-17 | 1997-09-17 | Barrier layer and wiring structure of semiconductor substrate wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27049297A JP3554665B2 (en) | 1997-09-17 | 1997-09-17 | Barrier layer and wiring structure of semiconductor substrate wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1197444A true JPH1197444A (en) | 1999-04-09 |
| JP3554665B2 JP3554665B2 (en) | 2004-08-18 |
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ID=17487041
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27049297A Expired - Lifetime JP3554665B2 (en) | 1997-09-17 | 1997-09-17 | Barrier layer and wiring structure of semiconductor substrate wiring |
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| Country | Link |
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| JP (1) | JP3554665B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002503766A (en) * | 1998-02-12 | 2002-02-05 | エーシーエム リサーチ，インコーポレイティド | Plating equipment and method |
| KR100443514B1 (en) * | 2001-12-22 | 2004-08-09 | 주식회사 하이닉스반도체 | method for manufacturing a diffusion barrier layer |
| JP2006526070A (en) * | 2003-05-09 | 2006-11-16 | ビーエーエスエフ アクチェンゲゼルシャフト | Composition for electroless plating of ternary materials for use in the semiconductor industry |
-
1997
- 1997-09-17 JP JP27049297A patent/JP3554665B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002503766A (en) * | 1998-02-12 | 2002-02-05 | エーシーエム リサーチ，インコーポレイティド | Plating equipment and method |
| KR100443514B1 (en) * | 2001-12-22 | 2004-08-09 | 주식회사 하이닉스반도체 | method for manufacturing a diffusion barrier layer |
| JP2006526070A (en) * | 2003-05-09 | 2006-11-16 | ビーエーエスエフ アクチェンゲゼルシャフト | Composition for electroless plating of ternary materials for use in the semiconductor industry |
| US7850770B2 (en) | 2003-05-09 | 2010-12-14 | Basf Aktiengesellschaft | Compositions for the currentless deposition of ternary materials for use in the semiconductor industry |
| US9062378B2 (en) | 2003-05-09 | 2015-06-23 | Basf Aktiengesellschaft | Compositions for the currentless deposition of ternary materials for use in the semiconductor industry |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3554665B2 (en) | 2004-08-18 |
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