JPH1196779A - Flash type memory, its controlling method, storage device, and computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of times of rewriting a flash type memory and to enable executing a program on an expanded storage device. SOLUTION: A header area and a program data area are arranged for each block in a physical address of a flash memory 12 side. However, a header area and a program data area for each block are arranged continuously in a logical address of a processor 10 side. When data included a program data area (n) is rewritten, both of a block of the data area (n) and a block of a corresponding head area are required to rewrite. However, the program data area (n) is in the same block with the corresponding head area when it is considered on the physical address. Therefore, only the block may be rewritten.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory, a method of managing the same, a storage device, and a computer system. More specifically, the present invention relates to an improvement of an efficient flash memory management method.

[0002]

BACKGROUND OF THE INVENTION Generally, electrically erasable programmable read only memories (EEPROMs), including flash type floating gate transistors, are readily available on the market today. These so-called flash memories are non-volatile memories similar in function and performance to EPROM memories, and further have a function of enabling in-circuit programmable operation for erasing blocks divided in the memory. In a flash memory, the contents of a previously written block area are rewritten by erasing the block area in advance.

In a typical computer system, a program of an operating system (hereinafter, simply referred to as "OS") manages data in a data storage device of the system. The attributes of the data storage device that are necessary and sufficient to achieve compatibility with the OS program are that data can be read from and written to any location on the data storage device. is there. However, in the case of a flash memory, data cannot be written to an area to which data has already been written unless data in that area is erased. For this reason, flash memory is not compatible with typical existing OS programs.

[0004] Focusing on such a point, software that enables a flash memory to be managed by an existing OS program has been proposed in the prior art.
In this prior art program, the flash memory is operated as a "write once read multiple times" device, or is operated as a "write multiple times read multiple times" device. The former is a device that cannot reuse a memory area that has been previously written, and can be used as an auxiliary storage device or an extended storage device. In the latter, an auxiliary storage device (semiconductor file storage device) having a control for reducing the number of times of rewriting of the flash memory is provided in the area in which a previously written memory area can be reused.

[0005]

According to the apparatus disclosed in the prior art as described above, a ROM executable is not provided on an extended storage device using a flash memory without a control structure for reducing the number of rewrites. Running a simple program. That is, when rewriting data in the flash memory, it is necessary to erase all blocks at once and then store the data. An auxiliary storage device (semiconductor file storage device) is known as a device having a control structure for reducing the number of rewrites of the flash memory, but a device capable of executing a program on an extended storage device using a flash memory. Not in In order to reduce the number of rewrites in the auxiliary storage device, there is a method of storing the information (the number of rewrites table) in a different memory, but the cost increases. Further, in the method of storing data on the same flash memory, data cannot be arranged completely continuously.

The present invention focuses on the above points,
An object of the present invention is to provide a device having a control structure for reducing the number of times of rewriting of a flash memory on an extended storage device using the flash memory. Another object is to enable execution of a program on an extended storage device without loading the program into a main storage device. Still another object is to provide an auxiliary storage device using a flash memory as a memory management device that converts a continuous logical address to a discontinuous physical address while having a control structure for reducing the number of times of rewriting. Is to reduce the overhead for access and to enable high-speed access to the data area block.

[0007]

In order to achieve the above object, a flash memory according to the present invention comprises a first area for storing management information of its own block and a second area for storing main information. , Provided for each block. In the storage device of the present invention, a first area or a second area of an adjacent block of the flash memory is
An address conversion means for converting a physical address and a logical address so as to be continuous logical addresses is provided. The address conversion means is constituted by, for example, wired logic. Further, the management information includes, for example, the number of times of writing of the block and the time of erasing the block. Another feature of the present invention is that, when erasing a block, if the number of times of writing is the same, a control means for preferentially selecting a block having the older erase time is provided.

[0008] The computer system of the present invention is characterized in that it includes a processor for executing a program stored in the second area on the flash memory. A flash memory management method according to the present invention is characterized in that a first area for storing management information of its own block and a second area for storing main information are provided for each block. One of the main modes is characterized in that the conversion between the physical address and the logical address is performed so that the first area of the adjacent block is a continuous logical address. Another embodiment is characterized in that the conversion between the physical address and the logical address is performed so that the second area of the adjacent block has a continuous logical address.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

[0010]

Embodiments of the present invention will be described below in detail. The present invention relates to an extended or auxiliary storage device including a processor 10, a flash memory 12, and a control device 14 thereof, as shown in FIG.
The present invention is applied to a computer system including an M (main storage device) 16. In order to reduce the number of times of rewriting, the flash memory 12 stores an area (header area) having rewriting information (erase information) in units of blocks of the flash memory 12 and programs and data on the flash memory 12. Area (program data area)
(See FIG. 4 described later). The flash memory control device 14 reads, writes,
A signal such as a chip select is generated, and the flash memory 12 is interfaced from the processor 10 (I / F).
Play a role.

In the header area, for example, the number of times of erasing and the time are described. Here, if the logical address of the processor 10 can be divided into units of the number of blocks of the flash memory 12 and stored in the flash memory 12,
The number of times of rewriting of the flash memory 12 can be reduced and the method of managing the flash memory 12 can be simplified. That is, if the data to be rewritten extends over a plurality of blocks, the rewriting process must be performed on the plurality of blocks. However, if data to be rewritten is in one block, only that block needs to be rewritten, and the number of times of rewriting of the flash memory 12 can be reduced to simplify management.

Therefore, the memory mapping shown in FIG. 3 is performed using the device shown in FIG. That is, the header area and the program / data area are divided into units of the number of blocks. Then, the divided areas are efficiently arranged in block units in the flash memory. That is, the divided header area and the divided program / data area which need to be rewritten at the same time are arranged so as to be included in the same block. Such an arrangement is similar to processor 1
This is realized by an address translation device 20 that translates a logical address of 0 into a physical address of the flash memory 12.

FIG. 4 shows an example of a memory map of the flash memory 12 having a block structure. This example is a flash memory capable of storing L × (m + 1) bytes, each block being L bytes and having a total of m + 1 blocks. Assuming that P bytes are required as a header area having information such as the number of times of rewriting of the flash memory 12 to manage each block, P × (m +
1) A byte header area is required. Therefore, this system has a program data area of (LP) × (m + 1) bytes.

The address conversion device 18 shown in FIG. 2 performs conversion on the flash memory 12 having such an area configuration. More specifically, as shown in FIG. 5, in the logical address of the processor 10, the header area of each block is sequentially arranged as block 0, block 1,..., Block m. On the other hand, in the program data area, the block 0, block 1,... As a result, the header area of each block is arranged with a continuous logical address. Similarly, the program data area of each block is also
They are arranged at consecutive logical addresses.

In such an address arrangement, for example, it is assumed that it is necessary to rewrite data included in the program data area n. In terms of the logical address of the processor 10, a total of two blocks, the block including the header area of the program data area n and the block corresponding to the program data area n, must be rewritten. However, when viewed from the physical address of the flash memory 12, the program data area n is in the same block as the corresponding header area.
Therefore, only that block needs to be rewritten.

As described above, according to this embodiment, the high-speed management program for reducing the number of times of rewriting of the flash memory reads the information in the header area, and can easily realize rewriting and additional writing of the execution program and data. In addition, since the blocks of the program data area are continuously arranged on the logical address, it is possible to realize an extended storage device and an auxiliary storage device having a data structure with no useless empty space, and a flash memory. The operation of the execution program becomes possible. Furthermore, since the header area is stored in a block managed by itself, no separate memory area is required for the header area.

A method of managing each block of the flash memory will be described.
h (hexadecimal notation) "is stored. Since the flash memory cannot be used as an extended storage device or an auxiliary storage device unless it is initialized, the flash memory stores the rewrite count of 0 and the current time in the header area of block 0, and similarly stores the rewrite count of 0 in the header area of block 1. The current time is stored, and so on until the last block is stored in ascending order.

In a system using a flash memory as an extended storage device or an auxiliary storage device, it is customary to store data and an execution program in a memory in a structure to be additionally written. In the structure to be added, the updated data and the execution program are added, but the previous data and the execution program are invalidated. Then, as the data and the execution program are repeatedly updated, a useless memory area is expanded. Therefore, it is necessary to relocate the memory area on the flash memory. At this time, as a candidate for a block to be erased, erasing is performed with priority given to a block having a small number of rewrites. At this time, when there are a plurality of blocks having the same number of rewrites and one of the blocks needs to be erased, the erase is performed with priority given to the earlier block erase time.

When actually erasing a block,
The previous number of rewrites “U” stored in the header area of the block is temporarily stored in another memory or register, and then the target block (header area and data program) is erased by a program that erases the block of the flash memory. Area) and initialize.
Immediately thereafter, a value “U + 1” obtained by incrementing the previous rewrite count by “1” is written into the header area of the block, and at the same time, the current time is also written. And if necessary,
Relocate the data program. Hereinafter, examples of the present embodiment will be described.

[0020]

Embodiment 1 As shown in FIG. 1, a processor 10, which is a general-purpose CPU or a general-purpose microcomputer, a high-speed accessible RAM 16, a flash memory 12, and an extended storage device or an auxiliary storage device including its control device 14 are provided. In such a system, in this embodiment, the flash memory 1 used for the extended storage device or the auxiliary storage device is used.
Suppose that a device having a total of 32 64 Kbyte blocks of 2 Mbit × 8 is mounted as 2.

The flash memory 12 has a memory map of physical addresses as shown in FIG. Each block has its own header area for each block to be managed by the OS program or the control program. In the header area, the number of times the block has been erased, the time at which the block was erased, and the like are recorded in the header area in a structure as shown in FIG. 7 and has a capacity of 16 bytes. The addresses shown in FIG. 7 are physical addresses of the flash memory 12. With reference to the contents stored in the header area of the block n, the OS program or the control program manages erasing and rewriting of the block n.

The physical address of the flash memory 12 is
It is converted into a logical address as seen from the processor 10, and
Alternatively, as shown in FIG. 5, the header area of each block and the blocks of the program / data area become continuous. An example of a calculation formula for conversion between the logical address and the physical address is as follows. The numerical value n is a number from 0 to 31 in decimal notation.
A numerical value obtained by converting n into a hexadecimal number is defined as N (h). Change the value of the physical address to “hexadecimal: [PA (h)], PA
[20: 0] ”, and the value of the logical address is“ hexadecimal number:
[LA (h)], LA [20: 0] "and the block N
The following shows the conversion equation using (h).

IF (000000h ≦ LA (h) ≦ 00FFEFh) PA (h) = LA (h) ELSE IF (00FFF0h ≦ LA (h) ≦ 01FFDFh) PA (h) = LA (h) +10 (h) ELSE IF (00FFE0h ≦ LA (h) ≦ 02FFCFh) PA (h) = LA (h) +20 (h) ELSE IF (02FFD0h ≦ LA (h) ≦ 03FFBFh) PA (h) = LA (h) +30 (h) ELSE IF (03FFC0h ≦ LA (h) ≦ 04FFAFh) PA (h) = LA (h) +40 (h) ELSE IF (04FFB0h ≦ LA (h) ≦ 05FF9Fh) PA (h) = LA (h) +50 (h) ELSE IF (05FFA0h ≦ LA (h) ≦ 06FF8Fh) PA (h) = LA (h) +60 (h) ELSE IF (0 6FF90h ≦ LA (h) ≦ 07FF7Fh) PA (h) = LA (h) +70 (h) ELSE IF (07FF80h ≦ LA (h) ≦ 08FF6Fh) PA (h) = LA (h) +80 (h) ELSE IF ( 08FF70h ≦ LA (h) ≦ 09FF5Fh) PA (h) = LA (h) +90 (h) ELSE IF (09FF60h ≦ LA (h) ≦ 0AFF4Fh) PA (h) = LA (h) + A0 (h) ELSE IF ( 0AFF50h ≦ LA (h) ≦ 0BFF3Fh) PA (h) = LA (h) + B0 (h) ELSE IF (0BFF40h ≦ LA (h) ≦ 0CFF2Fh) PA (h) = LA (h) + C0 (h) ELSE IF ( 0CFF30h ≦ LA (h) ≦ 0DFF1Fh) PA (h) = LA (h) + D0 (h) ELSE IF (0DFF2 h ≦ LA (h) ≦ 0EFF0Fh) PA (h) = LA (h) + E0 (h) ELSE IF (0EFF10h ≦ LA (h) ≦ 0FFEFFFh) PA (h) = LA (h) + F0 (h) ELSE IF ( 0FFFF00h ≦ LA (h) ≦ 10FEEFh) PA (h) = LA (h) +100 (h) ELSE IF (10FEF0h ≦ LA (h) ≦ 11FEDFh) PA (h) = LA (h) + 110F (h) ELSE IF ( 11FEEE0h ≦ LA (h) ≦ 12FECFh) PA (h) = LA (h) +120 (h) ELSE IF (12FED0h ≦ LA (h) ≦ 13FEBFh) PA (h) = LA (h) +130 (h) ELSE IF ( 13FEC0h ≦ LA (h) ≦ 14FEAFh) PA (h) = LA (h) +140 (h) ELSE IF (14F B0h ≦ LA (h) ≦ 15FE9Fh) PA (h) = LA (h) +150 (h) ELSE IF (15FEA0h ≦ LA (h) ≦ 16FE8Fh) PA (h) = LA (h) +160 (h) ELSE IF ( 16FE90h ≦ LA (h) ≦ 17FE7Fh) PA (h) = LA (h) +170 (h) ELSE IF (17FE80h ≦ LA (h) ≦ 18FE6Fh) PA (h) = LA (h) +180 (h) ELSE IF ( 18FE70h ≦ LA (h) ≦ 19FE5Fh) PA (h) = LA (h) +190 (h) ELSE IF (19FE60h ≦ LA (h) ≦ 1AFE4Fh) PA (h) = LA (h) + 1A0 (h) ELSE IF ( 1AFE50h ≦ LA (h) ≦ 1BFE3Fh) PA (h) = LA (h) + 1B0 (h) ELSE IF (1 BFE40h ≦ LA (h) ≦ 1CFE2Fh) PA (h) = LA (h) + 1C0 (h) ELSE IF (1CFE30h ≦ LA (h) ≦ 1DFE1Fh) PA (h) = LA (h) + 1D0 (h) ELSE IF ( 1DFE20h ≦ LA (h) ≦ 1EFE0Fh) PA (h) = LA (h) + 1E0 (h) ELSE IF (1EFE10h ≦ LA (h) ≦ 1FFDFFh) PA (h) = LA (h) + 1F0 (h) ELSE IF ( 1FFE00h≤LA (h) ≤1FFE0Fh) PA (h) = LA (h) -1EFE10 (h) ELSE IF (1FFE10h≤LA (h) ≤1FFE1Fh) PA (h) = LA (h) -1DFE20 (h) ELSE IF (1FFE20h ≦ LA (h) ≦ 1FFE2Fh) PA (h) = LA (h) −1CFE30 (H) ELSE IF (1FFE30h ≦ LA (h) ≦ 1FFE3Fh) PA (h) = LA (h) −1BFE40 (h) ELSE IF (1FFE40h ≦ LA (h) ≦ 1FFE4Fh) PA (h) = LA (h) -1AFE50 (h) ELSE IF (1FFE50h ≦ LA (h) ≦ 1FFE5Fh) PA (h) = LA (h) −19FE60 (h) ELSE IF (1FFE60h ≦ LA (h) ≦ 1FFE6Fh) PA (h) = LA ( h) -18FE70 (h) ELSE IF (1FFE70h ≦ LA (h) ≦ 1FFE7Fh) PA (h) = LA (h) −17FE80 (h) ELSE IF (1FFE80h ≦ LA (h) ≦ 1FFE8Fh) PA (h) = LA (h) -16FE90 (h) ELSE IF (1FFE90h ≦ LA (h) ≦ 1F E9Fh) PA (h) = LA (h) -15FEA0 (h) ELSE IF (1FFEA0h ≦ LA (h) ≦ 1FFEAFh) PA (h) = LA (h) −14FEB0 (h) ELSE IF (1FFEB0h ≦ LA (h) ) ≦ 1FFEBFh) PA (h) = LA (h) −13FEC0 (h) ELSE IF (1FFEC0h ≦ LA (h) ≦ 1FFECFh) PA (h) = LA (h) −12FED0 (h) ELSE IF (1FFED0h ≦ LA) (H) ≦ 1FFEDFh) PA (h) = LA (h) −11FEE0 (h) ELSE IF (1FFEE0h ≦ LA (h) ≦ 1FFEEFh) PA (h) = LA (h) −10FFEF0 (h) ELSE IF (1FFEF0h) ≦ LA (h) ≦ 1FFEFFh) PA (h) = LA (h) −FFFF00 (h) E SE IF (1FFFF00h ≦ LA (h) ≦ 1FFFOFh) PA (h) = LA (h) −EFF10 (h) ELSE IF (1FFF10h ≦ LA (h) ≦ 1FFF1Fh) PA (h) = LA (h) −DFF20 ( h) ELSE IF (1FFF20h ≦ LA (h) ≦ 1FFF2Fh) PA (h) = LA (h) −CFF30 (h) ELSE IF (1FFF30h ≦ LA (h) ≦ 1FFF3Fh) PA (h) = LA (h) − BFF40 (h) ELSE IF (1FFF40h ≦ LA (h) ≦ 1FFF4Fh) PA (h) = LA (h) −AFF50 (h) ELSE IF (1FFF50h ≦ LA (h) ≦ 1FFF5Fh) PA (h) = LA (h) ) -9FF60 (h) ELSE IF (1FFF60h ≦ LA (h) ≦ 1FFF6Fh) PA (h) = LA (h) -8FF70 (h) ELSE IF (1FFF70h ≦ LA (h) ≦ 1FFF7Fh) PA (h) = LA (h) -7FF80 (h) ELSE IF (1FFF80h ≦ LA (h) ≦ 1FFF8Fh) PA ( h) = LA (h) -6FF90 (h) ELSE IF (1FFF90h ≦ LA (h) ≦ 1FFF9Fh) PA (h) = LA (h) −5FFA0 (h) ELSE IF (1FFFA0h ≦ LA (h) ≦ 1FFFAFh) PA (h) = LA (h) -4FFB0 (h) ELSE IF (1FFFB0h ≦ LA (h) ≦ 1FFFBFh) PA (h) = LA (h) -3FFC0 (h) ELSE IF (1FFFC0h ≦ LA (h) ≦ 1FFFCFh) PA (h) = LA (h) −2FFD0 (h) ELSE IF (1FFFD0h ≦ LA h) ≦ 1FFFDFh) PA (h) = LA (h) −1FFE0 (h) ELSE IF (1FFFE0h ≦ LA (h) ≦ 1FFFEFFh) PA (h) = LA (h) −FFF0 (h) ELSE IF (1FFFF0h ≦ LA (h) ≦ 1FFFFFh) PA (h) = LA (h)

As an example, the first Means that the logical address LA (h) is 000000h and 00F
When it is between FEFh, it means that the physical address PA (h) has the same value as the logical address LA (h).

Similarly, ELSE IF (00FFF0h ≦ LA (h) ≦ 01FFDFh) PA (h) = LA (h) +10 (h) is obtained when logical addresses LA (h) are 00FFF0h and 01FFF.
When it is between FDFh, it means that the physical address PA (h) is a value obtained by adding 10 (h) to the logical address LA (h). Hereinafter, the same applies.

Next, the address translation device 18 of FIG. 2 is configured by wired logic using the above-described address translation formula, and takes an I / F with the processor 10 together with the control device 14 of the flash memory 12. The block management method of the flash memory 12 according to the present embodiment will be described. As described above, first, the header area of each block is initialized (initialized). An example of the initialization is as follows.

In the header area of the block 0, the physical address PA [20: 0] is changed from "00FFFDh" to "00
Write "00h" to each of "FFFFh"
The current time is written from “FFF6h” to “00FFFBh”, respectively. Next, in the header area of block 1, "01FFFD" of the physical address PA [20: 0] is set.
"00h" is written to "01FFFFh" from "h", and the current time is written to "01FFFBh" from "01FFFF6h". ………… In the header area of the ascending block xxh, the physical address PA
“XxFFFFh” to “xxFFFF” in [20: 0]
h ”is written with“ 00h ”, and“ xxFFFF6
h ”to“ xxFFFBh ”respectively. ...... In the header area of the last block 1Fh, "1FFFFD" of the physical address PA [20: 0] is used.
h ”to“ 1FFFFFFh ”and“ 00h ”respectively, and“ 1FFFF6h ”to“ 1FFFFBh ”to write the current times respectively, thereby completing the initialization.

In the present system using a flash memory as an extended storage device or an auxiliary storage device, data, execution programs, and the like are newly updated by a method of appending. This method itself is the same as the conventional method.
However, each time the data or the execution program is updated, an unnecessary memory area is expanded. Therefore, the data and the unnecessary
In order to delete the execution program and the memory fragmentation, the memory data is rearranged (defragmented) to reduce unnecessary memory areas and enlarge the reuse area. At this time, as described above, as a candidate for the block to be erased, the block with the smaller number of rewrites is preferentially erased. If the number of rewrites is the same and there are two or more candidates, the erase of the candidate with the oldest erase time is prioritized and erased. This processing is performed by the processor 10 by the defragmentation program.
Done through.

Specifically, the number of rewrites "V" stored in the header area of the preferentially selected block is stored in another memory or register, and then a program (erase) for erasing the corresponding block is performed. Move to execution of the erase sequence routine). After this program ends,
The block has been erased. Then, the header area is immediately updated. That is, the number of rewrites is newly written as a value “V + 1” obtained by incrementing the previous number by one, and the current time is further written. After this work is completed, the state is returned to a state where normal data and the like can be additionally written and read.

[0030]

Embodiment 2 In this embodiment 2, a flash memory 12 used for an extended storage device or an auxiliary storage device is
The system configuration is such that a 1 Mbit × 16 block having a total of 32 blocks of 32 kilowords is mounted. This flash memory has a memory map of physical addresses as shown in FIG. As in the above embodiment, each block has its own header area for each block to be managed by the OS program or control program. The contents, such as the number of times of erasure of the block and the erasure time, take eight words in a structure as shown in FIG. The addresses shown in FIG. 9 are physical addresses of the flash memory 12. With reference to the contents stored in the header area of the block n, the OS program or the control program manages block erasure and rewrite of the block n. This management method can be handled by the same method as in the first embodiment.

Next, address conversion is performed so that the header area of each block and the blocks of the program data area are continuous. An example of a calculation formula for the address conversion from the logical address to the physical address is as follows. The numerical value n, numerical value N (h), physical address value [PA (h)], PA [20: 1], logical address value [LA (h)], LA [20: 1] are the same as those described above. Same as the example.

IF (00000h ≦ LA (h) ≦ 07FF7h) PA (h) = LA (h) ELSE IF (07FF8h ≦ LA (h) ≦ 0FFEFh) PA (h) = LA (h) +8 (h) ELSE IF (0FFF0h ≦ LA (h) ≦ 17FE7h) PA (h) = LA (h) +10 (h) ELSE IF (17FE8h ≦ LA (h) ≦ 1FFDFh) PA (h) = LA (h) +18 (h) ELSE IF (1FFE0h ≦ LA (h) ≦ 27FD7h) PA (h) = LA (h) +20 (h) ELSE IF (27FD8h ≦ LA (h) ≦ 2FFCFh) PA (h) = LA (h) +28 (h) ELSE IF (2FFD0h ≦ LA (h) ≦ 37FC7h) PA (h) = LA (h) +30 (h) ELSE IF (37FC8h ≦ LA (h) ≦ 3FF BFh) PA (h) = LA (h) +38 (h) ELSE IF (3FFC0h ≦ LA (h) ≦ 47FB7h) PA (h) = LA (h) +40 (h) ELSE IF (47FB8h ≦ LA (h) ≦ 4FFAFh) PA (h) = LA (h) +48 (h) ELSE IF (4FFB0h ≦ LA (h) ≦ 57FA7h) PA (h) = LA (h) +50 (h) ELSE IF (57FA8h ≦ LA (h) ≦ 5FF9Fh) PA (h) = LA (h) +58 (h) ELSE IF (5FFA0h ≦ LA (h) ≦ 67F97h) PA (h) = LA (h) +60 (h) ELSE IF (67F98h ≦ LA (h) ≦ 6FF8Fh) PA (h) = LA (h) +68 (h) ELSE IF (6FF90h ≦ LA (h) ≦ 77F87h) PA (h) = LA (h) +70 (H) ELSE IF (77F88h ≦ LA (h) ≦ 7FF7Fh) PA (h) = LA (h) +78 (h) ELSE IF (7FF80h ≦ LA (h) ≦ 87F77h) PA (h) = LA (h) +80 (H) ELSE IF (87F78h ≦ LA (h) ≦ 8FF6Fh) PA (h) = LA (h) +88 (h) ELSE IF (8FF70h ≦ LA (h) ≦ 97F67h) PA (h) = LA (h) +90 (H) ELSE IF (97F68h ≦ LA (h) ≦ 9FF5Fh) PA (h) = LA (h) +98 (h) ELSE IF (9FF60h ≦ LA (h) ≦ A7F57h) PA (h) = LA (h) + A0 (H) ELSE IF (A7F58h ≦ LA (h) ≦ AFF4Fh) PA (h) = LA (h) + A8 (h) ELSE IF (AFF50h ≦ A (h) ≦ B7F47h) PA (h) = LA (h) + B0 (h) ELSE IF (B7F48h ≦ LA (h) ≦ BFF3Fh) PA (h) = LA (h) + B8 (h) ELSE IF (BFF40h ≦ LA (h) ≦ C7F37h) PA (h) = LA (h) + C0 (h) ELSE IF (C7F38h ≦ LA (h) ≦ CFF2Fh) PA (h) = LA (h) + C8 (h) ELSE IF (CFF30h ≦ LA (h) ≦ D7F27h) PA (h) = LA (h) + D0 (h) ELSE IF (D7F28h ≦ LA (h) ≦ DFF1Fh) PA (h) = LA (h) + D8 (h) ELSE IF (DFF20h ≦ LA (h) ≦ E7F17h) PA (h) = LA (h) + E0 (h) ELSE IF (E7F18h ≦ LA (h) ≦ EFF0Fh) PA (h) LA (h) + E8 (h) ELSE IF (EFF10h ≦ LA (h) ≦ F7F07h) PA (h) = LA (h) + F0 (h) ELSE IF (F7F08h ≦ LA (h) ≦ FFEFFh) PA (h) = LA (h) + F8 (h) ELSE IF (FFF00h ≦ LA (h) ≦ FFF07h) PA (h) = LA (h) −F7F08h ELSE IF (FFF08h ≦ LA (h) ≦ FFF0Fh) PA (h) = LA ( h) -EFF10h ELSE IF (FFF10h ≦ LA (h) ≦ FFF17h) PA (h) = LA (h) −E7F18h ELSE IF (FFF18h ≦ LA (h) ≦ FFF1Fh) PA (h) = LA (h) −DFF20h ELSE IF (FFF20h ≦ LA (h) ≦ FFF27h) PA (h) = LA (h) −D7F28h E SE IF (FFF28h ≦ LA (h) ≦ FFF2Fh) PA (h) = LA (h) −CFF30h ELSE IF (FFF30h ≦ LA (h) ≦ FFF37h) PA (h) = LA (h) −C7F38h ELSE IF (FFF38h) ≦ LA (h) ≦ FFF3Fh) PA (h) = LA (h) −BFF40h ELSE IF (FFF40h ≦ LA (h) ≦ FFF47h) PA (h) = LA (h) −B7F48h ELSE IF (FFF48h ≦ LA (h) ) ≦ FFF4Fh) PA (h) = LA (h) −AFF50h ELSE IF (FFF50h ≦ LA (h) ≦ FFF57h) PA (h) = LA (h) −A7F58h ELSE IF (FFF58h ≦ LA (h) ≦ FFF5Fh) PA (h) = LA (h) -9FF60h ELSE IF (FFF60 ≦ LA (h) ≦ FFF67h) PA (h) = LA (h) −97F68h ELSE IF (FFF68h ≦ LA (h) ≦ FFF6Fh) PA (h) = LA (h) −8FF70h ELSE IF (FFF70h ≦ LA (h) ) ≦ FFF77h) PA (h) = LA (h) −87F78h ELSE IF (FFF78h ≦ LA (h) ≦ FFF7Fh) PA (h) = LA (h) −7FF80h ELSE IF (FFF80h ≦ LA (h) ≦ FFF87h) PA (h) = LA (h) −77F88h ELSE IF (FFF88h ≦ LA (h) ≦ FFF8Fh) PA (h) = LA (h) −6FF90h ELSE IF (FFF90h ≦ LA (h) ≦ FFF97h) PA (h) = LA (h) -67F98h ELSE IF (FFF98h ≦ LA (h) ≦ FFF9 Fh) PA (h) = LA (h) -5FFA0h ELSE IF (FFFA0h ≦ LA (h) ≦ FFFA7h) PA (h) = LA (h) −57FA8h ELSE IF (FFFA8h ≦ LA (h) ≦ FFFAFh) PA ( h) = LA (h) −4FFB0h ELSE IF (FFFB0h ≦ LA (h) ≦ FFFB7h) PA (h) = LA (h) −47FB8h ELSE IF (FFFB8h ≦ LA (h) ≦ FFFFBFh) PA (h) = LA (H) -3FFC0h ELSE IF (FFFC0h ≦ LA (h) ≦ FFFC7h) PA (h) = LA (h) −37FC8h ELSE IF (FFFC8h ≦ LA (h) ≦ FFFCFh) PA (h) = LA (h) − 2FFD0h ELSE IF (FFFD0h ≦ LA (h) ≦ FFFD7h) PA (h) = LA (H) -27FD8h ELSE IF (FFFD8h ≦ LA (h) ≦ FFFDFh) PA (h) = LA (h) −1FFE0h ELSE IF (FFFE0h ≦ LA (h) ≦ FFFE7h) PA (h) = LA (h) − 17FE8h ELSE IF (FFFE8h ≦ LA (h) ≦ FFFFh) PA (h) = LA (h) −FFF0h ELSE IF (FFFF0h ≦ LA (h) ≦ FFFF7h) PA (h) = LA (h) −7FF8h ELSE IF ( FFFF8h ≦ LA (h) ≦ FFFFFh) PA (h) = LA (h)

Next, the address translation device 18 of FIG. 2 is configured by wired logic using the above-described address translation formula, and interfaces with the processor 10 together with the control device 14 of the flash memory 12. In this manner, similarly to the above-described embodiment, management and control of rewriting in the header area and conversion to an address map that makes blocks in the program / data area continuous can be performed.

[0034]

Other Embodiments There are many embodiments of the present invention, and various modifications can be made based on the above disclosure. For example, the following is also included. (1) In the first and second embodiments, the address translation device is realized by hardware logic.
And the address conversion from the logical address to the physical address may be performed by the table reference method. That is, the logical address is supplied to the address side of the ROM, and the physical address is output from the data side of the ROM.
Address control is performed while the chip enable and output enable of the ROM are kept asserted. In this ROM, a table obtained by expanding the address conversion formula as shown in the above embodiment may be stored.

(2) In the above embodiment, the present invention is applied to a flash memory. However, another similar memory has the same write / read function as the flash memory, and has a pre-write block erase characteristic. If you have a memory that has
It is equally applicable. (3) The above embodiment is directed to a case of operation in units of bytes or words (16 bits or 32 bits). However, the present invention can be similarly applied to other data units.

[0036]

As described above, according to the present invention,
The following effects are obtained. (1) Since address conversion is performed so that the corresponding header area and program / data area are in the same block of the memory, the number of times of rewriting of the block can be reduced and high-speed access can be performed. In addition, a memory for a header area is not required, and cost can be reduced. (2) By the address conversion, the blocks in the program / data area become continuous when viewed from the processor side, thereby reducing waste of the memory area, and without loading the execution program into the main storage device. The program can be executed on the auxiliary storage device.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a system using the present invention.

FIG. 2 is a block diagram illustrating a main part of one embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a memory mapping method for performing address conversion from a logical address to a physical address.

FIG. 4 is a diagram showing a memory mapping of physical addresses in a general-purpose flash memory having a block erasing function, and a relationship between a header area and a program / data area.

FIG. 5 is a diagram showing a relationship between a physical address of a flash memory and a logical address of a processor.

FIG. 6 is a diagram illustrating a memory map of a flash memory according to the first embodiment.

FIG. 7 is a diagram showing a memory map of a detailed structure in a block n of the flash memory according to the first embodiment.

FIG. 8 is a diagram illustrating a memory map of a flash memory according to a second embodiment.

FIG. 9 is a diagram showing a memory map of a detailed structure in a block n of a flash memory according to a second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Processor 12 ... Flash memory 14 ... Flash memory control device 16 ... RAM 18 ... Address conversion device

Claims (11)

[Claims] 1. A flash memory for erasing storage contents in units of blocks, wherein a first area for storing management information of its own block and a second area for storing main information are provided for each block. A flash-type memory provided in a flash memory. 2. A storage device comprising the flash memory according to claim 1, wherein an address for performing conversion between a physical address and a logical address such that a first area of an adjacent block is a continuous logical address. A storage device comprising conversion means. 3. A storage device comprising the flash type memory according to claim 1, wherein an address for performing conversion between a physical address and a logical address such that a second area of an adjacent block is a continuous logical address. 3. The apparatus according to claim 2, further comprising a conversion unit.
A storage device as described. 4. The storage device according to claim 3, wherein said address conversion means is constituted by wired logic. 5. The storage device according to claim 3, wherein said address translation means is constituted by a ROM storing a translation table. 6. The storage device according to claim 2, wherein the management information includes a number of times of writing of the block and a time at which the block is erased. 7. When erasing a block, if the number of times of writing is the same, there is provided control means for preferentially selecting a block having a longer erasing time.
A storage device as described. 8. A computer system provided with the storage device according to claim 3, further comprising a processor that executes a program stored in the second area on the flash memory. Computer system. 9. A flash memory management method for erasing storage contents in block units, comprising: a first area for storing management information of its own block; and a second area for storing main information. A flash type memory management method characterized by being provided for each block. 10. The flash memory management method according to claim 9, wherein the conversion between the physical address and the logical address is performed so that the first area of the adjacent block has a continuous logical address. 11. The flash memory management method according to claim 10, wherein the conversion between the physical address and the logical address is performed so that the second area of the adjacent block has a continuous logical address.