JPH1195875A - Reset method for cpu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the reset method of a CPU capable of resetting the CPU by simultaneously depressing a power supply switch and at least one more switch for more than a prescribed time. SOLUTION: In this reset method for the time when a CPU runs away and falls into a hung-up state, switch simultaneous depression time detection circuits OR and TE are provided, and when it has been detected that the power supply switch S1 and at least one more switch S2 are simultaneously pressurized for more than the prescribed time in the switch simultaneous depression time detection circuits OR and TE, reset signals/RST are outputted from the switch simultaneous depression time detection circuits OR and TE to the reset input terminal of the CPU and the CPU is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset method when a CPU goes out of control and falls into a hang-up state, and more particularly to a technique effective when applied to an electronic device such as a digital still camera having a small number of operation switches. About.

[0002]

2. Description of the Related Art In recent years, in portable devices such as digital still cameras, information devices, and the like, products that require advanced processing are increasing. ) Has also been improved in performance.

On the other hand, the program processing of the CPU is complicated, and the time required for commercialization of the product is short, so that there is a possibility that a "bug" such as a hang-up may occur. In many cases, it will be released. Therefore, in the above-mentioned products, C
It is common to provide a CPU reset means for resetting the PU.

A dedicated reset switch is provided as one of the CPU reset means described above, and when an abnormal state such as a hang-up occurs, the user presses the dedicated reset switch to reset the CPU. There is a known way to do this.

As another means, there is known a method of resetting the CPU by simultaneously pressing a plurality of switches other than the power switch.

[0006]

SUMMARY OF THE INVENTION However, CPU
In the method of providing a dedicated switch as a resetting means, providing a dedicated switch inevitably causes an increase in the cost of the product, and also requires a device that damages the external design or cannot be easily pressed. There was a problem that becomes.

According to the method of simultaneously pressing a plurality of switches as the CPU reset means, the above-mentioned problem can be solved. However, for example, two keys are simultaneously pressed in key input of a word processor or the like. Since this is generally performed, resetting the CPU by simultaneously pressing two switches easily causes an erroneous operation.

Therefore, the method of simultaneously pressing a plurality of switches as the CPU reset means has a problem that its application is difficult unless the product has three or more operation switches.

Further, the determination as to whether or not a reset is required is left to the discretion of the user. There is also a problem in that a forced reset occurs due to a user's erroneous judgment, and data being processed is lost. there were.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art.
Another object of the present invention is to provide a technique for resetting a CPU by simultaneously pressing a power switch and at least another switch for a predetermined time or more.

Another object of the present invention is to provide a method of resetting a CPU, which includes the steps of:
It is an object of the present invention to provide a technique capable of preventing data being processed from being destroyed even when at least another switch is pressed simultaneously. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. In a reset method when the CPU goes out of control and reaches a hang-up state, a switch simultaneous pressing time detecting circuit is provided, and the power switch and at least another switch are connected for at least a predetermined time by the switch simultaneous pressing time detecting circuit. When it is detected that the switches are simultaneously pressed, a reset signal is output from the switch simultaneous pressing time detection circuit to a reset input terminal of the CPU,
U is reset.

When the power switch is pressed, the CPU saves the data being processed, and then performs a standby state transition process of turning off the power of the electronic device on which the CPU is mounted. The switch simultaneous pressing time detection circuit detects that the power switch and at least another switch have been pressed simultaneously for a time longer than the time required for the standby state shifting process performed by the switch.
It is characterized in that the PU is reset.

The switch simultaneous pressing time detecting circuit is provided with a logic circuit whose output level is inverted while the power switch and at least another switch are simultaneously pressed, and an output of the logic circuit. And an integrating circuit.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

FIG. 1 shows a digital still camera C to which the CPU reset method according to the first embodiment of the present invention is applied.
FIG. 3 is a block diagram illustrating a schematic configuration of a PU unit.

In FIG. 1, a CPU 1 controls a camera system and the like, and realizes a calendar function using a built-in clock mechanism. Therefore, the CPU 1 is supplied with power from the backup battery (B1) via the diode (D1), and operates even during standby. CP
U2 manages data such as captured images and a personal computer interface, and performs data communication with the CPU 1 to exchange various control information.

The power source is a main battery (B) such as an alkaline battery.
2) is generated by a DC / DC converter (D / D), stabilized, and supplied to each circuit. In this case, C
PU1 is supplied with power from a DC / DC converter (D / D) via a diode (D2). Therefore, the CPU 1 operates from the main power supply (B2) during the operation of the camera.
During standby, it continues to operate on the backup battery (B1).

When the power switch (S1) is pressed during standby, a power ON / OFF signal input terminal (P
A power ON / OFF signal (/ PSW) of "Low level" (hereinafter, referred to as L level) is input to 1) (note that the symbol / indicates that the signal attached thereto is a row enable signal). Means.).

The CPU 1 turns on / off the power of "L level".
When the FF signal (/ PSW) is input, a control signal (CTL) of “High level” (hereinafter, referred to as H level) is supplied from a power control signal output terminal (P4) to a DC / DC converter (D / D). Output to As a result, the DC / DC converter (D / D) is turned on, and the camera is turned on. Here, when the shutter switch (S2) is pressed, the shutter ON / OFF signal input terminal (P2)
“Low level” shutter ON / OFF signal (/ SS
W) is input, and shooting is performed.

When the power switch (S1) is pressed during the operation of the camera, the CPU 1 causes the CPU 2 to
Transmits a command for executing a predetermined process such as storing data being processed in a flash memory (not shown),
After a predetermined process such as saving the data being processed in the flash memory by the CPU 2 is executed, an “L level” control signal (CTL) is output from the power control signal output terminal (P4) to the D terminal.
The output is output to the C / DC converter (D / D), the DC / DC converter (D / D) is stopped, and the camera is set in a standby state.

If the CPU 2 runs away for some reason during the operation of the camera, the CPU 1 executes the CPU
2 is detected and the DC / DC converter (D / D) is stopped to recover the runaway state of the CPU 2 and to operate normally from the next time. In addition, the user can determine that there is an abnormality and remove the main battery (B2), thereby recovering the runaway state of the CPU 2.

In general, the replacement of the backup power supply (B1) causes an increase in cost. Therefore, the backup power supply (B1) is usually fixed by soldering if the holding time is sufficient. is there. Therefore, CPU1
When the power supply goes out of control, the backup power supply (B1) cannot be removed. Therefore, there is no recovery means for recovering the runaway state of the CPU 1, and there is no other method except to reset the CPU 1.

Therefore, in the reset method of this embodiment, the power switch (S1) and the shutter switch (S2)
Are simultaneously pressed for a predetermined time to reset the CPU 1.

Therefore, in the digital still camera shown in FIG. 1, an OR circuit (OR) to which a power ON / OFF signal (/ PSW) and a shutter ON / OFF signal (/ SSW) are input, and an OR circuit (OR) And an integrating circuit (TE) to which the output of the OR) is input. The OR circuit (O
R) and the integration circuit (TE) constitute a switch simultaneous pressing time detection circuit of the present invention, and this integration circuit (TE) is composed of a resistor (R3) and a capacitor (C1).

The OR circuit (OR) and the integration circuit (TE)
Will be described with reference to the timing chart of FIG.

At time t0, the power switch (S1)
Is pressed, the power ON / OFF signal (/ PSW) becomes "L level". At time t1, the shutter switch (S1) is pressed while the power switch (S1) is pressed.
2), the shutter ON / OFF signal (/ S
SW) also becomes “L level”, and the output of the OR circuit (OR) becomes “L level”.

As it is, both switches (S1, S2)
When the capacitor (C1) is continuously pressed, (R3 × C
Since the discharge is performed with the time constant of 1), the output of the integration circuit (TE) (the potential at the connection point between the resistor (R3) and the capacitor (C1)) decreases exponentially.

At time t2, when the output of the integration circuit (TE) decreases to the threshold voltage (Vth) of the reset input terminal (P3) of the CPU 1, a reset signal (/ RST) is input to the CPU 1, and the CPU 1 Reset. That is, the CPU 1 is reset after a lapse of ta time since both switches (S1, S2) are simultaneously pressed. CP
After U1 is reset, it will start again from the beginning.

Incidentally, whether or not the CPU 1 is running out of control is left to the discretion of the user.
It is assumed that the reset operation is performed and the data being processed is destroyed even though the CPU 1 is operating normally.

However, this can be easily prevented by optimizing the time constant of the integration circuit (TE). This will be described with reference to the timing chart of FIG.

During normal operation, when the power switch (S1) is pressed at time t'0, the power ON / OFF signal (/ PSW) becomes "L level". In this case, C
Since the PU1 is operating normally, the PU1 performs a standby state transition process such as saving data being processed in order to transition to a standby state assuming that the operation is a power-off operation.

Next, when the shutter switch (S2) is pressed at time t'1 while the power switch (S1) is pressed, a shutter ON / OFF signal (/ SSW) is generated.
Also becomes “L level”, and the output of the integration circuit (TE) decreases exponentially. Then, at time t′2, when the output of the integration circuit (TE) decreases to the threshold voltage (Vth) of the reset input terminal (P3) of the CPU 1, C
A reset signal (/ RST) is input to PU1 and the CPU
1 is reset.

However, before the CPU 1 is reset, the above-mentioned standby state transition processing ends, and at time t′3
, The control signal (CTL) of “L level” is supplied from the power control signal output terminal (P4) to the DC / DC converter (D
/ D), the DC / DC converter (D / D) is stopped, and the camera is in a standby state.

That is, the time from the time t'0 when the power switch (S1) is pressed to the time t'3 when the standby state is set is tb, and both switches (S1 and S2) are simultaneously pressed and the OR circuit ( OR), when the time from the time t′1 when the output of “OR” becomes “L level” until the CPU 1 is reset is set to ta, the times ta and tb are set so as to satisfy the following equation (1). As a result, the CPU 1 is not forcibly reset during operation, and the data being processed is reliably stored.

[0036]

[Mathematical formula-see original document] ta> tb (1) In this case, in an actual product, the time tb is about 1 second. , Time ta may be about 2 seconds, and this time can be sufficiently handled by the integration circuit (TE).

Although the embodiment using the OR circuit (OR) has been described with reference to FIG. 1, the present invention is not limited to this, and the CPU 1 outputs the "H level" power ON / OFF signal. In the case of a CPU that operates with the (PSW) and the “H level” shutter ON / OFF signal (SSW), a NAND circuit (NAND) shown in FIG. 4 may be used instead of the OR circuit (OR).

The NAND circuit (NAND) shown in FIG.
Power ON / OFF signal (PSW) and shutter ON / O
Since the FF signal (SSW) is input, when both switches (S1 and S2) are simultaneously pressed, the output of the NAND circuit (NAND) becomes "L level".
Also in this case, the output of the NAND circuit (NAND) is input to the integration circuit (TE), and both switches (S1, S2)
Are simultaneously pressed for a predetermined time or more, the CPU 1
Will be reset.

In the above-described embodiment, the switch pressed simultaneously with the power switch (S1) is not limited to the shutter switch (S2), and it goes without saying that a switch other than the shutter switch (S2) may be used. . Also, as the integration circuit (TE), an integration circuit other than the RC integration circuit can be used.

Further, in the above embodiment, the case where the present invention is applied to a digital still camera having two CPUs has been described. However, the present invention is not limited to this. The present invention is also applicable to a digital still camera including only a CPU, and the present invention is not limited to a digital still camera, and is generally applicable to electronic devices including a CPU.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0042]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, a simple circuit configuration detects that the power switch and at least another switch are simultaneously pressed for a predetermined time or more, and resets the CPU. The rise can be minimized. (2) According to the present invention, it is possible to prevent the data being processed from being destroyed even when the power switch and at least another switch are simultaneously pressed by mistake during normal operation. Becomes

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a CPU unit of a digital still camera to which a CPU reset method according to a first embodiment of the present invention is applied;

FIG. 2 shows an OR circuit (OR) and an integration circuit (T) shown in FIG.
It is a figure showing the timing chart of E).

FIG. 3 is a diagram showing an example of an appropriate time constant of an integration circuit (TE) for preventing a reset operation from being performed even when the CPU 1 is operating normally and data being processed is destroyed. FIG. 4 is a diagram showing a timing chart of an integration circuit (TE) for explaining.

FIG. 4 is a diagram showing a modification of the switch simultaneous pressing time detection circuit of the present invention.

[Explanation of symbols]

CPU1, CPU21: central processing unit, B1: backup battery, B2: main battery, D1, D2: diode, R
1, R2, R3: resistor, C1: capacitor, OR: OR circuit, NAND: NAND circuit, S1: power switch, S
2: shutter switch, D / D: DC / DC converter, TE: integrating circuit.

Claims (4)

[Claims] 1. A reset method when a CPU goes out of control and reaches a hang-up state, further comprising a switch simultaneous pressing time detecting circuit, wherein the switch simultaneous pressing time detecting circuit includes the power switch and at least another switch. A reset signal output from the switch simultaneous pressing time detecting circuit to a reset input terminal of the CPU, thereby resetting the CPU. . 2. When the power switch is pressed, the CPU saves the data being processed, and then performs a standby state transition process of turning off the power of the electronic device on which the CPU is mounted. The switch simultaneous pressing time detection circuit detects that the power switch and at least another switch are pressed simultaneously for a time longer than the time required for the standby state transition process performed by the CPU, and resets the CPU. 2. The method according to claim 1, wherein the resetting is performed. 3. The switch simultaneous pressing time detecting circuit,
The power supply switch, a logic circuit whose output level is inverted while at least one other switch is pressed simultaneously, and an integration circuit to which an output of the logic circuit is input. 3. The method for resetting a CPU according to claim 1 or 2. 4. The electronic device on which the CPU is mounted is a digital still camera, and the at least one other switch is a shutter switch. The reset method of the CPU described in the section.