JPH1189241A - Inverter equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of types of components and the number of components and thereby simplify an assembling procedure by using the same main substrate having a circuit for controlling an inverter circuit and the one for detecting defects in the inverter circuit and the same sub-substrate having a defect detecting circuit for the inverter circuit connected to the main substrate by a connector, regardless of the circuit types of the inverter. SOLUTION: A three-phase AC inverter 1 is composed of a three-level GTO inverter 1 which have serially connected GTOs, four for each phase, and outputs three levels of voltages. A main substrate 2 is provided with a defect detecting circuit 21, a defect latch circuit 22, an OR circuit 23, a stop circuit 24, and a CPU 25. On the other hand, a sub-substrate 3 is provided with a defect detecting circuit 31, a defect latch circuit 32, an OR circuit 33, and a three-level GTO PWM circuit 34 and is connected to the main substrate 2 by a connector and is also connected to the inverter circuit. Even if other type of inverter circuit 1 is used, the same circuits are mounted on the main substrate 2 and the structure of only the sub-substrate 3 is changed. By this method, the same main substrate can be used regardless of the types of the inverter circuit and a mass production can be realized easily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter circuit and its control, and to an inverter device having a main board and a sub-board for detecting a failure.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional two-level IGBT (I
FIG. 2 is a block diagram showing a configuration of a multiplexed inverter device, wherein 1 is a two-level IGBT multiplexed inverter circuit, and 2 is a two-level IGBT.
A main board 3 for controlling the multiple inverter circuit 1 and detecting a failure is also a sub-board. 2 level I
The GBT multiplex inverter circuit 1 is a three-phase bridge IGBT inverter circuit 1 which is a converter for converting DC into three-phase AC.
The two reactors 1 and 12 are connected by a balance reactor 13.

The main board 2 has a plurality of failure detection circuits 21,
A plurality of failure latch circuits 22, an OR circuit 23, a stop circuit 24 for stopping the operation of the inverter when a failure occurs, and a CP
U25, and the sub-board 3 includes a plurality of failure detection circuits 3
1 and 2 level IGBT multiplexed PWM circuit (hereinafter simply referred to as PWM
An M (pulse width modulation) circuit 34 is provided. The main board 2 and the sub-board 3 are connected to the two-level IGBT multiplex inverter circuit 1 and are connected to each other via the connector 4. The connector 4 includes a failure detection circuit 31 of the sub board 3 and a failure latch circuit 22 of the main board 2.
And between the PWM circuit 34 of the sub-board 3 and the CPU 25 of the main board 2.

Each failure detection circuit 21 in the main board 2
Are respectively connected to the corresponding fault latch circuits 22. Each fault latch circuit 22 includes a fault latch circuit 22 connected to the fault detection circuit 31 of the sub-substrate 3 and is connected to each other.
The input terminal of the R circuit 23 is connected to the CPU 25 via the bus 5. The output of the OR circuit 23 is applied to a stop circuit 24 for stopping the operation of the two-level IGBT multiplex inverter circuit 1, and the stop circuit 24
Is supplied to the CPU 25.

On the other hand, each failure detection circuit 3 on the sub-board 3
Numerals 1 are connected to the corresponding failure latch circuits 22 on the main board 2 via the connector 4, respectively.
4 is also connected to the CPU 25 via the connector 4 and the bus 5.

Next, these operations will be described. In accordance with the signal from the PWM circuit 34, the CPU 25 of the main board 2
The level IGBT multiplex inverter circuit 1 is controlled so as to perform a predetermined conversion operation. If a fault occurs in the two-level IGBT multiplex inverter circuit 1, any one of the fault detection circuits 21 of the main board 2 responsible for the fault occurrence portion Or a failure is detected by one of the failure detection circuits 31 of the sub-board 3. When the failure detection circuit 21 of the main board 2 detects a failure, the detection signal is latched by the corresponding failure latch circuit 22, and when the failure detection circuit 31 of the sub-board 3 detects the failure, the detection signal is passed through the connector 4. Fault latch circuit 2 corresponding to each in main board 2
2 latched. The signal latched by each failure latch circuit 22 is directly input to the CPU 25 via the bus 5 and is also input to the OR circuit 23. The OR circuit 23 calculates the logical sum of the latch signals from the faulty latch circuit 22 and outputs a predetermined signal to the stop circuit 24. The stop circuit 24 outputs a signal for stopping the operation of the inverter or another signal to the CPU 25 based on a signal from the OR circuit 23.
The CPU 25 determines what kind of failure has occurred by software based on the signal from the stop circuit 24 and the latch signal from each failure latch circuit 22, and determines the failure content.
Necessary control is performed according to the type of failure that has occurred.

FIG. 5 is a block diagram showing the configuration of a conventional three-level IGBT inverter device. In FIG.
The level IGBT inverter circuit, 2 is a main board, and 3 is a sub board. The interconnection structure is the same as that of the two-level IGBT multiplex inverter shown in FIG.

That is, the main board 2 includes a plurality of failure detection circuits 21, a plurality of failure latch circuits 22, an OR circuit 23, a stop circuit 24, and a CPU 25. The sub-board 3 includes a plurality of failure detection circuits 31 and a three-level IGBTPWM. The main board 2 and the sub-board 3 are connected to the three-level IGBT inverter circuit 1, respectively, are connected to each other via the connector 4, and are connected to the sub-board 3. The connector 4 connects the failure detection circuit 31 to the failure latch circuit 22 of the main board 2, and the bus 5 connects the PWM circuit 34 of the sub board 3 to the CPU 25 of the main board 2.

A three-level IGBT inverter circuit 1 is a three-phase bridge IGB which is a converter for converting DC to three-phase AC.
It is configured by connecting two T inverter circuits 11 and 12 in parallel. Each failure detection circuit 2 in the main board 2
1 are respectively connected to the corresponding failure latch circuits 22, and each failure latch circuit 22 is connected to the failure detection circuit 3 of the sub-board 3.
1 including the fault latch circuit 22 connected to
The input terminal of the R circuit 23 is connected to the CPU 25 via the bus 5. The output terminal of the OR circuit 23 is connected to the input terminal of the stop circuit 24,
Are connected to the CPU 25.

On the other hand, each failure detection circuit 3 on the sub-board 3
Numerals 1 are connected to the corresponding failure latch circuits 22 on the main board 2 via the connector 4, respectively.
Reference numeral 4 also denotes a CPU 25 via a bus 5 via a connector 4.
It is connected to the.

Next, these operations will be described. In accordance with the signal from the PWM circuit 34 in the CPU 25 of the main board 2,
The level IGBT inverter circuit 1 is controlled to perform a predetermined conversion operation. If a failure occurs in the three-level IGBT inverter circuit 1, any one of the failure detection circuits 21 on the main board 2 responsible for the failure occurrence part, or A failure is detected by one of the failure detection circuits 31 of the sub-board 3. When the failure detection circuit 21 of the main board 2 detects a failure, the detection signal is sent to the corresponding failure latch circuit 22
When the failure detection circuit 31 of the sub board 3 detects a failure, the detection signal is latched by the corresponding failure latch circuit 22 on the main board 2 via the connector 4. The signal latched by each failure latch circuit 22 is directly input to the CPU 25 via the bus 5 and is also input to the OR circuit 23. The OR circuit 23 is the fault latch circuit 2
And outputs a predetermined signal to the stop circuit 24. The stop circuit 24 outputs a signal for stopping the operation of the inverter or another signal to the CPU 25 based on a signal from the OR circuit 23. CPU25
Determines the content of the fault by software based on the signal from the stop circuit 24 and the latch signal from each fault latch circuit 22, and performs necessary control according to the content of the generated fault. Do.

[0012]

FIG. 4 or FIG.
In the conventional inverter device shown in FIG. 1, a two-level IGBT multiplex inverter circuit 1 or 3 which is an inverter circuit
When the structure and the type of the level IGBT inverter circuit 1 are different, it is necessary to prepare the main board 2 and the sub-board 3 corresponding to each, and there is a problem that a variety of parts are required and an increase in manufacturing cost is unavoidable. .

The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to apply the same main board even when the structure and type of an inverter circuit in an inverter device are different. An object of the present invention is to provide an inverter device which is simplified and whose cost is reduced by mass production.

[0014]

An inverter device according to a first aspect of the present invention includes an inverter circuit, a main board including a circuit for controlling the inverter circuit and detecting a failure, and is connected to the main board by a connector. And a circuit for detecting a failure of the inverter circuit, wherein the main board is shared irrespective of the type and structure of the inverter circuit. According to the first aspect of the present invention, the type and the number of parts are reduced by the common use of the main board, and the assembly procedure is simplified.

In the inverter device according to a second aspect of the present invention, a plurality of failure detection circuits and at least one more failure detection circuit are provided on the main board, and the detection signals of the respective failure detection circuits are latched. A fault latch circuit, an OR circuit to which an output of each fault latch circuit is input, a stop circuit for stopping the operation of the inverter circuit based on an output of the OR circuit, an output of the stop circuit, and each fault latch Determining means for determining the failure content based on the output of the circuit. In the second invention, by providing the main board with the failure detection circuit, the failure latch circuit, the OR circuit, the stop circuit, and the CPU, the main board having the minimum necessary functions required for failure detection can be obtained. Common use becomes easy, and the presence of useless circuits can be reduced.

In the inverter device according to a third aspect of the present invention, the sub-board is provided for each of the plurality of failure detection circuits and each of the failure detection circuits, latches the detection signal of each of the failure detection circuits, and outputs the latched signal. Latch circuit that supplies the output to the determination means of the main board, and O which receives the output of each of the failure latch circuits as inputs and provides the output to the failure latch circuit of the main board.
And an R circuit. In the third invention, a failure detection circuit, a failure latch circuit, and an OR
Since the circuit is provided, the layout on the sub-board can be easily unified, which can contribute to the common use of the main board.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a configuration in which the present invention is applied to the conventional two-level IGBT multiplex inverter device shown in FIG. 4, wherein 1 is a two-level IGBT multiplex inverter circuit, and 2 is a two-level IGBT multiplex inverter circuit 1. Main board for control,
3 is a sub-substrate.

A two-level IGBT multiplex inverter circuit 1 is a three-phase bridge IG which is a converter for converting DC to three-phase AC.
Two BT inverter circuits 11 and 12 are multiplex-connected by a balance reactor 13.

The main board 2 includes a plurality of (three in the drawing) failure detection circuits 21, a plurality of (four in the drawing) failure latch circuits 22, one or more OR circuits more than the number of the failure detection circuits 21 23, a stop circuit 24 for stopping the operation of the inverter when a failure occurs, and one or more CPUs 25. The sub-board 3 includes a plurality of (two in the drawing) failure detection circuits 31, a plurality of (two in the drawing) failure latch circuits 32 equal to the number of the failure detection circuits 31, and one or more ORs.
A circuit 33 and a two-level IGBT multiplexed PWM circuit (hereinafter simply referred to as a PWM circuit) 34 are provided. Main board 2
And the sub-board 3 are connected to the two-level IGBT multiplex inverter circuit 1 and are connected to each other via the connector 4, and the OR circuit 33 of the sub-board 3 and the failure latch circuit 22 of the main board 2 are connected. A bus 5 is connected between the failure latch circuit 32 and the PWM circuit 34 of the sub board 3 and the CPU 25 of the main board 2 via the connector 4.
Connected by

Each failure detection circuit 21 in the main board 2
Are connected to the corresponding failure latch circuits 22, respectively. The output terminal of each failure latch circuit 22 is connected to the input terminal of the OR circuit 23, and is connected to the CPU 25 via the bus 5 together with the failure latch circuit 32 of the sub-board 3. It is connected. OR
An output terminal of the circuit 23 is connected to an input terminal of the stop circuit 24,
The output terminal of the stop circuit 24 is connected to the CPU 25.

On the other hand, each failure detection circuit 3 on the sub-board 3
1 are connected to the corresponding failure latch circuits 32 on the same sub-substrate 3, each failure latch circuit 32 is connected to the OR circuit 33 on the same sub-substrate 3, and furthermore, the PWM circuit 3
4 is connected to the CPU 25 by the bus 5 via the connector 4. The output terminal of the OR circuit 33 is connected to the failure latch circuit 22 on the main board 2 via the connector 4.

Next, these operations will be described. In accordance with the signal from the PWM circuit 34, the CPU 25 of the main board 2
The level IGBT multiplex inverter circuit 1 is controlled so as to perform a predetermined conversion operation. If a fault occurs in the two-level IGBT multiplex inverter circuit 1, any one of the fault detection circuits 21 of the main board 2 responsible for the fault occurrence portion Or a failure is detected by one of the failure detection circuits 31 of the sub-board 3. When the failure detection circuit 21 of the main board 2 detects a failure, the detection signal is latched by a corresponding failure latch circuit 22, and when the failure detection circuit 31 of the sub-board 3 detects a failure, the detection signal is converted to the corresponding failure. The data is latched by the latch circuit 32. The signal latched by each failure latch circuit 22 of the main board 2 is directly input to the CPU 25 via the bus 5 and also input to the OR circuit 23.

The signal latched by each failure latch circuit 32 of the sub-board 3 is input to the CPU 25 via the bus 5 via the connector 4 and also to the OR circuit 33. The output of the OR circuit 33 is input to the failure latch circuit 22 of the main board 2 via the connector 4. OR circuit 23
Calculates the logical sum of the latch signals from the faulty latch circuits 22 and outputs a predetermined signal to the stop circuit 24. Stop circuit 2
4 outputs a signal for stopping the operation of the inverter or another signal to the CPU 25 based on a signal from the OR circuit 23. The CPU 25 determines what kind of failure has occurred by software based on the signal from the stop circuit 24 and the latch signal from each of the failure latch circuits 22 and 32, and performs necessary control according to the content of the failure that has occurred. I do.

FIG. 2 shows the conventional three-level IGBT shown in FIG.
1 is a block diagram showing a configuration in a case where the present invention is applied to an inverter device. In the figure, reference numeral 1 denotes a three-level IGBT inverter circuit, 2 denotes a main board for controlling and detecting a failure of the three-level IGBT inverter circuit 1, and 3 denotes the same. Sub substrate. The structure of three-level IGBT inverter circuit 1 is the same as that shown in FIG. 5, and the structure of main substrate 2 is the same as that shown in FIG. As a result, the other fault detection circuits and fault latch circuits have been moved to the sub-board 3. The connection structure is the same as that of the two-level IGBT multiplex inverter device shown in FIG.

That is, the three-level IGBT inverter circuit 1
Is a converter for converting into three-phase alternating current, in which four IGBTs of each phase are connected in series and can output three voltage levels. The main board 2 includes a plurality of (three in the drawing) failure detection circuits 21, a plurality of failure latch circuits 22, one or more OR circuits 2 one more than the number of the failure detection circuits 21
3, a stop circuit 24 and one or more CPUs 25 are provided. The sub-board 3 includes a plurality of failure detection circuits 31, the same number of failure latch circuits 32, one or a plurality of OR circuits 3
A three- and three-level IGBTP PWM circuit (hereinafter simply referred to as a PWM circuit) 34 is provided. The main board 2 and the sub-board 3 are respectively connected to the three-level IGBT inverter circuit 1 and are mutually connected via the connector 4.
Between the OR circuit 33 of the sub-board 3 and the failure latch circuit 22 of the main board 2 and the failure latch circuit 3 of the sub-board 3
2 and the PWM circuit 34 and the CPU 25 of the main board 2 are connected to each other.

Each failure detection circuit 21 in the main board 2
Are respectively connected to the corresponding fault latch circuits 22, and each fault latch circuit 22 is connected to the fault latch circuit 32 of the sub-substrate 3.
Also, it is connected to the CPU 25 via the bus 5. Each failure latch circuit 22 of the main board 2 is provided with an OR circuit 23
Is connected to the input terminal of OR circuit 2 of main board 2
The output terminal 3 is connected to the input terminal of the stop circuit 24, and the output terminal of the stop circuit 24 is connected to the CPU 25.

On the other hand, each failure detection circuit 3 on the sub-board 3
1 is connected to the corresponding failure latch circuit 32, and each failure latch circuit 32 is connected to the CPU 25 by the bus 5 via the connector 4 together with the PWM circuit 34.
Each of the failure latch circuits 32 on the sub-board 3 is an OR circuit 33.
, And the output terminal of the OR circuit 33 is connected to the failure latch circuit 22 of the main board 2 via the connector 4.

Next, these operations will be described. In accordance with the signal from the PWM circuit 34 in the CPU 25 of the main board 2,
The level IGBT inverter circuit 1 is controlled to perform a predetermined conversion operation. If a failure occurs in the three-level IGBT inverter circuit 1, any one of the failure detection circuits 21 on the main board 2 responsible for the failure occurrence part, or A failure is detected by one of the failure detection circuits 31 of the sub-board 3. When the failure detection circuit 21 of the main board 2 detects a failure, the detection signal is sent to the corresponding failure latch circuit 22
When the failure detection circuit 31 of the sub-board 3 detects a failure, the detection signal is latched by the corresponding failure latch circuit 32.

The signal latched by each of the failure latch circuits 22 and 32 is sent directly to the CPU 5 by the bus 5 through the connector 4.
25, the latch signal of each fault latch circuit 22 of the main board 2 is input to the OR circuit 23, and the latch signal of each fault latch circuit 32 of the sub board 3 is ORed.
The output of the OR circuit 33 is input to the failure latch circuit 22 of the main board 2 via the connector 4. The OR circuit 23 of the main board 2 obtains the logical sum of the latch signals from the respective failure latch circuits 22 and outputs a predetermined signal to the stop circuit 24. The stop circuit 24 is an OR circuit 23
A signal for stopping the operation of the inverter or another signal is output to the CPU 25 based on the signal from the CPU 25. CPU
25 is a signal from the stop circuit 24 and each fault latch circuit 2
Based on the latch signals from 2 and 32, software determines what kind of failure has occurred and performs necessary control according to the details of the failure that has occurred.

FIG. 3 is a block diagram showing a configuration of a three-level GTO inverter device to which the present invention is applied. In FIG. 3, reference numeral 1 denotes a three-level GTO inverter circuit, 2 denotes a three-level GTO inverter circuit, A main board 3 for detection is also a sub-board. 3 level GTO
Except for the inverter circuit 1, the other structures on the main substrate 2 and the sub substrate 3 and the interconnection structure are the same as those of the two-level IGBT multiplex inverter device shown in FIG.

That is, the three-level GTO inverter circuit 1 is a converter for converting into three-phase alternating current, in which four GTOs of each phase are connected in series, and can output three voltage levels. The main board 2 includes a plurality of failure detection circuits 21, a plurality of failure latch circuits 22, one or more OR circuits 23, one or more OR circuits 23, a stop circuit 24, and one or more CPUs 25 than the number of the failure detection circuits 21. I have. Sub-substrate 3
Are a plurality of failure detection circuits 31, the same number of failure latch circuits 32, one or a plurality of OR circuits 33, and a three-level GTO
A PWM circuit (hereinafter simply referred to as a PWM circuit) 34 is provided. The main board 2 and the sub board 3 each have a three-level GT
O circuit 33 is connected to the O inverter circuit 1 and is connected to each other via the connector 4.
And the fault latch circuit 22 of the main board 2, and between the fault latch circuits 32 and the PWM circuit 34 of the sub board 3 and the CPU 25 of the main board 2, respectively.

Each failure detection circuit 21 in the main board 2
Are respectively connected to the corresponding fault latch circuits 22, and each fault latch circuit 22 is connected to the fault latch circuit 32 of the sub-substrate 3.
Also, it is connected to the CPU 25 via the bus 5. O
The output terminal of the R circuit 23 is connected to the input terminal of the stop circuit 24, and the output terminal of the stop circuit 24 is connected to the CPU 25.

On the other hand, each fault detection circuit 3 on the sub-board 3
1 are connected to the corresponding failure latch circuits 32, respectively. Each failure latch circuit 32 is connected to the OR circuit 33, and is also connected to the CPU 25 via the bus 5 together with the PWM circuit 34. The output terminal of the OR circuit 33 is connected to the failure latch circuit 22 of the main board 2 via the connector 4.

Next, these operations will be described. In accordance with the signal from the PWM circuit 34 in the CPU 25 of the main board 2,
The level GTO inverter circuit 1 is controlled to perform a predetermined conversion operation. When a failure occurs in the three-level GTO inverter circuit 1, any one of the failure detection circuits 21 or A failure is detected by one of the failure detection circuits 31 of the board 3. When the failure detection circuit 21 of the main board 2 detects a failure, the detection signal is latched by a corresponding failure latch circuit 22, and when the failure detection circuit 31 of the sub-board 3 detects a failure, the detection signal is converted to the corresponding failure. The data is latched by the latch circuit 32. The signals latched by the failure latch circuits 22 and 32 are directly input to the CPU 25 via the bus 5, and the latch signal of each failure latch circuit 22 of the main board 2 is input to the OR circuit 23 and the sub-board 3 Are input to the OR circuit 33. The OR circuit 33 takes the logical sum of the input latch signals, supplies the logical sum to the failure latch circuit 22 of the main board 2 via the connector 4 and latches the result. The OR circuit 23 obtains the logical sum of the latch signals from each of the faulty latch circuits 22 and outputs a predetermined signal to the stop circuit 24. The stop circuit 24 outputs a signal for stopping the operation of the inverter based on a signal from the OR circuit 23 or another signal to the CPU 2.
Output to 5 The CPU 25 determines what kind of failure has occurred by software based on the signal from the stop circuit 24 and the latch signal from each of the failure latch circuits 22 and 32, and performs necessary control according to the content of the failure that has occurred. I do.

As shown in FIGS. 1 to 3, even though the structure and the type of the inverter circuit are different, the main board 2 has exactly the same mounting circuit and the sub circuit board 3 only has a different structure. There is. With such a configuration, an IGBT multiplex inverter circuit having a different structure, an IG
Even if it is a BT inverter circuit or a GTO inverter circuit, the necessary components are left on the main substrate 2 and other components required for the structure are arranged on the sub substrate 3 so that the main substrate 2 can be used for various main inverter circuits. The present invention can be applied, the maintenance is good, and the apparatus can be configured at low cost.

[0036]

According to the first aspect of the present invention, even when the structure and the type of the inverter circuit are different, the mass production effect can be obtained by sharing the main board of the control system, and the cost can be reduced. According to the second aspect of the invention, by providing the main board with the fault detection circuit, the fault latch circuit, the OR circuit, the stop circuit, and the CPU, the balance with the circuit mounted on the sub-board is good, and the common use is further facilitated. In the third invention, a failure detection circuit, a failure latch circuit, and an OR
The provision of the circuit facilitates unification of the layout on the substrate and facilitates the common use of the main substrate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration in which the present invention is applied to the conventional two-level IGBT multiplex inverter shown in FIG.

FIG. 2 is a block diagram showing a configuration in which the present invention is applied to the conventional three-level IGBT inverter device shown in FIG.

FIG. 3 is a block diagram showing a configuration of a three-level GTO inverter device to which the present invention is applied.

FIG. 4 is a block diagram showing a configuration of a conventional two-level IGBT multiplex inverter device.

FIG. 5 is a block diagram showing a configuration of a conventional three-level IGBT inverter device.

[Explanation of symbols]

1 Inverter circuit, 2 main board, 3 sub board,
4 connector, 5 bus, 21 failure detection circuit, 22
Fault latch circuit.

Claims (3)

[Claims] An inverter circuit, a main board including a circuit for controlling the inverter circuit and detecting a failure, and a sub-circuit connected to the main board by a connector and including a circuit for detecting a failure of the inverter circuit. An inverter device, comprising: a substrate, wherein the main substrate is shared irrespective of the type of inverter circuit structure. 2. A main board, comprising: a plurality of failure detection circuits; at least one more failure detection circuit than the number of the failure detection circuits; a failure latch circuit for latching a detection signal of each failure detection circuit; OR to which the output of the latch circuit is input
A stop circuit for stopping the operation of the inverter circuit based on an output of the OR circuit; and a judging means for judging a failure content based on an output of the stop circuit and an output of each of the fault latch circuits. The inverter device according to claim 1, wherein: 3. A sub-board is provided corresponding to each of the plurality of fault detection circuits and each of the fault detection circuits. The sub-board latches a detection signal of each of the fault detection circuits and provides an output to a determination means of the main board. 2. The inverter device according to claim 1, further comprising: a fault latch circuit; and an OR circuit which receives an output of each of the fault latch circuits and supplies the output to the fault latch circuit on the main board.