JPH118862A - Two-dimentional-to-three-dimensional image conversion device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inexpensively convert a two-dimensional still image into a three- dimensional image by dividing a full area included in a single field into groups for each object included in the image and generating the information on the distance of the image of every group. SOLUTION: A field is divided into 60 areas, for example, and the integration value is calculated by the circuits 8, 9, 31 and 32 for the high frequency component, the luminance contrast and the color differences R-Y and B-Y of a luminance signal Y respectively and inputted to a CPU 3. The CPU 3 divides a full area of a single field into groups so as to include the areas whose image feature values are approximate to each other in the same group and generates the distance information on the image of each group based on the image feature value concerning the distance of image of every parallax calculation area. Furthermore, the image vertical position information is added for generation of the information on the distance of image of every parallax calculation area. Then the pixel delay FIFO 11 to 23 are controlled for every parallax calculation area via a parallax control circuit 4, and the distance information is converted into the right-left parallax information in every area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an apparatus and a method for converting into a two-dimensional image.

[0002]

2. Description of the Related Art As a method of converting a two-dimensional video into a three-dimensional video, a video signal which is temporally delayed from an original two-dimensional video signal using a field memory (hereinafter referred to as a delayed video signal). And outputs one of the original two-dimensional video signal and the delayed video signal as a left-eye video signal,
A method of outputting the other as a right-eye video signal is known. However, this method has a problem that the cost is high because a field memory is required to generate a video signal delayed in time with respect to the original two-dimensional video signal. Further, according to this method, only a moving two-dimensional image can be converted into a three-dimensional image.

[0003]

SUMMARY OF THE INVENTION The present invention eliminates the need for a field memory for generating a video signal that is temporally delayed from the original two-dimensional video signal, thereby reducing the cost of a two-dimensional video signal. It is an object of the present invention to provide an apparatus and a method for converting an image into a three-dimensional image.

Another object of the present invention is to provide an apparatus and a method for converting a two-dimensional video into a three-dimensional video, whereby a stereoscopic video can be obtained even if the video represented by the original two-dimensional video signal is a still video. With the goal.

[0005]

An apparatus for converting a two-dimensional image into a three-dimensional image according to the present invention includes a plurality of parallaxes set in one field screen for each field based on a two-dimensional input image signal. For each of the calculation areas,
A feature amount extracting unit that extracts an image feature amount related to the perspective of a video, and a disparity information generating unit that generates disparity information for each predetermined unit area in a one-field screen based on the image feature amount extracted for each disparity calculation area. And a first signal having a horizontal phase difference corresponding to the parallax information corresponding to the predetermined unit area from a signal in each predetermined unit area of the two-dimensional input video signal.
Phase control means for generating a video signal and a second video signal, respectively, wherein the parallax information generating means determines the entire area in one field screen based on the image feature amount relating to the perspective of the video for each parallax calculation area. First means for performing grouping for each object included in the screen, a grouping result obtained by the first means, and an image feature amount relating to perspective of the video for each parallax calculation area, and a video of each group. Second means for generating information about perspective, third means for generating information about perspective of video for each parallax calculation area based on information about perspective for video for each group, and video processing for video for each parallax calculation area. Fourth means for converting information on perspective into parallax information for each parallax calculation area is provided.

[0006] The predetermined unit area is, for example, an area of one pixel unit.

As the first means, for example, the following is used.

(1) On the basis of a frequency distribution indicating the number of parallax calculation regions with respect to the magnitude of the image feature amount related to the perspective of the image, the regions where the size of the image feature amount related to the perspective of the image are in the same group. In this way, all areas in one field screen are grouped.

(2) Based on a frequency distribution indicating the number of parallax calculation areas with respect to the magnitude of image features related to the perspective of the video, areas where the magnitudes of the image features related to the perspective of the video are in the same group. Means for grouping all areas in one field screen as described above, and when there are a plurality of areas spatially separated from each other in the same group, the areas are formed into different groups. Those that have means for grouping.

(3) On the basis of a frequency distribution indicating the number of parallax calculation regions with respect to the magnitude of the image feature amount related to the perspective of the image, the regions where the size of the image feature amount related to the perspective of the image are in the same group. Means for grouping all the areas in one field screen as described above. If there are a plurality of areas spatially separated from each other in the same group, the group is set so that these areas are respectively different groups. If there is a group consisting of a means for performing the division and a predetermined number or less of the parallax calculation areas, the group based on the image feature amount relating to the perspective of the video with respect to the parallax calculation areas in and around the group, Determines whether a group should belong to a surrounding group, and if it determines that the group should belong to a surrounding group. , Which comprises means for causing belong to that group to a group of the surroundings.

(4) On the basis of the frequency distribution indicating the number of parallax calculation regions with respect to the magnitude of the image feature amount relating to the perspective of the image, the regions where the magnitude of the image feature amount relating to the perspective of the image are in the same group. Means for grouping all the areas in one field screen as described above. If there are a plurality of areas spatially separated from each other in the same group, the group is set so that these areas are respectively different groups. Means for performing classification, if there is a group including a predetermined number or less of parallax calculation areas, the group based on the image feature amount related to the perspective of the video with respect to the parallax calculation areas in and around the group; Is determined to belong to the surrounding group, and if it is determined that the group should belong to the surrounding group, The two groups should be combined based on the means for causing the group to belong to the surrounding group, and the image characteristics related to the perspective of the video with respect to the parallax calculation areas in one group and the other group among the two adjacent groups. If it is determined whether or not the two groups should be combined, a means for combining the two groups is provided.

As the second means, for example, based on the image feature amount relating to the perspective of the video for each parallax calculation area in each group and the weighting factor preset for each parallax calculation area, the video of each group is determined. A device that calculates information regarding perspective is used.

As the third means, for example, the following is used.

(1) Among the parallax calculation areas below the height position where the perspective position represented by the information on the perspective of the video is lower than the height position of the screen, the perspective of the video with respect to the parallax calculation area. For a parallax calculation area in which the perspective position represented by the information regarding the parallax calculation area is a position that is more than a predetermined value more than the perspective position represented by the information regarding the perspective of the parallax calculation area immediately above the parallax calculation area, Means for correcting the information related to the perspective of the image with respect to the parallax calculation area so that the perspective position represented by the information about the parallax calculation area approaches the perspective position represented by the information related to the perspective of the image immediately above the parallax calculation area. What you have.

(2) Perspective position of the image with respect to the parallax calculation region among the parallax calculation regions among the parallax calculation regions below the height position where the perspective position represented by the information regarding the perspective of the image is among the height positions of the screen. For a parallax calculation area in which the perspective position represented by the information regarding the parallax calculation area is a position that is more than a predetermined value more than the perspective position represented by the information regarding the perspective of the parallax calculation area immediately above the parallax calculation area, Means for correcting the information related to the perspective of the video with respect to the parallax calculation area so that the perspective position represented by the information about the parallax calculation area approaches the perspective position represented by the information regarding the perspective of the video immediately above the parallax calculation area; At the boundary between the two groups that match each other, the information regarding the perspective of the video is within a predetermined range between the two groups. Sea urchin, which comprises means for correcting the information on the perspective of the image with respect to the parallax calculation region of the boundary portion of the two groups adjacent.

(3) Perspective position of the image with respect to the parallax calculation region, among the parallax calculation regions below the height position where the perspective position represented by the information regarding the perspective of the image is lower than the height position of the screen. For a parallax calculation area in which the perspective position represented by the information regarding the parallax calculation area is a position that is more than a predetermined value more than the perspective position represented by the information regarding the perspective of the parallax calculation area immediately above the parallax calculation area, Means for correcting the information related to the perspective of the video with respect to the parallax calculation area so that the perspective position represented by the information about the parallax calculation area approaches the perspective position represented by the information related to the perspective of the video immediately above the parallax calculation area, At the boundary between the two groups, information on the perspective of the video is set within a predetermined range between the two groups. Means for correcting the information regarding the perspective of the video with respect to the parallax calculation area at the boundary between two adjacent groups, and the difference between the information regarding the perspective of the video between the respective parallax calculation areas within the same group is within a predetermined range. And a means for smoothing information regarding the perspective of the video in each group.

The phase control means has, for example, a first storage which has a capacity capable of storing a two-dimensional input video signal for a plurality of pixels equal to or less than one horizontal line and temporarily stores the two-dimensional input video signal. Means for storing two-dimensional input video signals for a plurality of pixels equal to or less than one horizontal line, and for reading out two-dimensional input video signals temporarily from the second storage means and the first storage means Controlling an address based on disparity information corresponding to a predetermined unit area to which the horizontal and vertical position of the two-dimensional input video signal belongs with respect to a standard read address determined according to the horizontal and vertical position of the two-dimensional input video signal; A first video signal that generates a first video signal whose horizontal phase is advanced by an amount corresponding to the parallax information with respect to a reference horizontal phase defined by the standard read address
And controlling the read address of the second storage means based on the parallax information corresponding to the predetermined unit area to which the horizontal and vertical positions of the two-dimensional input video signal belong with respect to the standard read address. A second read address control means for generating a second video signal whose horizontal phase is delayed by an amount corresponding to the parallax information with respect to a reference horizontal phase defined by the standard read address is used. Can be

The image features relating to the perspective of the video include:
For example, the integrated value of the high frequency component, the luminance contrast, R
Any one or any combination selected from the integrated value of the -Y component and the integrated value of the BY component is used.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a 2D / 3D video converter for converting a 2D video into a 3D video.

A luminance signal Y, a color difference signal RY, and a color difference signal BY constituting a two-dimensional video signal are supplied to an AD conversion circuit 1.
(ADC), the digital Y signal, R-
It is converted into a Y signal and a BY signal.

The Y signal is sent to a high-frequency component integrating circuit 8 and a luminance contrast calculating circuit 9, and is sent to a first left image arbitrary pixel delay FIFO 11 and a first right image arbitrary pixel delay FIFO 21. The RY signal is sent to the RY component integrating circuit 31 and the second
To the left image arbitrary pixel delay FIFO 12 and the second right image arbitrary pixel delay FIFO 22. The BY signal is sent to the BY component integration circuit 32 and
To the left image arbitrary pixel delay FIFO 13 and the third right image arbitrary pixel delay FIFO 23.

As shown in FIG. 2, the high-frequency component integrating circuit 8 calculates the integrated value of the high-frequency component for each of a plurality of parallax calculation areas E1 to E12 set in one field screen, as shown in FIG. . The brightness contrast calculation circuit 9 calculates each parallax calculation area E1 for each field.
The brightness contrast for each of E12 to E12 is calculated. The RY component integrating circuit 31 calculates the integrated value of the RY component for each of the parallax calculation areas E1 to E12 for each field. The BY component integration circuit 32 calculates the integrated value of the BY component for each of the parallax calculation areas E1 to E12 for each field.

The integrated value of the high-frequency component for each of the parallax calculation areas E1 to E12, and each of the parallax calculation areas E1 to E12
Brightness contrast for each, each parallax calculation area E
The integrated value of the RY component for each of the parallax calculation areas E1 to E12 and the integrated value of the BY component for each of the parallax calculation areas E1 to E12 are used as image feature amounts relating to perspective of the video for each of the parallax calculation areas E1 to E12.

Note that a total of 60 parallax calculation areas of 6 rows and 10 columns are actually set in the one-field screen as shown in FIG. 13, but for convenience of explanation, as shown in FIG. It is assumed that a total of 12 parallax calculation areas E1 to E12 of 3 rows and 4 columns are set in one field screen.

Based on the information sent from the high frequency component integrating circuit 8, the luminance contrast calculating circuit 9, the RY component integrating circuit 31, and the BY component integrating circuit 32, the CPU 3 calculates the parallax calculating areas E1 to E12. Is generated. In this example, the parallax information is generated such that the front-side object such as the subject has a smaller parallax amount, and the back-side object such as the background has a larger parallax amount. The details of the method of generating the parallax information will be described later.

The parallax information for each of the parallax calculation areas E1 to E12 calculated by the CPU 3 is sent to the parallax control circuit 4. The parallax control circuit 4 controls the parallax calculation areas E1 to E
Based on the disparity information for No. 12, disparity information for each pixel position in each field is generated. Then, based on the obtained parallax information for each pixel position, each of the FIFOs 11 to
13, 21 to 23, video signals (Y signal, RY signal,
Each of the FIs is adjusted so that the read address when reading the (BY signal) is shifted between the arbitrary pixel delay FIFOs 11 to 13 for the left image and the arbitrary pixel delay FIFOs 21 to 23 for the right image.
The read addresses of the FOs 11 to 13 and 21 to 23 are controlled. Accordingly, the left image arbitrary pixel delay FIFO 11
13 is different from the horizontal phase of the right video signal read from the right video arbitrary pixel delay FIFOs 21 to 23.

Arbitrary pixel delay FIFO 11-13 for left image
From the left video signal (YL signal, (RY) L
Signal, (BY) L signal) is a DA conversion circuit (DAC)
After being converted into an analog signal by 5, it is sent to a three-dimensional display device (not shown). Arbitrary pixel delay FIFO for right image
Right video signal (YR signal,
The (RY) R signal and the (BY) R signal are converted into analog signals by a DA conversion circuit (DAC) 6,
It is sent to a three-dimensional display device (not shown).

Since the horizontal phase of the left video signal is different from the horizontal phase of the right video signal, a parallax occurs between the left video and the right video. As a result, the left image is observed only with the left eye,
When the right image is observed only with the right eye, a three-dimensional image in which the subject is located in front of the background is obtained.

FIG. 3 shows the configuration of the RY component integrating circuit 31.

In FIG. 2, each of the parallax calculation areas E1 to E
12, the number of pixels in the horizontal direction is m, and each of the parallax calculation areas E1 to E
12, the number of pixels in the vertical direction is n, and the first parallax calculation area E1
The horizontal position (HAD), where the coordinates of the upper left of
And the vertical position (VAD).

The RY component integrating circuit 31 includes a timing signal generating circuit 201, an adding circuit 202, an RY component integrating register group 203, and a selecting circuit (SEL) 204. The RY component accumulation register group 203 includes first to first pixels corresponding to the respective parallax calculation areas E1 to E12.
Two RY component integration registers 211 to 222 are provided.

The timing signal generating circuit 201 receives a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync of an input video signal and a clock signal CLK for detecting a horizontal address in each horizontal period.

The timing signal generating circuit 201 outputs first to twelfth enable signals EN1 to EN12, a reset signal RST and an output timing signal DOUT based on the horizontal synchronizing signal Hsync, the vertical synchronizing signal Vsync and the clock signal CLK. .

Each of the enable signals EN1 to EN12 corresponds to each of the parallax calculation areas E1 to E12, and is always at the L level. When the horizontal and vertical positions of the input video signal are in the corresponding areas, the enable signals EN1 to EN12 are set to the H level. Level. The first to twelfth enable signals EN1 to EN12 are input as write signals to the first to twelfth luminance integration registers 211 to 222, respectively. Further, the first to twelfth enable signals EN1 to EN12 are also sent to the selection circuit 204. The selection circuit 204 selects and outputs input data corresponding to the H-level enable signal.

The reset signal RST is output at the effective video start timing of each field in the input video signal and sent to each of the RY component integration registers 211 to 222. When the reset signal RST is input to each of the RY component integration registers 211 to 222, the content is set to 0.

As shown in FIG. 2, the output timing signal DOUT is at the H level for a certain period from the time when the vertical position of the input video signal exceeds the vertical position at the lower end of the parallax calculation area E12 at the bottom. Output timing signal DOUT
Is sent to the CPU 3.

A reset signal is output at the effective video start timing of the input video signal, and the contents of the RY component integration registers 211 to 222 are set to 0. When the horizontal / vertical position of the input video signal is within the first parallax calculation area E1, the first enable signal EN1 is at the H level, and is held in the first RY component integration register 211. The RY value is added to the addition circuit 202 via the selection circuit 204.
And the RY signal in the input video signal is input to the addition circuit 202.

Therefore, the first luminance integrating register 21
The RY value held at 1 and the RY signal in the input video signal are added by the adding circuit 202, and the addition result is stored in the first RY component integration register 211. That is, when the horizontal / vertical position of the input video signal is within the first parallax calculation area E1, the RY values of the pixels within the first parallax calculation area E1 are integrated, and the integration result is calculated as the first value. One RY component accumulation register 211 is stored.

In this manner, the parallax calculation areas E1 to E
The RY component integrated values for each 12 are stored in the corresponding RY component integrated registers 211 to 222. When the output timing signal DOUT becomes H level, each RY
The RY component integrated value for each of the parallax calculation areas E1 to E12 stored in the component integration registers 211 to 222 is C
It is sent to PU3 via a data bus (DATA-BUS).

The configuration of the BY component integration circuit 32 is also the same as the configuration of the RY component integration circuit 31 of FIG. 3, and a description thereof will be omitted.

FIG. 4 shows the configuration of the high frequency component integrating circuit 8.

The high-frequency component integrating circuit 8 includes a timing signal generating circuit 231, a high-pass filter (HPF) 232,
An absolute value conversion circuit 233, a slice processing circuit 234, an addition circuit 235, a high frequency component integration register group 236, and a selection circuit 237 are provided. The high-frequency component accumulation register group 236 includes first to twelfth high-frequency component accumulation registers 241 to 241 corresponding to the parallax calculation areas E1 to E12, respectively.
252.

The input signal and the output signal of the timing signal generation circuit 231 correspond to the timing signal generation circuit 20 shown in FIG.
1 is the same as the input signal and the output signal.

As the high-pass filter 232, for example, as shown in FIG.
A high-pass filter having tap coefficients of −1, 0, 2, 0 and −1 including a bit shift circuit 266 for obtaining an output twice as large as the input value, an adder 267 and a subtractor 268 is used. Can be

Further, as the slice processing circuit 234,
A circuit having input / output characteristics as shown in FIG. 6 is used. The output is set to 0 for inputs from 0 to Ia in order to prevent noise from being extracted as a high-frequency component.

Therefore, the high-frequency component of the Y signal in the input video signal is extracted by the high-pass filter 232, the absolute value thereof is obtained by the absolute value conversion circuit 233, and noise is removed from the absolute value of the high-frequency component by the slice processing circuit 234. You.

A reset signal is output at the effective video start timing of the input video signal, and the contents of each of the high frequency component integration registers 241 to 252 are set to 0. When the horizontal / vertical position of the input video signal is within the first parallax calculation area E1, the first enable signal EN1 is at the H level, so that the high-frequency component held in the first high-frequency component integration register 241 is stored. Is added through the selection circuit 237 to the addition circuit 23.
5 and the high frequency component of the Y signal in the input video signal (the output of the slice processing circuit 234) is input to the addition circuit 235.

Therefore, the high-frequency component held in the first high-frequency component integration register 241 and the high-frequency component of the Y signal in the input video signal are added by the addition circuit 235, and the addition result is added to the first high-frequency component integration. It is stored in the register 241. That is, when the horizontal and vertical positions of the input video signal are within the first parallax calculation area E1, the high-frequency components of the pixels in the first parallax calculation area E1 are integrated, and the integration result is the first. It is stored in the high frequency component integration register 241.

In this manner, each of the parallax calculation areas E1 to E
The integrated value of the high frequency component for each 12 is stored in the corresponding high frequency component integration registers 241-252. Then, when the output timing signal DOUT becomes H level, the integrated value of the high frequency component for each of the parallax calculation areas E1 to E12 stored in each of the high frequency component integration registers 241 to 252 is sent to the CPU 3 via the data bus. .

FIG. 7 shows another example of the high frequency component integrating circuit 8.

The high frequency component integrating circuit 8 includes a timing signal generating circuit 238, a high pass filter 232, a peak detecting circuit 239, an adding circuit 235, a high frequency component integrating register group 236, and a selecting circuit 237.

The timing signal generation circuit 238 is almost the same as the timing signal generation circuit 201 of FIG. 3, but as shown in FIG. 2, the horizontal position of the input video signal is immediately before the parallax calculation areas E1, E5, E9. 3 is different from the timing signal generating circuit 201 in FIG. 3 in that a trigger pulse (region boundary signal RST1) is output when the horizontal position of the image and the horizontal position at the end of each of the parallax calculation regions E1 to E12 are reached. . The region boundary signal RST1 is supplied to the peak detection circuit 23
9

The high frequency component of the Y signal extracted by the high-pass filter 232 is sent to a peak detection circuit 239. The peak detection circuit 239 controls each of the parallax calculation areas E1 to E1.
The maximum value of the high frequency component is detected for each horizontal line in E12. As shown in FIG. 8, a peak detection circuit 239 having a comparison circuit 271, a maximum value register 272, and a gate 273 is used. FIG. 9 shows a horizontal synchronization signal Hsync of an input video signal and an area boundary signal RS.
The output of T1, the gate 273, etc. is shown.

The maximum value register 272 includes a high-frequency component of the Y signal extracted by the high-pass filter 232, an area boundary signal RST 1, and a determination result signal L of the comparison circuit 271.
a and the clock signal CLK are input. Comparison circuit 2
71 compares the output of the maximum value register 272 with the high frequency component of the Y signal in the input video signal, and when the high frequency component of the Y signal is larger than the output of the maximum value register 272,
The determination result signal La is set to the H level.

When the region boundary signal RST1 goes high, the contents of the maximum value register 272 are set to zero. In a state where the region boundary signal RST1 is at the L level, if the determination result signal La from the comparison circuit 271 is at the H level,
The high frequency component of the Y signal is stored in the maximum value register 272. That is, the contents of the maximum value register 272 are updated. Therefore, the maximum value register 272 stores the parallax calculation areas E1 to E12 corresponding to the horizontal and vertical positions of the input video signal every time the area boundary signal RST1 is at the L level.
The maximum value of the high frequency components of the Y signal for each pixel of one horizontal line is stored.

Gate 273 outputs the output value of maximum value register 272 when region boundary signal RST1 attains H level, and outputs 0 when region boundary signal RST1 is at L level. That is, every time the region boundary signal RST1 becomes H level, the gate circuit 273 outputs the predetermined parallax calculation regions E1 to E1 stored in the maximum value register 272.
The maximum value of the high frequency component of the Y signal for one horizontal line in 2 is output. Therefore, the integrated value of the maximum value of the high frequency component of the Y signal for each horizontal line in the corresponding parallax calculation area is accumulated in each of the high frequency component integration registers 241 to 252 (see FIG. 7).

FIG. 10 shows the configuration of the luminance contrast calculation circuit 9.

The luminance contrast calculation circuit 9 includes a timing signal generation circuit 301 and a luminance contrast detection circuit group 302. Brightness / contrast detection circuit group 3
02 denotes first to twelfth luminance contrast detection circuits 311 to 311 corresponding to the parallax calculation areas E1 to E12, respectively.
22.

The input signal and the output signal of the timing signal generation circuit 301 correspond to the timing signal generation circuit 20 shown in FIG.
1 is the same as the input signal and the output signal.

Each luminance contrast detecting circuit 311 to 32
2, includes a first comparison circuit 331, a maximum value register 332, a second comparison circuit 333, a minimum value register 334, and a subtractor 335, as shown in FIG.

The maximum value register 332 stores a Y signal in the input video signal and an enable signal EN (N = 1, N = 1, E2) in the areas E1 to E12 corresponding to the luminance contrast detection circuit.
2... 12), reset signal RST, first comparison circuit 33
1 and the clock signal CL
K is input. The first comparison circuit 331 compares the output value of the maximum value register 332 with the Y signal of the input video signal, and when the Y signal of the input video signal is larger than the output value of the maximum value register 332, sets the determination signal Lb to H. To level.

When the reset signal RST goes high,
The contents of the maximum value register 332 are set to 0. The enable signals EN of the areas E1 to E12 corresponding to the luminance contrast detection circuit are at the H level and the determination signal Lb is at the H level.
When the signal is at the level, the Y signal is stored in the maximum value register 332. That is, the contents of the maximum value register 332 are updated. Therefore, immediately before the output timing signal DOUT is output, the maximum value register 332 stores the parallax calculation area E corresponding to the luminance contrast detection circuit.
The maximum value of the luminance values of the pixels in 1 to E12 is accumulated.

The minimum value register 334 stores the Y signal in the input video signal and the enable signal EN (N = 1, N = 1, E2) in the areas E1 to E12 corresponding to the luminance contrast detection circuit.
2... 12), reset signal RST, second comparison circuit 33
3 and the clock signal CL output from
K is input. The second comparison circuit 333 compares the output value of the minimum value register 334 with the Y signal of the input video signal. When the Y signal of the input video signal is smaller than the output value of the minimum value register 334, the determination signal Lc is set to H. To level.

When the reset signal RST goes high,
A predetermined maximum value is set in the minimum value register 334. When the enable signals EN of the areas E1 to E12 corresponding to the luminance contrast detection circuit are at the H level and the determination signal Lc is at the H level, the Y signal is stored in the minimum value register 334. That is, the minimum value register 3
34 is updated. Therefore, immediately before the output timing signal DOUT is output, the minimum value of the luminance values of the pixels in the parallax calculation areas E1 to E12 corresponding to the luminance contrast detection circuit is accumulated in the minimum value register 334. You.

As a result, at the point in time when the output timing signal DOUT is output, the output of the subtractor 335 is the difference between the maximum value and the minimum value of the luminance values of the pixels in the corresponding parallax calculation areas E1 to E12. The value corresponds to the difference (luminance contrast). Then, the output timing signal DOUT
Is output, the output (luminance contrast) of the subtractor 335 is sent to the CPU 3.

FIG. 12 shows a procedure of the parallax information generation processing for each parallax calculation area performed by the CPU 3.

In the parallax information generation processing for each divided area, grouping processing (step 1), space separation processing (step 2), singularity processing (step 3), inter-group coupling processing (step 4), group-by-group processing Depth information generation processing (step 5), depth information correction processing for all areas (step 6), depth information correction processing for group boundaries (step 7), depth information correction processing for the inside of the group (step 8), and parallax information calculation processing (step 8) Step 9) is performed.

The parallax information generation processing will be described by taking as an example 60 parallax calculation areas actually set for one field. FIG. 13 shows 60 parallax calculation areas F1 to F60 actually set for one field.

(1) Description of grouping process

The grouping process in step 1 is the first process performed for the purpose of grouping all the regions constituting one image for each object included in the image.

There are two grouping methods as described below.

(1-1) First Method First, the high frequency integrated values obtained for each of the parallax calculation areas F1 to F60 are normalized to values within a predetermined range (for example, 0 to 20). Then, a distribution (histogram) of the number of parallax calculation regions belonging to each normalized value of the high-frequency integrated value is generated. FIG.
FIG. 4 shows an example of the generated histogram. And
The parallax calculation areas included in the peaks between the valleys of the histogram are defined as one group. Brightness contrast may be used instead of the high frequency integrated value. FIG.
Shows the result of grouping the parallax calculation areas F1 to F60 in this way. In FIG.
The numbers G1 to G4 indicate group numbers.

(1-2) Second Method The integrated value of the RY component obtained for each of the parallax calculation areas F1 to F60 is normalized to a value in the range of 0 to 20. And R
-Generate a distribution (histogram) of the number of parallax calculation areas belonging to each normalized value of the Y component integrated value. Based on this histogram, a boundary value between groups is determined from the normalized values of the RY component integrated values.

Further, the integrated values of the BY components obtained for each of the parallax calculation areas F1 to F60 are normalized to values in the range of 0 to 10. Then, a distribution (histogram) of the number of parallax calculation regions belonging to each normalized value of the BY component integrated value is generated. Based on the histogram, a boundary value between groups is obtained from the normalized values of the BY component integrated values.

Then, as shown in FIG. 16, all the parallax calculation areas are grouped using the two types of boundary values obtained in this way. FIGS. 17 and 18 show the results of grouping the parallax calculation areas F1 to F60 in this way. 17 and 18, G
1 to G5 indicate group numbers.

In this embodiment, it is assumed that the grouping process has been performed by the second method.

(2) Description of space separation processing

In the spatial separation processing of step 2, among the parallax calculation areas belonging to the same group by the processing of step 1, spatially adjacent parallax calculation areas are combined into one group. That is, even if the parallax calculation areas belong to the same group by the process of step 1, the parallax calculation areas spatially separated by other groups are separated into different groups.

More specifically, as shown in FIG. 19, in step 1, the parallax calculation areas belonging to group 3 (G3) are group 31 (G31), group 32 (G31).
(G32) and group 33 (G33).

(3) Description of singularity processing

In this singularity processing, if there is a group consisting of only one parallax calculation area, does one parallax calculation area correspond to another object different from the other adjacent group? Is determined as corresponding to the same object as another adjacent group.

For example, as shown in FIG. 20, it is assumed that a certain group is a group composed of only one parallax calculation area A. The two parallax calculation areas in the upper direction of the parallax calculation area A are changed from those close to the parallax calculation area A to U
1, U2. The two parallax calculation areas in the lower direction of the parallax calculation area A are changed from those closer to the parallax calculation area A to D1,
D2. The two parallax calculation areas in the left direction of the parallax calculation area A are changed from those close to the parallax calculation area A to L1 and L2.
And The two parallax calculation areas on the right side of the parallax calculation area A are defined as R1 and R2 starting from the one close to the parallax calculation area A.

In this case, the color distance between the area A and the areas U1, D1, L1, and R1 outside the area A by one in each of the up, down, left, and right directions around the area A is one area outside the area A. Areas U1, D1, L1, R1 and 1
If the color distance from the regions U2, D2, L2, and R2 on the outer side is larger than that of the regions U2, D2, L2, and R2, it is determined that the group including only the region A alone forms one group. Otherwise, the area A is determined to belong to the surrounding group. That is, the grouping is corrected.

The definition of the color distance will be described. The BY component integrated value and the RY component integrated value for a certain parallax calculation area Fa are represented by Fa (BY) and Fa (RY), respectively, and the BY component integrated value for a certain parallax calculation area Fb,
The RY component integrated values are represented by Fb (BY) and Fb (R
−Y), the color distance di between the area Fa and the area Fb
st is defined by the following equation 1.

[0086]

(Equation 1)

For example, the (BY component integrated value, RY component integrated value) of the area A in FIG. 20 is (-4, 5) and the area U1
Of (BY component integrated value, RY component integrated value) is (-5,
In 4), it is assumed that the (BY component integrated value, RY component integrated value) of the area U2 is (−7, 2). Area A and area U1
Is the color distance dist of “2”, and the color distance dist of the area U1 and the area U2 is “4”.

If the group 31 (G31) in FIG. 19 is composed of only one parallax calculation area, and it is determined that the group 31 (G1) belongs to the group 1 (G1) by the above-described singularity processing, FIG. Grouping is modified as follows.

(4) Description of Inter-Group Connection Processing

In the inter-group combining process in step 4, first, for each group, the average value of the RY component integrated values and the average value of the BY component integrated values of the parallax calculation areas constituting the group are calculated. You.

Next, the color distance between two adjacent groups is calculated. That is, two adjacent groups are defined as Ga and Gb. Assuming that the group Ga is composed of n parallax calculation areas a1, a2,... An, the average value * Ga of the integrated values of the BY components of the group Ga
Average value of (BY) and RY component integrated values * Ga (R
−Y) is obtained by the following Expression 2.

[0092]

(Equation 2)

Assuming that the group Gb is composed of m parallax calculation areas b1, b2,... Bm, the average value * Gb (BY) of the integrated values of the BY components of the group Gb and R- The average value * Gb (RY) of the Y component integrated value is obtained by the following equation (3).

[0094]

(Equation 3)

The color distance dist between the group Ga and the group Gb is defined by the following equation (4).

[0096]

(Equation 4)

Then, it is determined whether or not the color distance between two adjacent groups is smaller than a threshold value. When the color distance is smaller than the threshold value, these two groups are combined. That is, these two groups are combined into one group.

(5) Depth information generation processing for each group

In the depth information generation processing for each group in step 5, first, the integrated value of the high frequency components obtained for each of the parallax calculation areas F1 to F60 is normalized to a value in the range of 0 to 10. Further, the luminance contrast obtained for each of the parallax calculation areas F1 to F60 is normalized to a value in the range of 0 to 10.

Then, the normalized value of the obtained integrated value of the high-frequency component, the normalized value of the luminance contrast, and the background weight component given in advance for each of the parallax calculation areas F1 to F60 as shown in FIG. Based on this, depth information for each group is generated.

A method of generating depth information for an arbitrary group will be described. First, the number n of parallax calculation areas belonging to the group is determined. Further, the sum Σa of the normalized values a of the integrated values of the high frequency components for the parallax calculation regions belonging to the group is calculated. Further, the sum Σb of the normalized values b of the brightness contrasts for the parallax calculation areas belonging to the group is calculated. Also,
The sum Σc of the background weight components c for the parallax calculation regions belonging to the group is calculated.

Then, based on the following equation 5, depth information H for the group is generated.

[0103]

(Equation 5)

In Equation 5, K1, K2 and K3 are coefficients, for example, K1 = 3/8, K2 = 1/8,
K3 = 4/8.

(6) Depth Information Correction Processing for All Regions

In the depth information correction processing for each group in step 5, first, an average value of depth information is calculated for each row of the parallax calculation areas F1 to F60. If the depth information for each of the parallax calculation areas F1 to F60 has a value as shown in FIG. 23, for example, the average value of the depth information for each of the first to sixth rows is 1.2, 3 .6, 6.0, 7.
2, 4.0, and 1.2.

Next, from each row of the parallax calculation area, an area where many objects at the near position are reflected is extracted. That is,
The row having the largest average value of the depth information is extracted. FIG.
In the example of No. 3, the area of the fourth row is extracted.

Next, with respect to each area of the row below the extracted row, each area of the row below the extracted row is compared with the area immediately above so that the depth information does not suddenly decrease. Is adjusted. In particular,
For an area in which the depth information of each area in the row below the extracted row is smaller than the area immediately above by 3 or more, the depth information of the area is set to a value smaller by 2 than the depth information of the area immediately above. Can be changed.

In the example of FIG. 23, as shown in FIG. 24, among the regions F41 to F50 in the fifth row, first, the regions F42 to F49 whose depth information is smaller than the depth information of the region immediately above by three or more. , The depth information is corrected.
Thereafter, among the regions F51 to F60 in the sixth row, the depth information is corrected for the regions F53 to F58 whose depth information is smaller than the depth information (corrected depth information) of the region immediately above by three or more. Is done.

That is, when the relationship of the depth information with respect to the screen height at an arbitrary horizontal position is a relationship as shown by the curve U1 in FIG. 25, the relationship between the depth information and the screen height is corrected by the depth correction. However, FIG.
The correction is made so as to have the relationship shown in FIG.

As described above, in each row of the parallax calculation area,
The reason that the depth information of the area below the area where many objects at the near position are reflected is corrected for the following reason.

In general, an object existing in front is often displayed on the lower side of the screen. Further, the object reflected on the lower side of the screen is often an image with little change such as the ground. An image with little change, such as the ground, has a low high-frequency component, so that the value of the depth information is small even though it is ahead. Therefore, depth information is increased by depth correction so that the depth information of an image located in front of the object and having a low high-frequency component is not larger than the value of the depth information of the area immediately above the image.

(7) Description of Depth Information Correction Processing for Group Boundary

At the boundary between two adjacent groups, grouping may not be performed correctly. In addition, if the depth estimation value for each group is significantly different at the boundary between two adjacent groups, image distortion becomes significant.

Therefore, in the depth information correction processing for the group boundary in step 7, first, for each boundary between two adjacent groups, the depth information of the parallax calculation area of one group and the parallax calculation area of the other group are set. It is determined whether the difference from the depth information is equal to or greater than a predetermined value. When the difference between the two pieces of depth information is equal to or greater than a predetermined value, the smaller depth information (that is, the one located rearward) is set so that the difference between the two pieces of depth information becomes smaller than the predetermined value. The depth information for the parallax calculation area is increased.

(8) Description of Depth Information Correction Process for Inside Group

Due to the correction processing in steps 6 and 7, there is a difference in depth information depending on the region even in the same group. When this difference increases, the image distortion becomes significant. Therefore, in the depth information correction processing for the inside of the group in step 8, the estimated depth value in the group is smoothed for each group.

That is, as shown in FIG. 26, in the same group, the attention area is A, the depth information corresponding thereto is HA, and the four adjacent areas are U, D, L,
R, depth information for them HU, HD, HL, H
Assuming that R, the estimated depth value HA for the attention area A is corrected by the following Expression 6.

[0119]

(Equation 6)

Each of the parallax calculation areas F thus obtained
The depth information for each of 1 to F60 is normalized again within the range of 0 to 10.

(9) Description of parallax information calculation processing

In the parallax information calculation processing of step 9, the depth information for each of the parallax calculation areas F1 to F60 is stored in each area F1.
Is converted into disparity information for each of F60.

That is, the depth information is converted into the parallax information for each of the areas F1 to F60 based on the relationship between the depth information and the parallax information set in advance. The relationship between the depth information and the disparity information is shown in FIG.
As shown by 2, the relationship is inversely proportional.

In FIG. 27, the relationship between the depth information indicated by the straight line S1 and the parallax information is used when a stereoscopic image having a relatively strong stereoscopic effect is desired to be obtained. The relationship between the depth information indicated by the straight line S2 and the parallax information is used when it is desired to obtain a stereoscopic image having a relatively weak stereoscopic effect. The relationship between the depth information and the parallax information is represented by a straight line S1 and a straight line S2.
It is possible to adjust the three-dimensional effect by adjusting between.

The thus obtained disparity information for each disparity calculation area is sent to the disparity control circuit 4 (see FIG. 1).

FIG. 28 mainly shows the configuration of the parallax control circuit and the arbitrary pixel delay FIFO shown in FIG. In the following, the parallax calculation area is set to E1 as shown in FIG.
To E12.

FIG. 28 shows an arbitrary pixel delay FIFO 11 to 11.
13, 21 to 23, left image arbitrary pixel delay FIFO 11 and right image arbitrary pixel delay FI for Y signal
Although only FO21 is shown, other arbitrary pixel delays FI
FO12, 13, 22, and 23 have the same configuration and perform the same control, so that other arbitrary pixel delay FIFOs
Descriptions of the configurations and control methods of 12, 13, 22, and 23 are omitted.

Incidentally, the disparity information calculated by the CPU 3 is disparity information for the center position of each of the disparity calculation areas E1 to E12. The parallax control circuit 4 obtains parallax information for each pixel position on a one-field screen based on the parallax information for the center position of each of the parallax calculation areas E1 to E12. Then, in order to generate a left image and a right image having parallax corresponding to the parallax information for the pixel position from the two-dimensional video signal for each pixel position, an arbitrary left video image is generated based on the parallax information for each pixel position. Pixel delay F
IFO 11-13 and right pixel arbitrary pixel delay FIFO
The read addresses 21 to 23 are controlled.

The parallax information for each pixel position on the one-field screen is stored in the timing signal generation circuit 51, the parallax interpolation coefficient generation circuit 52, the parallax information storage means 60, and the parallax selection circuit 8.
0, and is generated by the first to fourth multipliers 81 to 84 and the addition circuit 85.

The horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync of the input video signal are input to the timing signal generation circuit 51. Further, a clock signal CLK for detecting a horizontal address in each horizontal period is also input to the timing signal generation circuit 51.

The timing signal generating circuit 51 generates a horizontal address signal HAD indicating an absolute horizontal position of an input video signal, an absolute vertical position of the input video signal, based on the horizontal synchronizing signal Hsync, the vertical synchronizing signal Vsync and the clock signal CLK. And a relative horizontal position signal HPOS representing the relative horizontal position of the input video signal.
And a relative vertical position signal VPOS indicating the relative vertical position of the input video signal is generated and output.

The relative horizontal position and the relative vertical position of the input video signal will be described.

As shown in FIG. 29, the parallax calculation areas E1 to E12 in FIG. 2 are set as follows. As shown by the dotted line in FIG. 29, the entire screen is divided into 20 regions of 4 rows and 5 columns (hereinafter, referred to as first divided regions). Then, a quadrangular area having four vertices at the center of the first divided area at the upper left, the center of the first divided area at the upper right, the center of the first divided area at the lower left, and the center of the first divided area at the lower right is 3 Row 4
The column is divided into 12 regions (hereinafter, referred to as second divided regions), and each of the second divided regions is set as parallax calculation regions E1 to E12.

The number of pixels in the horizontal direction of the first divided region and the second divided region is represented by m, and the number of pixels in the first divided region and the second divided region in the vertical direction is represented by n. The relative horizontal position of the input video signal is represented by 0 to (m-1), with the left end of each first divided area being 0 and the right end being m.
The relative vertical position of the input video signal is represented by 0 to (n-1), with the upper end of each first divided area being 0 and the lower end being n.

The relative horizontal position signal HPO of the input video signal
S and the relative vertical position VPOS are sent to the parallax interpolation coefficient generation circuit 52. The parallax interpolation coefficient generation circuit 52 generates a first parallax interpolation coefficient KUL based on the relative horizontal position signal HPOS, the relative vertical position VPOS, and the following equation (7).
A second parallax interpolation coefficient KUR, a third parallax interpolation coefficient KDL, and a fourth parallax interpolation coefficient KDR are generated and output.

[0136]

(Equation 7)

FIG. 3 shows the basic concept of a method for generating disparity information for each pixel position on a one-field screen.
Explanation will be made using 0. It is assumed that the horizontal and vertical position (hereinafter, referred to as a target position) represented by the horizontal address signal HAD and the vertical address signal VAD is Pxy in FIG. A case where parallax information for the target position Pxy is obtained will be described.

(1) First, from among the parallax information for each of the parallax calculation areas E1 to E12 calculated by the CPU 3, four vertices of the first divided area including the target position Pxy,
In this example, disparity information for the disparity calculation areas E1, E2, E5, and E6 centered on PE1, PE2, PE5, and PE6 is extracted as UL, UR, DL, and DR, respectively. That is, of the four vertices of the first divided region including the target position Pxy, the disparity information of the region E1 centered on the upper left vertex is the first disparity information UL, and the disparity information of the region E2 centered on the upper right vertex is UL. Is extracted as the second disparity information UR, the disparity information of the region E5 centered on the lower left vertex is extracted as the third disparity information DL, and the disparity information of the region E6 centered on the lower right vertex is extracted as the fourth disparity information DR. You.

However, only one vertex of the four vertices of the first divided region including the target position is disparity, as in the case where the first divided region including the target position is the first upper left divided region. If the parallax information corresponds to the center of the detection area, the parallax information of the parallax calculation area is the first to fourth parallax information U
Extracted as L, UR, DL, DR.

Further, as in the case where the first divided area including the target position is the first divided area on the right of the first divided area at the upper left corner, four vertices of the first divided area including the target position are used. Among the four vertices of the first divided region including the target position, only the lower two vertices of the first divided region include the parallax information UL, As the UR, the parallax information of the parallax calculation area centered on the lower vertex is extracted.

Further, as in the case where the first divided area including the target position is the first divided area below the first divided area at the upper left end, the four vertices of the first divided area including the target position are used. Among the four vertices of the first divided area including the position of interest, only the two vertices on the right correspond to the center of the parallax calculation area. , The parallax information of the parallax calculation area centered on the right vertex is extracted.

Further, as in the case where the first divided region including the target position is the first divided region to the left of the first lower divided region at the lower right, four vertices of the first divided region including the target position are used. If only the upper two vertices of the first divisional area correspond to the center of the parallax calculation area, the parallax information DL corresponding to the lower two vertices of the four vertices of the first divided area including the target position, As DR, parallax information of a parallax calculation area centered on the upper vertex is extracted.

Also, as in the case where the first divided region including the target position is the first divided region above and above the first divided region at the lower right, four vertices of the first divided region including the target position are used. Among the four vertices of the first divided area including the target position, only the two vertexes on the left side of the parallax calculation area correspond to the center of the parallax calculation area. , The parallax information of the parallax calculation area centered on the left vertex is extracted.

(2) Next, the first to fourth parallax interpolation coefficients K
UL, KUR, KDL and KDR are required.

The first parallax interpolation coefficient KUL is determined by the target position P
xy, the distance ΔX from the target position Pxy to the right side of the first divided area e with respect to the horizontal width m of the first divided area e including xy
R and the ratio {(m-HPOS) / m} to the first divided region e
の (n−VPO) of the vertical width n to the distance ΔYD from the target position Pxy to the lower side of the first divided region e.
S) / n}. That is, the first
Is larger as the distance between the upper left vertex PE1 of the first divided area e including the target position Pxy and the target position Pxy is smaller.

The second parallax interpolation coefficient KUR is calculated based on the target position P
xy, the distance ΔX from the target position Pxy to the left side of the first divided region e with respect to the horizontal width m of the first divided region e
L (HPOS / m) and the ratio {(n-VPOS) / n} of the distance ΔYD from the target position Pxy to the lower side of the first divided region e with respect to the vertical width n of the first divided region e.
And the product of That is, the second parallax interpolation coefficient KUR increases as the distance between the upper right vertex PE2 of the first divided region e including the target position Pxy and the target position Pxy decreases.

The third parallax interpolation coefficient KDL is calculated based on the target position P
xy, the distance ΔX from the target position Pxy to the right side of the first divided area e with respect to the horizontal width m of the first divided area e including xy
R and the ratio {(m-HPOS) / m} to the first divided region e
(VPOS / n) of the distance ΔYU from the target position Pxy to the upper side of the first divided area e with respect to the vertical width n of
And the product of That is, the third parallax interpolation coefficient KDL increases as the distance between the lower left vertex PE5 of the first divided region e including the target position Pxy and the target position Pxy decreases.

The fourth parallax interpolation coefficient KDR is calculated based on the target position P
xy, the distance ΔX from the target position Pxy to the left side of the first divided region e with respect to the horizontal width m of the first divided region e
L and the ratio (VPOS / n) of the vertical width n of the first divided area e to the distance ΔYU from the target position Pxy to the upper side of the first divided area e. Desired. That is, the fourth parallax interpolation coefficient KD
R increases as the distance between the lower right vertex PE6 of the first divided area e including the target position Pxy and the target position Pxy decreases.

(3) The first to fourth extracted in the above (1)
To the parallax information UL, UR, DL, DR of the first to fourth parallax interpolation coefficients KUL, calculated in (2) above, respectively.
KUR, KDL, and KDR are each multiplied. Then, the obtained four multiplication values are added to generate disparity information for the target position Pxy.

The parallax information storage means 60 stores the areas E1 to E1.
2 are provided with first to twelfth parallax registers 61 to 72 provided correspondingly to the two. The first to twelfth disparity registers 61 to 72 store disparity information for each of the regions E1 to E12 generated by the CPU 3.

At the subsequent stage of the parallax information storage means 60, a parallax selection circuit 80 is provided. In the parallax selection circuit 80,
Parallax information is sent from each of the parallax registers 61 to 72. Further, the horizontal address signal HAD and the vertical address signal VAD are sent from the timing signal generation circuit 51 to the parallax selection circuit 80.

According to the rule shown in FIG. 31 (a), the parallax selecting circuit 80 sets the area corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 30, the first area including the target position). Of the parallax calculation area centered on the upper left vertex of the
Select and output as L. Further, the parallax selection circuit 80
According to the rule shown in FIG. 31B, a region corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 30, the center is located at the upper right vertex of the first region including the target position) The disparity information for the disparity calculation area) is selected and output as the second disparity information UR.

Further, the parallax selecting circuit 80 is provided in FIG.
According to the rule shown in (c), an area corresponding to the horizontal address signal HAD and the vertical address signal VAD (a parallax calculation area centered on the lower left vertex of the first area including the target position in the example of FIG. 30). Is selected and output as third parallax information DL. Further, the parallax selection circuit 80 determines the area corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 30, the first area including the target position in accordance with the rule shown in FIG. 31D). Parallax calculation area centered on the lower right vertex)
Is selected and output as fourth parallax information DR. In FIG. 31, for example, the symbols “” ”represented by a and b, such as 0 to m, are used as symbols meaning a or more and less than b.

The first selected by the parallax selection circuit 80
The disparity information UL, the second disparity information UR, the third disparity information DL, and the fourth disparity information DR are input to first, second, third, and fourth multipliers 81, 82, 83, 84, respectively.

First, second, third and fourth multipliers 8
1, 82, 83, and 84 also receive the first parallax interpolation coefficient KUL, the second parallax interpolation coefficient KUR, the third parallax interpolation coefficient KDL, and the fourth parallax interpolation coefficient KDR from the parallax interpolation coefficient generation circuit 52, respectively. I have.

The first multiplier 81 multiplies the first disparity information UL by a first disparity interpolation coefficient KUL. The second multiplier 82
The second parallax information UR is multiplied by a second parallax interpolation coefficient KUR. The third multiplier 83 multiplies the third disparity information DL by a third disparity interpolation coefficient KDL. The fourth multiplier 84 multiplies the fourth disparity information DR by a fourth disparity interpolation coefficient KDR.

The outputs of the multipliers 81, 82, 83, 84 are added by an adder 85. Thereby, the disparity information PR for the target position is obtained.

Each of the arbitrary pixel delay FIFOs 11 and 21 is 1
To perform horizontal phase control in units smaller than pixels,
Each of the two line memories 11a, 11b, 21a,
21b. Each arbitrary pixel delay FIFO11, 2
1, two line memories 11a, 11b, 21a, 2
1b, a Y signal is input and a clock signal CLK is input.

The horizontal address signal HAD output from the timing signal generation circuit 51 is also input to the standard address generation circuit 90. Standard address generation circuit 90
Is a standard write address WAD and a standard read address R for the two line memories 11a, 11b, 21a, 21b in each of the arbitrary pixel delay FIFOs 11, 21.
Generate and output AD. Further, the standard address generation circuit 90 also outputs a synchronization signal Csync added to the left video signal and the right video signal obtained by the 2D / 3D converter. The horizontal synchronization signal represented by the synchronization signal Csync is a horizontal synchronization signal Hsync of the input video signal.
The signal is delayed by a predetermined number of clocks from c.

The standard read address RAD is used to advance or delay the horizontal phase of the video signal input to each of the arbitrary pixel delay FIFOs 11 and 21 with respect to the reference horizontal phase defined by the standard read address. In addition, it is delayed by a predetermined number of clocks from the standard write address WAD. The standard write address WAD output from the standard address generation circuit 90 is stored in the two line memories 11 in each of the arbitrary pixel delay FIFOs 11 and 21.
a, 11b, 21a, and 21b are input as write control signals indicating write addresses.

The standard read address RAD output from the standard address generation circuit 90 is input to an adder 91 and a subtractor 92, respectively. Adder 91 and subtractor 9
2, the parallax information PR of the target position output from the adding circuit 85 is also input.

At the adder 91, the standard read address R
The disparity information PR is added to AD. As a result, the left video read address PRL is obtained.

The integer part PRL1 of the left video read address PRL is stored in the first line memory 11a in the left video arbitrary pixel delay FIFO 11 in the read address RADL1.
Enter as Therefore, the first line memory 11
The Y signal is read from the address corresponding to the address RADL1 of a. The read Y signal is input to the first left video multiplier 101.

The address value obtained by adding 1 to the integer part PRL1 of the left video read address PRL is input to the second line memory 11b in the left video arbitrary pixel delay FIFO 11 as the read address RADL2. Therefore, the Y signal is read from the address corresponding to the address RADL2 of the second line memory 11b. The read Y signal is input to the second left video multiplier 102.

The read address RADL1 for the first line memory 11a is different from the read address RADL2 for the second line memory 11b by one, so that the Y signal read from the first line memory 11a The Y signal read from the second line memory 11b is a signal whose horizontal position is shifted by one.

The fractional part PRL2 of the left video read address PRL is input to the second left video multiplier 102 as a second left video interpolation coefficient. A value obtained by subtracting the decimal part PRL2 of the read address PRL for the left image from 1 (1-PR
L2) is input to the first left video multiplier 101 as a first left video interpolation coefficient.

Therefore, the first left video multiplier 101
Then, the Y signal read from the first line memory 11a is multiplied by a first left video interpolation coefficient (1-PRL2). In the second left video multiplier 102, the Y signal read from the second line memory 11b is multiplied by a second left video interpolation coefficient PRL2. Then, each multiplier 101,
The Y signal obtained by 102 is added by the adder 103, and then output as a left video Y signal YL-OUT.

Thus, the standard read address RAD
With respect to the reference horizontal phase defined by the above, a left image Y signal whose horizontal phase amount is delayed by an amount corresponding to the parallax information for the target position is obtained.

In the subtractor 92, the standard read address R
The disparity information PR is subtracted from AD. As a result, the right video read address PRR is obtained.

The integer part PRR1 of the read address PRR for the right image is stored in the first line memory 21a in the arbitrary pixel delay FIFO 21 for the right image in the read address RADR1.
Enter as Therefore, the first line memory 21
The Y signal is read from the address corresponding to the address RADR1 of a. The read Y signal is input to the first right video multiplier 111.

The address value obtained by adding 1 to the integer part PRR1 of the read address PRR for the right image is input to the second line memory 21b in the arbitrary pixel delay FIFO 21 for the right image as the read address RADR2. Therefore, the Y signal is read from the address corresponding to the address RADR2 of the second line memory 21b. The read Y signal is input to the second right video multiplier 112.

Since the read address RADR1 for the first line memory 21a is different from the read address RADR2 for the second line memory 21b by one, the Y signal read from the first line memory 21a and The Y signal read from the second line memory 21b is a signal whose horizontal position is shifted by one.

The decimal part PRR2 of the read address PRR for the right image is input to the second right image multiplier 112 as a second right image interpolation coefficient. A value obtained by subtracting the decimal part PRR2 of the read address PRR for the right image from 1 (1-PR
R2) is input to the first right image multiplier 111 as a first right image interpolation coefficient.

Therefore, the first right video multiplier 111
Then, the Y signal read from the first line memory 21a is multiplied by a first right video interpolation coefficient (1-PRR2). In the second right image multiplier 112, the Y signal read from the second line memory 21b is multiplied by a second right image interpolation coefficient PRR2. Then, each multiplier 111,
The Y signal obtained by 112 is added by the adder 113 and then output as a right video Y signal YR-OUT.

As a result, the standard read address RAD
With respect to the reference horizontal phase defined by the above, a Y signal for right video is obtained in which the horizontal phase amount is advanced by an amount corresponding to the parallax information for the target position.

FIG. 32 shows that the parallax information for the target position is 0.
3 shows the signals of the respective units.

When the disparity information is 0, the left video read address PRL output from the adder 91 and the right video read address PRR output from the subtractor 92 are output.
Is an address consisting of only an integer part without a decimal part equal to the standard read address RAD.

Therefore, the arbitrary pixel delay FIF for the left image
Read address RADL1 for the first line memory 11a in O11 and right image arbitrary pixel delay FIFO
The read address RADR1 for the first line memory 21a in the memory 21 is equal to the standard read address RAD.

Also, an arbitrary pixel delay FIFO 11 for the left image
The read address RADL2 for the second line memory 11b in the first and the read address RADR2 for the second line memory 21b in the right image arbitrary pixel delay FIFO 21 have a value that is one greater than the standard read address RAD.

The first left video interpolation coefficient (1-PRL)
2) and the first right video interpolation coefficient (1-PRR2) are 1
And the second left video interpolation coefficient PRL2 and the second right video interpolation coefficient PRR2 become zero.

As a result, a left image arbitrary pixel delay FIFO
11, the standard address RA of the first line memory 11a
The Y signal read from the address corresponding to D is output from the adder 103 as the left video Y signal YL-OUT, and corresponds to the standard address RAD of the first line memory 21a in the right video arbitrary pixel delay FIFO 21. The Y signal read from the address to be output is output from the adder 113 as a right video Y signal YR-OUT. That is, two Y signals having the same amount of phase shift in the horizontal direction, that is, two Y signals having no parallax are output as a left video Y signal and a right video Y signal.

FIG. 33 shows each address value when the standard write address WAD for a certain target position is 20, the standard read address RAD for the target position is 10, and the disparity information for the target position is 1.2. Is shown. FIG. 34 shows signals of the respective units at that time.

In this case, the left video read address PRL output from the adder 91 is 11.2,
Its integer part PRL1 becomes 11, and its decimal part PRL2
Is 0.2.

Therefore, the arbitrary pixel delay FIF for the left image
The read address RADL1 for the first line memory 11a in O11 is 11, and the read address RADL2 for the second line memory 11b is 12. Further, the first left video interpolation coefficient KL1 ｛= (1-PR
L2)｝ is 0.8, and the second left image interpolation coefficient KL2
(= PRL2) is 0.2.

Therefore, the left image arbitrary pixel delay FIF
The Y signal (Y ₁₁ ) is read from the address 11 of the first line memory 11 a in O 11, and a signal (0) that is 0.8 times the read Y signal (Y ₁₁ ) is read from the first multiplier 101. .
8 * Y ₁₁ ) is output.

On the other hand, a left image arbitrary pixel delay FIFO 11
, The Y signal (Y ₁₂ ) is read from the address 12 of the second line memory 11 b, and the signal (0...) Which is 0.2 times the Y signal (Y ₁₂ ) read from the second multiplier 102. 2 * Y
₁₂ ) is output. Then, from the adder 103, 0.
Y signal YL for left image corresponding to 8 * Y ₁₁ + 0.2 * Y ₁₂
−OUT is output. That is, read address 1
The Y signal corresponding to 1.2 is a left video Y signal YL-OU.
Output as T.

The read address PRR for the right image output from the subtractor 92 is 8.8, and its integer part PRR
1 becomes 8, and the decimal part PRR2 becomes 0.8.

Therefore, the arbitrary pixel delay FIF for right video
The read address RADR1 for the first line memory 21a in O21 becomes 8, and the second line memory 2a
The read address RADR2 for 1b is 9.
Also, the first right video interpolation coefficient KR1 ｛= (1-PRR
2) と な り is 0.2, and the second right video interpolation coefficient KR2
(= PRR2) is 0.8.

Therefore, an arbitrary pixel delay FIF for right video
Y signal (Y ₈₎ is read from the first line memory 21a of the address 8 in O21, 0.2 times the signal of the Y signal read out from the first multiplier 111 (Y ₈₎ (0 .2
* Y ₈ ) is output.

On the other hand, a right image arbitrary pixel delay FIFO 21
, The Y signal (Y ₉ ) is read from the address 9 of the second line memory 21 b, and the signal (0...) 0.8 times the read Y signal (Y ₉ ) from the second multiplier 112. 8 *
Y ₉ ) is output. Then, from the adder 113,
A right video Y signal YR-OUT corresponding to 0.2 * Y ₈ + 0.8 * Y ₉ is output. In other words, the Y signal corresponding to the read address 8.8 is the right video Y signal YR-OU.
Output as T.

As a result, a left image and a right image having a disparity of 11.2−8.8 = 2.4, that is, a disparity twice as large as the disparity information 1.2 are obtained.

In the 2D / 3D video converter according to the above-described embodiment, a field memory for generating a video signal that is temporally delayed from the original two-dimensional video signal is unnecessary, so that the cost can be reduced. Can be achieved. Further, in the 2D / 3D video converter according to the above-described embodiment, a stereoscopic video can be obtained even if the video represented by the original two-dimensional video signal is a still video.

Also, the entire area in one field screen is grouped for each object included in the screen, and
Since the information about the perspective of the video for each group is generated, the parallax variation of each part in the same object is suppressed. As a result, image distortion is reduced within the same object, and good stereoscopic vision is possible.

[0194]

According to the present invention, a field memory for generating a video signal delayed in time from the original two-dimensional video signal is not required, and a two-dimensional video whose cost can be reduced is reduced. An apparatus and method for converting to a two-dimensional image are realized.

Further, according to the present invention, an apparatus and a method for converting a two-dimensional video into a three-dimensional video, which can obtain a stereoscopic video even when the video represented by the original two-dimensional video signal is a still video, are realized. I do.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a 2D / 3D video conversion device.

FIG. 2 is a schematic diagram illustrating a parallax calculation area.

FIG. 3 is a block diagram illustrating a configuration of an RY component integrating circuit.

FIG. 4 is a block diagram illustrating a configuration of a high-frequency component integration circuit.

FIG. 5 is a circuit diagram showing a specific example of a high-pass filter 232 of FIG.

FIG. 6 is a graph showing input / output characteristics of the slice processing circuit 234 of FIG.

FIG. 7 is a block diagram showing another example of the high frequency component integrating circuit.

8 is a circuit diagram showing a specific example of the peak detection circuit 239 in FIG.

FIG. 9 is a time chart showing signals of respective parts of the peak detection circuit 239.

FIG. 10 is a block diagram illustrating a configuration of a luminance contrast calculation circuit.

11 is a circuit diagram illustrating a configuration of a luminance contrast detection circuit in FIG.

FIG. 12 is a flowchart illustrating a generation processing procedure of disparity information by a CPU.

FIG. 13 is a schematic diagram illustrating a parallax calculation area actually set.

FIG. 14 is a histogram showing the number of parallax calculation regions for each normalized value of the high-frequency component integrated value.

FIG. 15 is a schematic diagram showing a grouping result obtained based on the histogram of FIG. 14;

FIG. 16 shows the normalized value of the RY component integrated value on the vertical axis,
9 is a graph showing the distribution of the parallax calculation area, with the normalized value of the BY component integrated value as the horizontal axis.

FIG. 17 is a schematic diagram showing a grouping result obtained based on the graph of FIG. 16;

FIG. 18 is a schematic diagram showing a grouping result obtained based on the graph of FIG.

FIG. 19 is a schematic diagram showing a grouping result corrected by the spatial separation processing.

FIG. 20 is a schematic diagram for explaining singularity processing.

FIG. 21 is a schematic diagram showing a grouping result corrected by singularity processing.

FIG. 22 is a schematic diagram showing background weight components set in advance for each parallax calculation area.

FIG. 23 is a schematic diagram illustrating an example of depth information of each parallax calculation area before depth correction.

FIG. 24 is a schematic diagram illustrating depth information of each parallax calculation area after depth correction.

FIG. 25 is a graph showing the relationship between the height position of the screen before depth correction and the depth information and the relationship between the height position of the screen after depth correction and the depth information.

FIG. 26 is a schematic diagram for describing depth information correction processing for the inside of a group.

FIG. 27 is a graph illustrating a relationship between depth information and disparity information.

FIG. 28 is a block diagram mainly illustrating a configuration of a parallax control circuit and an arbitrary pixel delay FIFO.

FIG. 29 is a schematic diagram illustrating a relative horizontal position, a relative vertical position, and the like.

FIG. 30 is an explanatory diagram for describing a method of generating disparity information for a target pixel.

FIG. 31 is a diagram illustrating a selection rule by a parallax selection circuit.

FIG. 32 is a time chart illustrating signals of respective units when disparity information is 0.

FIG. 33 is a block diagram in which each address value when the disparity information is 1.2 is added to the disparity control circuit.

FIG. 34 is a time chart showing signals of respective units when the disparity information is 1.2.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 AD conversion circuit 3 CPU 4 Parallax control circuit 5, 6 DA conversion circuit 8 High frequency component integration circuit 9 Luminance contrast calculation circuit 11, 12, 13 Left pixel arbitrary pixel delay FIFO 11 a, 11 b, 21 a, 21 b Line memory 21, 22 , 23 Right pixel arbitrary pixel delay FIFO 31 RY component integration circuit 32 BY component integration circuit 51, 201, 231, 238, 301 Timing signal generation circuit 52 Parallax interpolation coefficient generation circuit 60 Parallax information storage means 61-72 Parallax register 80 Parallax selection circuit 81-84 Multiplier 85 Addition circuit 90 Standard address generation circuit 91 Adder 92 Subtractor 101, 102, 111, 112 Multiplier 103, 113 Adder

Claims (12)

[Claims] 1. A feature amount for extracting an image feature amount related to perspective of an image for each of a plurality of parallax calculation areas set in one field screen for each field based on a two-dimensional input image signal. Extracting means, disparity information generating means for generating disparity information for each predetermined unit area in one field screen based on the image feature amount extracted for each disparity calculation area, and each predetermined unit area of the two-dimensional input video signal And a phase control unit for respectively generating a first video signal and a second video signal having a horizontal phase difference corresponding to the parallax information corresponding to the predetermined unit region from the signals in the sub-regions. A first unit configured to group all regions in a one-field screen for each object included in the screen based on an image feature amount related to perspective of a video for each parallax calculation region; Second means for generating information on the perspective of the video for each group based on the grouping result by the first means and the image feature amount relating to the perspective of the video for each parallax calculation area, Third means for generating information about the perspective of the video for each parallax calculation area based on the information, and fourth means for converting the information about the perspective of the video for each parallax calculation area into parallax information for each parallax calculation area. An apparatus for converting a 2D image into a 3D image, comprising: 2. The image processing apparatus according to claim 1, wherein, based on a frequency distribution indicating the number of parallax calculation regions with respect to the magnitude of the image feature amount related to the perspective of the video, an area in which the size of the image feature amount related to the perspective of the video is approximated. 2. The apparatus for converting a two-dimensional video into a three-dimensional video according to claim 1, wherein all the areas in one field screen are grouped so as to be in the same group. 3. The image processing apparatus according to claim 1, wherein, based on a frequency distribution indicating the number of parallax calculation areas with respect to the magnitude of the image feature amount related to the perspective of the video, an area in which the size of the image feature amount related to the perspective of the video is approximated. Means for grouping all areas in one field screen so as to be in the same group, and, when there are a plurality of areas spatially separated from each other in the same group, these areas are each assigned to a different group. The apparatus for converting a two-dimensional image into a three-dimensional image according to claim 1, further comprising: means for performing grouping. 4. The image processing apparatus according to claim 1, wherein, based on a frequency distribution indicating the number of parallax calculation regions with respect to the magnitude of the image feature amount related to the perspective of the video, an area in which the size of the image feature amount related to the perspective of the video is approximated. Means for grouping all areas in one field screen so as to be in the same group. If there are a plurality of areas spatially separated from each other in the same group, these areas are respectively different groups As described above, when there is a group configured by the grouping and a parallax calculation area equal to or less than a predetermined number, the image feature amount related to the perspective of the video with respect to the parallax calculation areas in and around the group is determined. Based on whether the group should belong to the surrounding group and determine that the group should belong to the surrounding group. Case, device to convert the group means that belong to the group of surrounding the two-dimensional image according to the 3D image to claim 1, further comprising a. 5. The image processing apparatus according to claim 1, wherein, based on a frequency distribution indicating the number of parallax calculation regions with respect to the magnitude of the image feature amount related to the perspective of the video, an area where the size of the image feature amount related to the perspective of the video is approximated. Means for grouping all areas in one field screen so as to be in the same group. If there are a plurality of areas spatially separated from each other in the same group, these areas are respectively different groups In the case where there is a group composed of a predetermined number or less of parallax calculation areas, a grouping method is performed based on the image feature amount related to the perspective of the video with respect to the parallax calculation areas in and around the group. To determine whether the group should belong to the surrounding group and determine that the group should belong to the surrounding group Means for making the group belong to a surrounding group, and, of two adjacent groups, two groups based on image feature amounts relating to perspective of a video with respect to a parallax calculation region in one group and the other group. Is to be combined or not, and if it is determined that both groups should be combined,
The apparatus for converting a 2D image into a 3D image according to claim 1, further comprising: means for combining the two groups. 6. The image processing apparatus according to claim 1, wherein the second means is configured to calculate the perspective of the video for each group based on an image feature amount relating to the perspective of the video for each parallax calculation area in each group and a weight coefficient preset for each parallax calculation area. The apparatus for converting a two-dimensional image into a three-dimensional image according to any one of claims 1, 2, 3, 4, and 5, wherein the device calculates information relating to the three-dimensional image. 7. The parallax calculation area of the parallax calculation areas of the parallax calculation areas below the height position where the perspective position represented by the information regarding the perspective of the video is lower than the height position of the screen among the height positions of the screen For the parallax calculation area in which the perspective position represented by the information regarding the perspective of the image with respect to the parallax calculation area immediately above the parallax calculation area is a position that is more than a predetermined value from the perspective position represented by the information regarding the perspective of the image with respect to the parallax calculation area immediately above the parallax calculation area, Is corrected so that the perspective position represented by the information regarding the perspective of the image with respect to the image approaches the perspective position represented by the information regarding the perspective of the image immediately above the parallax calculation area. Claims 1 and 2, comprising means.
The two-dimensional image described in any one of 3, 4, 5, and 6 is
A device that converts to two-dimensional video. 8. A parallax calculation area of a parallax calculation area of a parallax calculation area below a height position where a perspective position represented by information on perspective of an image is lower than a height position of the screen among the height positions of the screen. For the parallax calculation area in which the perspective position represented by the information regarding the perspective of the image with respect to the parallax calculation area immediately above the parallax calculation area is a position that is more than a predetermined value from the perspective position represented by the information regarding the perspective of the image with respect to the parallax calculation area immediately above the parallax calculation area, Is corrected so that the perspective position represented by the information regarding the perspective of the image with respect to the image approaches the perspective position represented by the information regarding the perspective of the image immediately above the parallax calculation area. Means and information on the perspective of the video at the boundary between two adjacent groups 7. A means for correcting information relating to perspective of an image with respect to a parallax calculation area at a boundary between two adjacent groups so that For converting 2D images into 3D images. 9. The parallax calculation area of the parallax calculation areas of the parallax calculation areas below the height position where the perspective position represented by the information regarding the perspective of the video is lower than the height position of the screen among the height positions of the screen For the parallax calculation area in which the perspective position represented by the information regarding the perspective of the image with respect to the parallax calculation area immediately above the parallax calculation area is a position that is more than a predetermined value from the perspective position represented by the information regarding the perspective of the image with respect to the parallax calculation area immediately above it Is corrected so that the perspective position represented by the information regarding the perspective of the image with respect to the image approaches the perspective position represented by the information regarding the perspective of the image immediately above the parallax calculation area. Means, at the boundary between two adjacent groups, information about the perspective of the image is within a predetermined range between the two groups. As described above, the means for correcting the information regarding the perspective of the video with respect to the parallax calculation region at the boundary between two adjacent groups, and the difference between the information regarding the perspective of the video between the respective parallax calculation regions within the same group is within a predetermined range. Means for smoothing information about the perspective of the video in each group, so that the two-dimensional video according to any one of claims 1, 2, 3, 4, 5, and 6 is converted into a three-dimensional video. The device to convert. 10. A first storage means having a capacity capable of storing a two-dimensional input video signal for a plurality of pixels equal to or less than one horizontal line, and temporarily storing the two-dimensional input video signal. A second storage unit having a capacity capable of storing a two-dimensional input video signal for a plurality of pixels equal to or less than one horizontal line, and temporarily storing the two-dimensional input video signal; a read address of the first storage unit Is controlled based on disparity information corresponding to a predetermined unit area to which the horizontal and vertical positions of the two-dimensional input video signal belong with respect to a standard read address determined according to the horizontal and vertical positions of the two-dimensional input video signal. First read address control means for generating a first video signal having a horizontal phase advanced by an amount corresponding to the parallax information with respect to a reference horizontal phase defined by the standard read address, And controlling the read address of the second storage means with respect to the standard read address based on parallax information corresponding to a predetermined unit area to which the horizontal and vertical positions of the two-dimensional input video signal belong. 2. A second read address control means for generating a second video signal whose horizontal phase is delayed by an amount corresponding to the parallax information with respect to a reference horizontal phase defined by: An apparatus for converting a 2D image according to any one of 4, 5, 6, 7, 8 and 9 into a 3D image. 11. An image feature amount relating to perspective of an image is any one or any selected from an integrated value of a high-frequency component, a luminance contrast, an integrated value of an RY component, and an integrated value of a BY component. Claims 1, 2, 3,
An apparatus for converting a 2D image according to any one of 4, 5, 6, 7, 8, 9 and 10 into a 3D image. 12. The two-dimensional image according to any one of claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 and 11, wherein the predetermined unit area is an area of one pixel unit. A device that converts to two-dimensional video.