JP3005474B2 - Apparatus and method for converting 2D image to 3D image - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an apparatus and a method for converting into a two-dimensional image.

[0002]

2. Description of the Related Art As a method of converting a two-dimensional video into a three-dimensional video, a video signal which is temporally delayed from an original two-dimensional video signal using a field memory (hereinafter referred to as a delayed video signal). And outputs one of the original two-dimensional video signal and the delayed video signal as a left-eye video signal,
A method of outputting the other as a right-eye video signal is known. However, this method has a problem that the cost is high because a field memory is required to generate a video signal delayed in time with respect to the original two-dimensional video signal. Further, according to this method, only a moving two-dimensional image can be converted into a three-dimensional image.

[0003]

SUMMARY OF THE INVENTION The present invention eliminates the need for a field memory for generating a video signal that is temporally delayed from the original two-dimensional video signal, thereby reducing the cost of a two-dimensional video signal. It is an object of the present invention to provide an apparatus and a method for converting an image into a three-dimensional image.

Another object of the present invention is to provide an apparatus and a method for converting a two-dimensional video into a three-dimensional video, whereby a stereoscopic video can be obtained even if the video represented by the original two-dimensional video signal is a still video. With the goal.

[0005]

An apparatus for converting a two-dimensional video into a three-dimensional video according to the present invention sets a plurality of parallax calculation areas in advance in each field screen of a two-dimensional video signal, and sets the plurality of parallax calculation areas in advance. A feature extraction unit for extracting a feature of an image from a two-dimensional video signal in each disparity calculation region, and disparity information for generating disparity information for each disparity calculation region based on the feature of the image extracted by the feature extraction unit Generating means; 1
For each pixel, the parallax calculation area including the pixel or
A unit disparity information generating unit configured to generate unit disparity information from the disparity information of the disparity calculation region adjacent to the disparity calculation region including the pixel; and a three-dimensional unit based on the unit disparity information generated by the unit disparity generation information unit. Video signal generating means for generating a first video signal and a second video signal having horizontal parallax for video from the two-dimensional video signal.

Further, the parallax information generating means includes a hand <br/> stage that generates a distance information of the parallax calculation for each region from the feature of the image, of the height position of the screen, represented by the distance information among the parallax calculation regions of lower than distance position closest height position, perspective position represented by the distance information for the parallax calculation region, it expresses by the distance information of the parallax calculation region immediately thereabove the far-near disparity calculation areas is farther than a predetermined value from the position,
Means for correcting the perspective information for the parallax calculation area, so as to approach the perspective position represented by the perspective information for the parallax calculation area immediately above, and the perspective information for each corrected parallax calculation area, Means for converting into parallax information for each parallax calculation area.

A plurality of parallax calculation areas are set in advance in each field screen of the two-dimensional video signal, and image features are extracted from the two-dimensional video signal in each parallax calculation area for each of the parallax calculation areas. One step, a second step of generating disparity information for each disparity calculation area based on the features of the image extracted in the first step, and, for each pixel, the pixel
The parallax calculation area or its pixel is included
A third step of generating unit disparity information from disparity information of the disparity calculation area close to the disparity calculation area;
A fourth step of generating a first video signal and a second video signal having a horizontal parallax for a three-dimensional video from the two-dimensional video signal based on the unit parallax information generated in the step. .

The second step is a step of generating perspective information for each of the parallax calculation areas from the features of the image, and the perspective position represented by the perspective information among the height positions of the screen is the closest height. is among the parallax calculation regions of the lower side of the position, the distance position represented by the distance information for the parallax calculation region, more than a predetermined value from the far-near position that is represented by the distance information of the parallax calculation region immediately thereabove For the parallax calculation area that is a distant position,
So as to approach the perspective position represented by the distance information of the parallax calculation region immediately thereabove, and correcting the previous SL perspective information, the distance information for each parallax calculation for each region of the corrected parallax calculation region Converting the disparity information into each disparity information.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a 2D / 3D video converter for converting a 2D video into a 3D video.

A luminance signal Y, a color difference signal RY, and a color difference signal BY constituting a two-dimensional video signal are supplied to an AD conversion circuit 1.
(ADC), the digital Y signal, R-
It is converted into a Y signal and a BY signal.

The Y signal is sent to a luminance integrating circuit 7, a high-frequency component integrating circuit 8, and a luminance contrast calculating circuit 9, and is sent to a first left image arbitrary pixel delay FIFO 11 and a first right image arbitrary pixel delay FIFO 21. Sent. Note that the luminance integrating circuit 7, the high-frequency component integrating circuit 8, and the luminance contrast calculating circuit 9 correspond to the feature extracting means of the present invention.

The RY signal is sent to a saturation accumulator 10 and a second left image arbitrary pixel delay FIFO 12
And the second right image arbitrary pixel delay FIFO 22. The BY signal is sent to the saturation integration circuit 10 and sent to the third left image arbitrary pixel delay FIFO 13 and the third right image arbitrary pixel delay FIFO 23.

The luminance integrating circuit 7 calculates, for each field, a luminance integrated value for each of a plurality of parallax calculation areas E1 to E12 set in advance in one field screen as shown in FIG. The high-frequency component integrating circuit 8 calculates an integrated value of a high-frequency component for each of the parallax calculation areas E1 to E12 for each field. The brightness contrast calculation circuit 9 calculates each parallax calculation area E1 for each field.
The brightness contrast for each of E12 to E12 is calculated. The saturation integration circuit 10 calculates an integrated value of saturation for each of the parallax calculation areas E1 to E12 for each field.

The luminance integrated value for each of the parallax calculation areas E1 to E12, the integrated value of the high frequency component for each of the parallax calculation areas E1 to E12, and the respective parallax calculation areas E1 to E1
The luminance contrast for each of the two and the integrated value of the saturation for each of the parallax calculation regions E1 to E12 are features of the image related to the perspective of the video in each of the parallax calculation regions E1 to E12.

Note that a total of 60 parallax calculation areas of 6 rows and 10 columns are actually set in the one-field screen as shown in FIG. 15, but for convenience of explanation, as shown in FIG. It is assumed that a total of 12 parallax calculation areas E1 to E12 of 3 rows and 4 columns are set in one field screen.

The CPU 3 generates parallax information for each of the parallax calculation areas E1 to E12 based on the information sent from the brightness integration circuit 7, the high frequency component integration circuit 8, the brightness contrast calculation circuit 9 and the saturation integration circuit 10. I do. CP
U3 corresponds to the parallax information generating means of the present invention. In this example, the parallax information is generated such that the front-side object such as the subject has a smaller parallax amount, and the back-side object such as the background has a larger parallax amount. The details of the method of generating the parallax information will be described later.

The parallax information for each of the parallax calculation areas E1 to E12 calculated by the CPU 3 is sent to the parallax control circuit 4. The parallax control circuit 4 controls the parallax calculation areas E1 to E
Based on the disparity information for No. 12, disparity information for each pixel position in each field is generated. The parallax control circuit 3 corresponds to a unit parallax information generating unit of the present invention. Then, based on the obtained parallax information for each pixel position, each FIFO
Video signals (Y signal, RY
Signal, BY signal), the read address is shifted between the left image arbitrary pixel delay FIFOs 11 to 13 and the right image arbitrary pixel delay FIFOs 21 to 23,
The read addresses of the FIFOs 11 to 13 and 21 to 23 are controlled. Therefore, the arbitrary pixel delay FIF for the left image
The horizontal phase of the left video signal read from O11 to O13 and the horizontal phase of the right video signal read from the right video arbitrary pixel delay FIFOs 21 to 23 become different.

Arbitrary pixel delay FIFO 11-13 for left image
From the left video signal (YL signal, (RY) L
Signal, (BY) L signal) is a DA conversion circuit (DAC)
After being converted into an analog signal by 5, it is sent to a three-dimensional display device (not shown). Arbitrary pixel delay FIFO for right image
Right video signal (YR signal,
The (RY) R signal and the (BY) R signal are converted into analog signals by a DA conversion circuit (DAC) 6,
It is sent to a three-dimensional display device (not shown).

Since the horizontal phase of the left video signal is different from the horizontal phase of the right video signal, a parallax occurs between the left video and the right video. As a result, the left image is observed only with the left eye,
When the right image is observed only with the right eye, a three-dimensional image in which the subject is located in front of the background is obtained.

FIG. 3 shows the configuration of the luminance integrating circuit 7.

In FIG. 2, each of the parallax calculation areas E1 to E
12, the number of pixels in the horizontal direction is m, and each of the parallax calculation areas E1 to E
12, the number of pixels in the vertical direction is n, and the first parallax calculation area E1
The horizontal position (HAD), where the coordinates of the upper left of
And the vertical position (VAD).

The luminance integrating circuit 7 includes a timing signal generating circuit 201, an adding circuit 202, and a luminance integrating register group 2.
03 and a selection circuit (SEL) 204. The luminance integration register group 203 stores the parallax calculation areas E1 to E1.
2 are provided with first to twelfth luminance integrating registers 211 to 222 respectively corresponding to the two.

The timing signal generating circuit 201 receives a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync of an input video signal and a clock signal CLK for detecting a horizontal address in each horizontal period.

The timing signal generation circuit 201 outputs first to twelfth enable signals EN1 to EN12, a reset signal RST, and an output timing signal DOUT based on the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the clock signal CLK. .

Each of the enable signals EN1 to EN12 corresponds to each of the parallax calculation areas E1 to E12, and is always at the L level. When the horizontal and vertical positions of the input video signal are within the corresponding areas, the enable signals EN1 to EN12 are set to the H level. Level. The first to twelfth enable signals EN1 to EN12 are input as write signals to the first to twelfth luminance integration registers 211 to 222, respectively. Further, the first to twelfth enable signals EN1 to EN12 are also sent to the selection circuit 204. The selection circuit 204 selects and outputs input data corresponding to the H-level enable signal.

The reset signal RST is output at the effective video start timing of each field in the input video signal, and is sent to each of the luminance integration registers 211 to 222. A reset signal RST is sent to each of the brightness integration registers 211 to 222.
Is input, the content is set to 0.

As shown in FIG. 2, the output timing signal DOUT is at the H level for a certain period from the time when the vertical position of the input video signal exceeds the vertical position at the lower end of the lowermost parallax calculation area E12. Output timing signal DOUT
Is sent to the CPU 3.

A reset signal is output at the effective video start timing of the input video signal,
The contents of 11 to 222 are set to 0. When the horizontal / vertical position of the input video signal is within the first parallax calculation area E1,
Since the first enable signal EN1 is at the H level, the luminance value held in the first luminance integration register 211 is sent to the addition circuit 202 via the selection circuit 204, and the Y signal in the input video signal is added. Input to the circuit 202.

Therefore, the first luminance integrating register 21
1 and the Y value in the input video signal.
The signal and the signal are added by the adding circuit 202, and the result of the addition is stored in the first luminance integration register 211. That is, when the horizontal and vertical positions of the input video signal are within the first parallax calculation area E1, the first parallax calculation area E1
The luminance values of the pixels within are accumulated, and the accumulation result is accumulated in the first luminance accumulation register 211.

In this manner, the parallax calculation areas E1 to E
The brightness integration value for each of the 12 is stored in the corresponding brightness integration register 2
11 to 222. When the output timing signal DOUT becomes H level, each of the brightness integration registers 2
Each of the parallax calculation areas E1 to E stored in 11 to 222
The integrated luminance value for each of the CPUs 12 is sent to the data bus (DA
TA-BUS).

FIG. 4 shows the configuration of the high frequency component integrating circuit 8.

The high frequency component integrating circuit 8 includes a timing signal generating circuit 231, a high-pass filter (HPF) 232,
An absolute value conversion circuit 233, a slice processing circuit 234, an addition circuit 235, a high frequency component integration register group 236, and a selection circuit 237 are provided. The high-frequency component accumulation register group 236 includes first to twelfth high-frequency component accumulation registers 241 to 241 corresponding to the parallax calculation areas E1 to E12, respectively.
252.

The input signal and the output signal of the timing signal generation circuit 231 correspond to the timing signal generation circuit 20 shown in FIG.
1 is the same as the input signal and the output signal.

As the high-pass filter 232, for example, as shown in FIG.
A high-pass filter having tap coefficients of −1, 0, 2, 0 and −1 including a bit shift circuit 266 for obtaining an output twice as large as the input value, an adder 267 and a subtractor 268 is used. Can be

The slice processing circuit 234 includes
A circuit having input / output characteristics as shown in FIG. 6 is used. The output is set to 0 for inputs from 0 to Ia in order to prevent noise from being extracted as a high-frequency component.

Therefore, the high-frequency component of the Y signal in the input video signal is extracted by the high-pass filter 232, the absolute value thereof is obtained by the absolute value conversion circuit 233, and the slice processing circuit 234 removes noise from the absolute value of the high-frequency component. You.

A reset signal is output at the effective video start timing of the input video signal, and the contents of each of the high frequency component integration registers 241 to 252 are set to 0. When the horizontal / vertical position of the input video signal is within the first parallax calculation area E1, the first enable signal EN1 is at the H level, so that the high-frequency component held in the first high-frequency component integration register 241 is stored. Is added through the selection circuit 237 to the addition circuit 23.
5 and the high frequency component of the Y signal in the input video signal (the output of the slice processing circuit 234) is input to the addition circuit 235.

Therefore, the high-frequency component held in the first high-frequency component integration register 241 and the high-frequency component of the Y signal in the input video signal are added by the addition circuit 235, and the addition result is added to the first high-frequency component integration. It is stored in the register 241. That is, when the horizontal and vertical positions of the input video signal are within the first parallax calculation area E1, the high-frequency components of the pixels in the first parallax calculation area E1 are integrated, and the integration result is the first. It is stored in the high frequency component integration register 241.

In this manner, the parallax calculation areas E1 to E
The integrated value of the high frequency component for each 12 is stored in the corresponding high frequency component integration register 241. When the output timing signal DOUT becomes H level, the integrated value of the high frequency component for each of the parallax calculation areas E1 to E12 stored in each of the high frequency component integration registers 241 to 252 is determined by the CPU.
3 via the data bus.

FIG. 7 shows another example of the high-frequency component integrating circuit 8.

The high frequency component integrating circuit 8 includes a timing signal generating circuit 238, a high pass filter 232, a peak detecting circuit 239, an adding circuit 235, a high frequency component integrating register group 236, and a selecting circuit 237.

The timing signal generation circuit 238 is almost the same as the timing signal generation circuit 201 of FIG. 3, but as shown in FIG. 2, the horizontal position of the input video signal is set immediately before the parallax calculation areas E1, E5, E9. 3 is different from the timing signal generating circuit 201 in FIG. 3 in that a trigger pulse (region boundary signal RST1) is output when the horizontal position of the image and the horizontal position at the end of each of the parallax calculation regions E1 to E12 are reached. . The region boundary signal RST1 is supplied to the peak detection circuit 23
9

The high frequency component of the Y signal extracted by the high pass filter 232 is sent to a peak detection circuit 239. The peak detection circuit 239 controls each of the parallax calculation areas E1 to E1.
The maximum value of the high frequency component is detected for each horizontal line in E12. As shown in FIG. 8, a peak detection circuit 239 having a comparison circuit 271, a maximum value register 272, and a gate 273 is used. FIG. 9 shows a horizontal synchronization signal Hsync of an input video signal and an area boundary signal RS.
The output of T1, the gate 273, etc. is shown.

The maximum value register 272 includes a high-frequency component of the Y signal extracted by the high-pass filter 232, an area boundary signal RST 1, and a determination result signal L of the comparison circuit 271.
a and the clock signal CLK are input. Comparison circuit 2
71 compares the output of the maximum value register 272 with the high frequency component of the Y signal in the input video signal, and when the high frequency component of the Y signal is larger than the output of the maximum value register 272,
The determination result signal La is set to the H level.

When the region boundary signal RST1 goes high, the contents of the maximum value register 272 are set to zero. If the determination result signal L1 from the comparison circuit 271 is at the H level while the region boundary signal RST1 is at the L level,
The high frequency component of the Y signal is stored in the maximum value register 272. That is, the contents of the maximum value register 272 are updated. Therefore, the maximum value register 272 stores the parallax calculation areas E1 to E12 corresponding to the horizontal and vertical positions of the input video signal every time the area boundary signal RST1 is at the L level.
The maximum value of the high frequency components of the Y signal for each pixel of one horizontal line is stored.

Gate 273 outputs the output value of maximum value register 272 when region boundary signal RST1 attains H level, and outputs 0 when region boundary signal RST1 is at L level. That is, every time the region boundary signal RST1 becomes H level, the gate circuit 273 outputs the predetermined parallax calculation regions E1 to E1 stored in the maximum value register 272.
The maximum value of the high frequency component of the Y signal for one horizontal line in 2 is output. Therefore, the integrated value of the maximum value of the high frequency component of the Y signal for each horizontal line in the corresponding parallax calculation area is accumulated in each of the high frequency component integration registers 241 to 252 (see FIG. 7).

FIG. 10 shows the configuration of the luminance contrast calculation circuit 9.

The luminance contrast calculation circuit 9 includes a timing signal generation circuit 301 and a luminance contrast detection circuit group 302. Brightness / contrast detection circuit group 3
02 denotes first to twelfth luminance contrast detection circuits 311 to 311 corresponding to the parallax calculation areas E1 to E12, respectively.
22.

The input signal and the output signal of the timing signal generation circuit 301 correspond to the timing signal generation circuit 20 shown in FIG.
1 is the same as the input signal and the output signal.

Each of the luminance contrast detection circuits 311 to 32
2, includes a first comparison circuit 331, a maximum value register 332, a second comparison circuit 333, a minimum value register 334, and a subtractor 335, as shown in FIG.

The maximum value register 332 stores the Y signal in the input video signal and the enable signal EN (N = 1, N = 1, E2) in the areas E1 to E12 corresponding to the luminance contrast detection circuit.
2... 12), reset signal RST, first comparison circuit 33
1 and the clock signal CL
K is input. The first comparison circuit 331 compares the output value of the maximum value register 332 with the Y signal of the input video signal, and when the Y signal of the input video signal is larger than the output value of the maximum value register 332, sets the determination signal Lb to H. To level.

When the reset signal RST goes high,
The contents of the maximum value register 332 are set to 0. The enable signals EN of the areas E1 to E12 corresponding to the luminance contrast detection circuit are at the H level and the determination signal Lb is at the H level.
When the signal is at the level, the Y signal is stored in the maximum value register 332. That is, the contents of the maximum value register 332 are updated. Therefore, immediately before the output timing signal DOUT is output, the maximum value register 332 stores the parallax calculation area E corresponding to the luminance contrast detection circuit.
The maximum value of the luminance values of the pixels in 1 to E12 is accumulated.

The minimum value register 334 stores the Y signal of the input video signal and the enable signal EN (N = 1, N = 1, E2) in the areas E1 to E12 corresponding to the luminance contrast detection circuit.
2... 12), reset signal RST, second comparison circuit 33
3 and the clock signal CL output from
K is input. The second comparison circuit 334 compares the output value of the minimum value register 334 with the Y signal of the input video signal, and when the Y signal of the input video signal is smaller than the output value of the minimum value register 334, sets the determination signal Lc to H. To level.

When the reset signal RST goes high,
A predetermined maximum value is set in the minimum value register 334. When the enable signals EN of the areas E1 to E12 corresponding to the luminance contrast detection circuit are at the H level and the determination signal Lc is at the H level, the Y signal is stored in the minimum value register 334. That is, the minimum value register 3
34 is updated. Therefore, immediately before the output timing signal DOUT is output, the minimum value of the luminance values of the pixels in the parallax calculation areas E1 to E12 corresponding to the luminance contrast detection circuit is accumulated in the minimum value register 334. You.

As a result, at the point in time when the output timing signal DOUT is output, the output of the subtractor 335 is the difference between the maximum value and the minimum value of the luminance values of the pixels in the corresponding parallax calculation areas E1 to E12. The value corresponds to the difference (luminance contrast). Then, the output timing signal DOUT
Is output, the output (luminance contrast) of the subtractor 335 is sent to the CPU 3.

FIG. 12 shows the structure of the saturation accumulating circuit 10.

The saturation integration circuit 10 includes a timing signal generation circuit 341, a saturation calculation circuit 342, an addition circuit 343, a saturation integration register group 344, and a selection circuit 345. The saturation integration register group 344 stores the parallax calculation areas E
There are first to twelfth saturation integration registers 351 to 362 corresponding to 1 to E12, respectively.

The input signal and the output signal of the timing signal generation circuit 341 are the same as those of the timing signal generation circuit 20 shown in FIG.
1 is the same as the input signal and the output signal.

The saturation calculating circuit 342 sets the value of the RY signal in the input video signal to (RY) and the value of the BY signal in the input video signal to (BY), and calculates the following equation (1).
To obtain the value SAI corresponding to the saturation.

[0061]

(Equation 1) A reset signal RST is output at the effective video start timing in the input video signal, and the saturation integration registers 351 to 351 are output.
The content of 362 is set to 0. When the horizontal / vertical position of the input video signal is within the first parallax calculation area E1, the first enable signal EN1 is at the H level, and thus the saturation held in the first saturation integration register 351 is stored. Is sent to the addition circuit 343 via the selection circuit 345, and the saturation calculated by the saturation calculation circuit 342 is added to the addition circuit 3.
Input to 43.

Therefore, the first saturation integration register 35
The saturation held at 1 and the saturation calculated by the saturation calculation circuit 342 are added by the addition circuit 343, and the addition result is stored in the first saturation integration register 351. That is, the horizontal and vertical positions of the input video signal
Is within the parallax calculation area E1, the saturation of the pixels in the first parallax calculation area E1 is accumulated, and the accumulation result is accumulated in the first saturation accumulation register 351.

In this way, the parallax calculation areas E1 to E
The integrated value of the saturation for each 12 is stored in the corresponding saturation integration registers 351 to 362. When the output timing signal DOUT becomes H level, the parallax calculation areas E1 to E1 stored in the saturation integration registers 351 to 362 are stored.
The integrated value of the saturation for each E12 is sent to the CPU 3 via the data bus.

FIG. 13 shows a method of calculating the amount of parallax performed by the CPU 3.

The first normalizing means 401 normalizes the integrated value of the high-frequency component for each of the parallax calculation areas E1 to E12 to a value in the range of 0 to 10. The second normalization unit 402 sets the luminance contrast of each of the parallax calculation areas E1 to E12 to 0.
Normalize to a value in the range of -10. Third normalizing means 40
3 normalizes the integrated luminance value for each of the parallax calculation areas E1 to E12 to a value in the range of 0 to 10. Fourth normalizing means 4
A step 04 normalizes the saturation integration value for each of the parallax calculation areas E1 to E12 to a value in a range of 0 to 10.

Each of the normalized parallax calculation areas E1 to E12
The integrated value of the high-frequency component for each is multiplied by the coefficient K1 by the multiplying unit 405 and then sent to the adding unit 409. The normalized luminance contrast for each of the parallax calculation areas E1 to E12 is added to the coefficient K2 by the multiplication unit 406.
Are accumulated and sent to the adding means 409. After the coefficient K3 is multiplied by the multiplication means 407 to the normalized luminance integrated value for each of the parallax calculation areas E1 to E12,
It is sent to the adding means 409. The normalized saturation integrated value for each of the parallax calculation areas E1 to E12 is multiplied by a multiplication unit 408.
After the coefficient K4 is integrated by the above, it is sent to the adding means 409.

As specific examples of the coefficients K1, K2, K3, K4, K1 = 0.6, K2 = 0.2, K3 = 0.1, K3
4 = 0.1. Also, K1 = 0.75, K2
= 0.25, K3 = 0.0, K4 = 0.0.

By controlling the set values of these coefficients K1 to K4, any one or any combination selected from the integrated value of the high-frequency component, the luminance contrast, the luminance integrated value and the chroma integrated value can be determined. , Can be used as an image feature amount related to the perspective of a video.

Therefore, only the integrated value of the high-frequency component can be used as the image feature amount relating to the perspective of the video. It is also possible to use only the luminance contrast as the image feature amount relating to the perspective of the video. The integrated value of the high-frequency component and the luminance contrast may be used as the image feature amount relating to the perspective of the video. An integrated value of a high-frequency component, a luminance contrast, and a luminance integrated value can also be used as the image feature amount relating to the perspective of a video. The integrated value of the high-frequency component, the luminance contrast, and the integrated value of the saturation can also be used as the image feature amount related to the perspective of the video.
The integrated value of the high-frequency component, the luminance contrast, the integrated luminance value, and the integrated chroma value can also be used as the image feature amount relating to the perspective of the video.

In the adding means 409, each of the multiplying means 405
The values for each of the parallax calculation areas E1 to E12 obtained by 408 are added. The value for each of the parallax calculation areas E1 to E12 obtained by the adding unit 409 is normalized by the fifth normalizing unit 410 to a value in the range of 0 to 10 (hereinafter, referred to as depth information). FIG.
9 shows the relationship between the output value of the value 09 and the depth information obtained by the fifth normalization means 410. Each parallax calculation area E
Depth information for each of E1 to E12 is used as a parallax calculation area E1 to E12.
This is information on the distance of the video for each of the twelve. Each of the parallax calculation areas E1 to E5 obtained by the fifth normalization unit 410
The depth information for each E12 is sent to the depth correction unit 411.

In a general image, the subject exists in the front and the background exists in the rear. Also, since there are many images that are in focus with respect to the subject, it is considered that the closer the object is, the higher the high-frequency component, contrast, brightness, and saturation are. Therefore, in the present embodiment, it is assumed that an object in front of an area where the integrated value of the high-frequency component, the luminance contrast, the integrated value of the luminance, and the integrated value of the saturation are larger is captured.

Therefore, it is possible to determine that the region where the depth information obtained by the adding means 409 is larger is the region where the object existing ahead is captured. When the stereoscopic position of the region in which the object present in the forefront is captured is set as the tube position of the stereoscopic display device, the depth information obtained by the adding unit 409 is inversely proportional to the depth from the tube position.

Hereinafter, the depth correction processing by the depth correction means 411 will be described.

It is easier to understand the depth correction process by taking the actually set parallax calculation area as an example, and therefore, the 60 parallax calculation areas actually set for one field are explained. The depth correction processing by the depth correction unit 411 will be described. FIG.
Indicates 60 parallax calculation areas F1 to F60 actually set for one field.

First, an average value of depth information is calculated for each row of the parallax calculation areas F1 to F60. When the depth information for each of the parallax calculation areas F1 to F60 has a value as shown in FIG. 16, the average value of the depth information for each of the first to sixth rows is 1.2, 3.6, 6.0, 7.2, 4.
0 and 1.2.

Next, from each row of the parallax calculation area, an area where many objects at the near position are reflected is extracted. That is,
The row having the largest average value of the depth information is extracted. FIG.
In the example of No. 6, the area of the fourth row is extracted.

Next, with respect to each area of the row below the extracted row, each area of the row below the extracted row is compared with the area immediately above so that the depth information does not suddenly decrease. Is adjusted. In particular,
For an area in which the depth information of each area in the row below the extracted row is smaller than the area immediately above by 3 or more, the depth information of the area is set to a value smaller by 2 than the depth information of the area immediately above. Can be changed.

In the example of FIG. 16, as shown in FIG. 17, among the regions F41 to F50 in the fifth row, the regions F42 to F49 whose depth information is smaller than the depth information of the region immediately above by three or more. , The depth information is corrected.
Thereafter, the depth information is corrected for the regions F53 to F58 of the regions F51 to F60 in the sixth row whose depth information is smaller than the depth information (corrected depth information) of the region immediately above by three or more. Is done.

That is, if the relationship of the depth information to the height of the screen at an arbitrary horizontal position is a relationship as shown by a curve U1 in FIG. 18, the relationship of the depth information to the height of the screen is corrected by the depth correction. However, FIG.
The correction is made so as to have the relationship shown in FIG.

As described above, of each row of the parallax calculation area,
The reason that the depth information of the area below the area where many objects at the near position are reflected is corrected for the following reason.

In general, an object existing in front is often displayed on the lower side of the screen. Further, the object reflected on the lower side of the screen is often an image with little change such as the ground. An image with little change, such as the ground, has a low high-frequency component, so that the value of the depth information is small even though it is ahead. Therefore, depth information is increased by depth correction so that the depth information of an image located in front of the object and having a low high-frequency component is not larger than the value of the depth information of the area immediately above the image.

Depth information for each area (actually, F1 to F60 but E1 to E12 for convenience of explanation) whose depth information has been corrected by the depth correction means 411 is as follows.
The renormalization means 412 normalizes the data within the range of 0 to 10. The depth information for each of the areas E1 to E12 obtained by the re-normalization means 412 is
13 is converted into parallax information for each of the regions E1 to E12.

The parallax information determining means 413 converts the depth information into parallax information for each of the regions E1 to E12 based on the relationship between the predetermined depth information and the parallax information. The relationship between depth information and disparity information is shown in FIG.
Are inversely proportional as shown by the straight line S1 or S2.

In FIG. 19, the relationship between the depth information indicated by the straight line S1 and the parallax information is used when it is desired to obtain a stereoscopic image having a relatively strong stereoscopic effect. The relationship between the depth information indicated by the straight line S2 and the parallax information is used when it is desired to obtain a stereoscopic image having a relatively weak stereoscopic effect. The relationship between the depth information and the parallax information is represented by a straight line S1 and a straight line S2.
It is possible to adjust the three-dimensional effect by adjusting between.

Each of the regions E1 to E1 thus obtained
The disparity information for each of the two is sent to the disparity control circuit 4 (see FIG. 1). Note that the depth correction by the depth correction unit 411 may be omitted.

FIG. 20 mainly shows the configuration of the parallax control circuit and the arbitrary pixel delay FIFO shown in FIG.

FIG. 20 shows an arbitrary pixel delay FIFO 11 to 11.
13, 21 to 23, left image arbitrary pixel delay FIFO 11 and right image arbitrary pixel delay FI for Y signal
Although only FO21 is shown, other arbitrary pixel delays FI
FO12, 13, 22, and 23 have the same configuration and perform the same control, so that other arbitrary pixel delay FIFOs
Descriptions of the configurations and control methods of 12, 13, 22, and 23 are omitted.

The disparity information calculated by the CPU 3 is disparity information for the center position of each of the disparity calculation areas E1 to E12. The parallax control circuit 4 obtains parallax information for each pixel position on a one-field screen based on the parallax information for the center position of each of the parallax calculation areas E1 to E12. Then, in order to generate a left image and a right image having parallax corresponding to the parallax information for the pixel position from the two-dimensional video signal for each pixel position, an arbitrary left video image is generated based on the parallax information for each pixel position. Pixel delay F
IFO 11-13 and right pixel arbitrary pixel delay FIFO
The read addresses 21 to 23 are controlled.

The parallax information for each pixel position on the one-field screen is obtained from a timing signal generation circuit 51, a parallax interpolation coefficient generation circuit 52, a parallax information storage means 60, and a parallax selection circuit 8.
0, and is generated by the first to fourth multipliers 81 to 84 and the addition circuit 85.

The horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync of the input video signal are input to the timing signal generating circuit 51. Further, a clock signal CLK for detecting a horizontal address in each horizontal period is also input to the timing signal generation circuit 51.

The timing signal generating circuit 51 generates a horizontal address signal HAD indicating an absolute horizontal position of an input video signal, an absolute vertical position of the input video signal based on the horizontal synchronizing signal Hsync, the vertical synchronizing signal Vsync and the clock signal CLK. And a relative horizontal position signal HPOS representing the relative horizontal position of the input video signal.
And a relative vertical position signal VPOS indicating the relative vertical position of the input video signal is generated and output.

The relative horizontal position and the relative vertical position of the input video signal will be described.

As shown in FIG. 21, the parallax calculation areas E1 to E12 in FIG. 2 are set as follows. As shown by the dotted line in FIG. 21, the entire screen is divided into 20 regions of 4 rows and 5 columns (hereinafter, referred to as first divided regions). Then, a quadrangular region having four vertices at the center of the first divided region at the upper left end, the center of the first divided region at the upper right end, the center of the first divided region at the lower left end, and the center of the first divided region at the lower right end is 3 Row 4
The column is divided into 12 regions (hereinafter, referred to as second divided regions), and each of the second divided regions is set as parallax calculation regions E1 to E12.

The number of pixels in the horizontal direction of the first divided region and the second divided region is represented by m, and the number of pixels of the first divided region and the second divided region in the vertical direction is represented by n. The relative horizontal position of the input video signal is represented by 0 to (m-1), with the left end of each first divided area being 0 and the right end being m.
The relative vertical position of the input video signal is represented by 0 to (n-1), with the upper end of each first divided area being 0 and the lower end being n.

The relative horizontal position signal HPO of the input video signal
S and the relative vertical position VPOS are sent to the parallax interpolation coefficient generation circuit 52. The parallax interpolation coefficient generation circuit 52 generates a first parallax interpolation coefficient KUL based on the relative horizontal position signal HPOS, the relative vertical position VPOS, and the following equation (2).
A second parallax interpolation coefficient KUR, a third parallax interpolation coefficient KDL, and a fourth parallax interpolation coefficient KDR are generated and output.

[0096]

(Equation 2) The basic concept of a method of generating disparity information for each pixel position on a one-field screen will be described with reference to FIG. It is assumed that the horizontal / vertical position (hereinafter, referred to as a target position) represented by the horizontal address signal HAD and the vertical address signal VAD is Pxy in FIG. A case where parallax information for the target position Pxy is obtained will be described.

(1) First, among the parallax information for each of the parallax calculation areas E1 to E12 calculated by the CPU 3, four vertices of the first divided area including the target position Pxy,
In this example, disparity information for the disparity calculation areas E1, E2, E5, and E6 centered on PE1, PE2, PE5, and PE6 is extracted as UL, UR, DL, and DR, respectively. That is, of the four vertices of the first divided region including the target position Pxy, the disparity information of the region E1 centered on the upper left vertex is the first disparity information UL, and the disparity information of the region E2 centered on the upper right vertex is UL. Is extracted as the second disparity information UR, the disparity information of the region E5 centered on the lower left vertex is extracted as the third disparity information DL, and the disparity information of the region E6 centered on the lower right vertex is extracted as the fourth disparity information DR. You.

However, only one vertex of the four vertices of the first divided region including the target position is disparity as in the case where the first divided region including the target position is the first upper left divided region. If the parallax information corresponds to the center of the detection area, the parallax information of the parallax calculation area is the first to fourth parallax information U
Extracted as L, UR, DL, DR.

Further, as in the case where the first divided area including the target position is the first divided area on the right side of the first divided area at the upper left corner, four vertices of the first divided area including the target position are used. If only the lower two vertices of the first divided area correspond to the center of the parallax calculation area, the parallax information UL corresponding to the upper two vertices of the four vertices of the first divided area including the target position, As the UR, parallax information of a parallax calculation area centered on the lower vertex is extracted.

Further, as in the case where the first divided area including the target position is the first divided area below the first divided area at the upper left end, the four vertices of the first divided area including the target position are used. Among the four vertices of the first divided area including the target position, only the two vertices on the right side correspond to the center of the parallax calculation area. , The parallax information of the parallax calculation area centered on the right vertex is extracted.

Further, as in the case where the first divided area including the target position is the first divided area to the left of the first lower divided right area, the four vertices of the first divided area including the target position are used. If only the upper two vertices of the first divisional area correspond to the center of the parallax calculation area, the parallax information DL corresponding to the lower two vertices of the four vertices of the first divided area including the target position, As DR, parallax information of a parallax calculation area centered on the upper vertex is extracted.

Further, as in the case where the first divided area including the target position is the first divided area on the upper right side of the first divided area, the four vertices of the first divided area including the target position are used. Among the four vertices of the first divided area including the target position, only the two vertexes on the left side of the parallax calculation area correspond to the center of the parallax calculation area. , The parallax information of the parallax calculation area centered on the left vertex is extracted.

(2) Next, the first to fourth parallax interpolation coefficients K
UL, KUR, KDL and KDR are required.

The first parallax interpolation coefficient KUL is determined by the target position P
xy, the distance ΔX from the target position Pxy to the right side of the first divided area e with respect to the horizontal width m of the first divided area e including xy
R and the ratio {(m-HPOS) / m} to the first divided region e
の (n−VPO) of the vertical width n to the distance ΔYD from the target position Pxy to the lower side of the first divided region e.
S) / n}. That is, the first
Is larger as the distance between the upper left vertex PE1 of the first divided area e including the target position Pxy and the target position Pxy is smaller.

The second parallax interpolation coefficient KUR is calculated based on the target position P
xy, the distance ΔX from the target position Pxy to the left side of the first divided region e with respect to the horizontal width m of the first divided region e
L (HPOS / m) and the ratio {(n-VPOS) / n} of the distance ΔYD from the target position Pxy to the lower side of the first divided region e with respect to the vertical width n of the first divided region e.
And the product of That is, the second parallax interpolation coefficient KUR increases as the distance between the upper right vertex PE2 of the first divided region e including the target position Pxy and the target position Pxy decreases.

The third parallax interpolation coefficient KDL is calculated based on the target position P
xy, the distance ΔX from the target position Pxy to the right side of the first divided area e with respect to the horizontal width m of the first divided area e including xy
R and the ratio {(m-HPOS) / m} to the first divided region e
(VPOS / n) of the distance ΔYU from the target position Pxy to the upper side of the first divided area e with respect to the vertical width n of
And the product of That is, the third parallax interpolation coefficient KDL increases as the distance between the lower left vertex PE5 of the first divided region e including the target position Pxy and the target position Pxy decreases.

The fourth parallax interpolation coefficient KDR is calculated based on the target position P
xy, the distance ΔX from the target position Pxy to the left side of the first divided region e with respect to the horizontal width m of the first divided region e
L and the ratio (VPOS / n) of the vertical width n of the first divided area e to the distance ΔYU from the target position Pxy to the upper side of the first divided area e. Desired. That is, the fourth parallax interpolation coefficient KD
R increases as the distance between the lower right vertex PE6 of the first divided area e including the target position Pxy and the target position Pxy decreases.

(3) The first to fourth extracted in the above (1)
To the parallax information UL, UR, DL, DR of the first to fourth parallax interpolation coefficients KUL, calculated in (2) above, respectively.
KUR, KDL, and KDR are each multiplied. Then, the obtained four multiplication values are added to generate disparity information for the target position Pxy.

The parallax information storage means 60 stores the areas E1 to E1.
2 are provided with first to twelfth parallax registers 61 to 72 provided correspondingly to the two. The first to twelfth disparity registers 61 to 72 store disparity information for each of the regions E1 to E12 generated by the CPU 3.

At the subsequent stage of the parallax information storage means 60, a parallax selection circuit 80 is provided. In the parallax selection circuit 80,
Parallax information is sent from each of the parallax registers 61 to 72. Further, the horizontal address signal HAD and the vertical address signal VAD are sent from the timing signal generation circuit 51 to the parallax selection circuit 80.

According to the rule shown in FIG. 23 (a), the parallax selecting circuit 80 determines the area corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 22, the first area including the target position). Of the parallax calculation area centered on the upper left vertex of the
Select and output as L. Further, the parallax selection circuit 80
Is a region corresponding to the horizontal address signal HAD and the vertical address signal VAD according to the rule shown in FIG. 23B (in the example of FIG. 22, the center is set at the upper right vertex of the first region including the target position). The disparity information for the disparity calculation area) is selected and output as the second disparity information UR.

Further, the parallax selecting circuit 80 is provided in FIG.
According to the rule shown in (c), an area corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 22, a parallax calculation area centered on the lower left vertex of the first area including the target position). Is selected and output as third parallax information DL. Further, the parallax selection circuit 80 determines the region corresponding to the horizontal address signal HAD and the vertical address signal VAD (in the example of FIG. 22, the first region including the target position in accordance with the rule shown in FIG. 23D). Parallax calculation area centered on the lower right vertex)
Is selected and output as fourth parallax information DR. In FIG. 23, for example, symbols “” ”represented by a and b, such as 0 to m, are used as symbols that mean not less than a and less than b.

The first selected by the parallax selection circuit 80
The disparity information UL, the second disparity information UR, the third disparity information DL, and the fourth disparity information DR are input to first, second, third, and fourth multipliers 81, 82, 83, 84, respectively.

First, second, third and fourth multipliers 8
1, 82, 83, and 84 also receive the first parallax interpolation coefficient KUL, the second parallax interpolation coefficient KUR, the third parallax interpolation coefficient KDL, and the fourth parallax interpolation coefficient KDR from the parallax interpolation coefficient generation circuit 52, respectively. I have.

The first multiplier 81 multiplies the first disparity information UL by a first disparity interpolation coefficient KUL. The second multiplier 82
The second parallax information UR is multiplied by a second parallax interpolation coefficient KUR. The third multiplier 83 multiplies the third disparity information DL by a third disparity interpolation coefficient KDL. The fourth multiplier 84 multiplies the fourth disparity information DR by a fourth disparity interpolation coefficient KDR.

The outputs of the multipliers 81, 82, 83 and 84 are added by an adder 85. Thereby, the disparity information PR for the target position is obtained.

Each of the arbitrary pixel delay FIFOs 11 and 21 is 1
To perform horizontal phase control in units smaller than pixels,
Each of the two line memories 11a, 11b, 21a,
21b. Each arbitrary pixel delay FIFO11, 2
1, two line memories 11a, 11b, 21a, 2
1b, a Y signal is input and a clock signal CLK is input.

The horizontal address signal HAD output from the timing signal generation circuit 51 is also input to the standard address generation circuit 90. Standard address generation circuit 90
Is a standard write address WAD and a standard read address R for the two line memories 11a, 11b, 21a, 21b in each of the arbitrary pixel delay FIFOs 11, 21.
Generate and output AD. Further, the standard address generation circuit 90 also outputs a synchronization signal Csync added to the left video signal and the right video signal obtained by the 2D / 3D converter. The horizontal synchronization signal represented by the synchronization signal Csync is a horizontal synchronization signal Hsync of the input video signal.
The signal is delayed by a predetermined number of clocks from c.

The standard read address RAD is used to advance or delay the horizontal phase of the video signal input to each of the arbitrary pixel delay FIFOs 11 and 21 with respect to the reference horizontal phase defined by the standard read address. In addition, it is delayed by a predetermined number of clocks from the standard write address WAD. The standard write address WAD output from the standard address generation circuit 90 is stored in the two line memories 11 in each of the arbitrary pixel delay FIFOs 11 and 21.
a, 11b, 21a, and 21b are input as write control signals indicating write addresses.

The standard read address RAD output from the standard address generation circuit 90 is input to an adder 91 and a subtractor 92, respectively. Adder 91 and subtractor 9
2, the parallax information PR of the target position output from the adding circuit 85 is also input.

At the adder 91, the standard read address R
The disparity information PR is added to AD. As a result, the left video read address PRL is obtained.

The integer part PRL1 of the left video read address PRL is stored in the first line memory 11a in the left video arbitrary pixel delay FIFO 11 in the read address RADL1.
Enter as Therefore, the first line memory 11
The Y signal is read from the address corresponding to the address RADL1 of a. The read Y signal is input to the first left video multiplier 101.

The address value obtained by adding 1 to the integer part PRL1 of the left video read address PRL is input to the second line memory 11b in the left video arbitrary pixel delay FIFO 11 as the read address RADL2. Therefore, the Y signal is read from the address corresponding to the address RADL2 of the second line memory 11b. The read Y signal is input to the second left video multiplier 102.

The read address RADL1 for the first line memory 11a differs from the read address RADL2 for the second line memory 11b by one, so that the Y signal read from the first line memory 11a The Y signal read from the second line memory 11b is a signal whose horizontal position is shifted by one.

The decimal part PRL2 of the left video read address PRL is input to the second left video multiplier 102 as a second left video interpolation coefficient. A value obtained by subtracting the decimal part PRL2 of the read address PRL for the left image from 1 (1-PR
L2) is input to the first left video multiplier 101 as a first left video interpolation coefficient.

Therefore, the first left video multiplier 101
Then, the Y signal read from the first line memory 11a is multiplied by a first left video interpolation coefficient (1-PRL2). In the second left video multiplier 102, the Y signal read from the second line memory 11b is multiplied by a second left video interpolation coefficient PRL2. Then, each multiplier 101,
The Y signal obtained by 102 is added by the adder 103, and then output as a left video Y signal YL-OUT.

Thus, the standard read address RAD
With respect to the reference horizontal phase defined by the above, a left image Y signal whose horizontal phase amount is delayed by an amount corresponding to the parallax information for the target position is obtained.

In the subtractor 92, the standard read address R
The disparity information PR is subtracted from AD. As a result, the right video read address PRR is obtained.

The integer part PRR1 of the right read address PRR is stored in the first line memory 21a in the right video arbitrary pixel delay FIFO 21 in the read address RADR1.
Enter as Therefore, the first line memory 21
The Y signal is read from the address corresponding to the address RADR1 of a. The read Y signal is input to the first right video multiplier 111.

The address value obtained by adding 1 to the integer part PRR1 of the right video read address PRR is input as the read address RADR2 to the second line memory 21b in the right video arbitrary pixel delay FIFO 21. Therefore, the Y signal is read from the address corresponding to the address RADR2 of the second line memory 21b. The read Y signal is input to the second right video multiplier 112.

Since the read address RADR1 for the first line memory 21a and the read address RADR2 for the second line memory 21b are different by one, the Y signal read from the first line memory 21a and The Y signal read from the second line memory 21b is a signal whose horizontal position is shifted by one.

The fractional part PRR2 of the right video read address PRR is input to the second right video multiplier 112 as a second right video interpolation coefficient. A value obtained by subtracting the decimal part PRR2 of the read address PRR for the right image from 1 (1-PR
R2) is input to the first right image multiplier 111 as a first right image interpolation coefficient.

Therefore, the first right video multiplier 111
Then, the Y signal read from the first line memory 21a is multiplied by a first right video interpolation coefficient (1-PRR2). In the second right image multiplier 112, the Y signal read from the second line memory 21b is multiplied by a second right image interpolation coefficient PRR2. Then, each multiplier 111,
The Y signal obtained by 112 is added by the adder 113 and then output as a right video Y signal YR-OUT.

Thus, the standard read address RAD
With respect to the reference horizontal phase defined by the above, a Y signal for right video is obtained in which the horizontal phase amount is advanced by an amount corresponding to the parallax information for the target position.

FIG. 24 shows that the parallax information for the target position is 0.
3 shows the signals of the respective units.

When the disparity information is 0, the left video read address PRL output from the adder 91 and the right video read address PRR output from the subtractor 92.
Is an address consisting of only an integer part without a decimal part equal to the standard read address RAD.

Therefore, the arbitrary pixel delay FIF for the left image
Read address RADL1 for the first line memory 11a in O11 and right image arbitrary pixel delay FIFO
The read address RADR1 for the first line memory 21a in the memory 21 is equal to the standard read address RAD.

Further, a left image arbitrary pixel delay FIFO 11
The read address RADL2 for the second line memory 11b in the first and the read address RADR2 for the second line memory 21b in the right image arbitrary pixel delay FIFO 21 have a value that is one greater than the standard read address RAD.

The first left image interpolation coefficient (1-PRL)
2) and the first right video interpolation coefficient (1-PRR2) are 1
And the second left video interpolation coefficient PRL2 and the second right video interpolation coefficient PRR2 become zero.

As a result, the left image arbitrary pixel delay FIFO
11, the standard address RA of the first line memory 11a
The Y signal read from the address corresponding to D is output from the adder 103 as the left video Y signal YL-OUT, and corresponds to the standard address RAD of the first line memory 21a in the right video arbitrary pixel delay FIFO 21. The Y signal read from the address to be output is output from the adder 113 as a right video Y signal YR-OUT. That is, two Y signals having the same amount of phase shift in the horizontal direction, that is, two Y signals having no parallax are output as a left video Y signal and a right video Y signal.

FIG. 25 shows the case where the standard write address WAD for a certain target position is 20, the standard read address RAD for the target position is 10, and the disparity information for the target position is 1.2. Is shown. FIG. 26 shows signals of the respective units at that time.

In this case, the read address PRL for the left image output from the adder 91 is 11.2,
Its integer part PRL1 becomes 11, and its decimal part PRL2
Is 0.2.

Therefore, the arbitrary pixel delay FIF for the left image
The read address RADL1 for the first line memory 11a in O11 is 11, and the read address RADL2 for the second line memory 11b is 12. Further, the first left video interpolation coefficient KL1 ｛= (1-PR
L2)｝ is 0.8, and the second left image interpolation coefficient KL2
(= PRL2) is 0.2.

Therefore, an arbitrary pixel delay FIF for the left image
The Y signal (Y11) is read from the address 11 of the first line memory 11a in O11, and the signal (0.8) that is 0.8 times the read Y signal (Y11) is read from the first multiplier 101. * Y11) is output.

On the other hand, a left image arbitrary pixel delay FIFO 11
, The Y signal (Y12) is read from the address 12 of the second line memory 11b, and the second multiplier 102 outputs a signal (0.2) that is 0.2 times the read Y signal (Y12).
* Y12) is output. Then, the adder 103 outputs a left video Y signal YL-OUT corresponding to 0.8 * Y11 + 0.2 * Y12. That is, the Y signal corresponding to the read address 11.2 is output as the left video Y signal YL-OUT.

The read address PRR for the right image output from the subtractor 92 is 8.8, and its integer part PRR
1 becomes 8, and the decimal part PRR2 becomes 0.8.

Therefore, the right picture arbitrary pixel delay FIF
The read address RADR1 for the first line memory 21a in O21 becomes 8, and the second line memory 2a
The read address RADR2 for 1b is 9.
Also, the first right video interpolation coefficient KR1 ｛= (1-PRR
2) と な り is 0.2, and the second right video interpolation coefficient KR2
(= PRR2) is 0.8.

Therefore, the right pixel arbitrary pixel delay FIF
The Y signal (Y8) is read from the address 8 of the first line memory 21a in O21, and the signal (0.2) which is 0.2 times as large as the read Y signal (Y8) is read from the first multiplier 111. * Y8) is output.

On the other hand, a right image arbitrary pixel delay FIFO 21
, A Y signal (Y9) is read from the address 9 of the second line memory 21b, and a signal (0.8 *) that is 0.8 times the read Y signal (Y9) from the second multiplier 112.
Y9) is output. Then, from the adder 113,
Y for right image equivalent to 0.2 * Y8 + 0.8 * Y9
The signal YR-OUT is output. That is, the Y signal corresponding to the read address 8.8 is the Y signal YR-
Output as OUT.

As a result, a left image and a right image having a disparity of 11.2−8.8 = 2.4, that is, a disparity twice as large as the disparity information 1.2 are obtained.

In the 2D / 3D video converter according to the above-described embodiment, a field memory for generating a video signal delayed in time with respect to the original two-dimensional video signal is unnecessary, so that the cost can be reduced. Can be achieved. Further, in the 2D / 3D video converter according to the above-described embodiment, a stereoscopic video can be obtained even if the video represented by the original two-dimensional video signal is a still video.

[0152]

According to the present invention, a field memory for generating a video signal delayed in time from the original two-dimensional video signal is not required, and a two-dimensional video whose cost can be reduced is reduced. An apparatus and method for converting to a two-dimensional image are realized.

Further, according to the present invention, an apparatus and a method for converting a two-dimensional video into a three-dimensional video, which can obtain a three-dimensional video even if the video represented by the original two-dimensional video signal is a still video, are realized. I do.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a 2D / 3D video conversion device.

FIG. 2 is a schematic diagram illustrating a parallax calculation area.

FIG. 3 is a block diagram illustrating a configuration of a luminance integration circuit.

FIG. 4 is a block diagram illustrating a configuration of a high-frequency component integration circuit.

FIG. 5 is a circuit diagram showing a specific example of a high-pass filter 232 of FIG.

FIG. 6 is a graph showing input / output characteristics of the slice processing circuit 234 of FIG.

FIG. 7 is a block diagram showing another example of the high frequency component integrating circuit.

8 is a circuit diagram showing a specific example of the peak detection circuit 239 in FIG.

FIG. 9 is a time chart showing signals of respective parts of the peak detection circuit 239.

FIG. 10 is a block diagram illustrating a configuration of a luminance contrast calculation circuit.

11 is a circuit diagram illustrating a configuration of a luminance contrast detection circuit in FIG.

FIG. 12 is a circuit diagram illustrating a configuration of a saturation integration circuit.

FIG. 13 is an explanatory diagram for describing a method of generating disparity information by a CPU.

FIG. 14 is a graph showing an input / output relationship of the normalizing means 410 of FIG.

FIG. 15 is a schematic diagram illustrating a parallax calculation area actually set.

FIG. 16 is a schematic diagram illustrating an example of depth information of each parallax calculation area before depth correction.

FIG. 17 is a schematic diagram illustrating depth information of each parallax calculation area after depth correction.

FIG. 18 is a graph showing a relationship between the height position of the screen before the depth correction and the depth information and a relationship between the height position of the screen after the depth correction and the depth information.

FIG. 19 is a graph showing a relationship between depth information and disparity information.

FIG. 20 is a block diagram mainly showing a configuration of a parallax control circuit and an arbitrary pixel delay FIFO.

FIG. 21 is a schematic diagram showing a relative horizontal position, a relative vertical position, and the like.

FIG. 22 is an explanatory diagram for describing a method of generating disparity information for a target pixel.

FIG. 23 is a diagram illustrating a selection rule by a parallax selection circuit.

FIG. 24 is a time chart illustrating signals of respective units when disparity information is 0;

FIG. 25 is a block diagram in which each address value when the disparity information is 1.2 is added to the disparity control circuit.

FIG. 26 is a time chart illustrating signals of respective units when the disparity information is 1.2.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 AD conversion circuit 3 CPU 4 Parallax control circuit 5, 6 DA conversion circuit 7 Luminance integration circuit 8 High-frequency component integration circuit 9 Luminance contrast calculation circuit 10 Saturation integration circuit 11, 12, 13 Left pixel arbitrary pixel delay FIFO 21, 22 23, right image arbitrary pixel delay FIFO 11a, 11b, 21a, 21b Line memory 51 Timing signal generation circuit 52 Parallax interpolation coefficient generation circuit 60 Parallax information storage means 61-72 Parallax register 80 Parallax selection circuit 81-84 Multiplier 85 Addition Circuit 90 Standard address generation circuit 91 Adder 92 Subtractor 101, 102, 111, 112 Multiplier 103, 113 Adder 401, 402, 403, 404, 410, 412 Normalization means 405, 406, 407, 408 Multiplication means 409 Addition means 411 depth correction means 413 Parallax information determination means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 13/00-15/00

Claims (4)

(57) [Claims] 1. A feature of setting a plurality of parallax calculation areas in each field screen of a two-dimensional video signal in advance, and extracting image features from the two-dimensional video signal in each parallax calculation area for each of the parallax calculation areas. extraction means, a parallax information generating means for generating parallax information in each parallax calculation region based on the feature of the image extracted by the feature extracting means, for each pixel, the image
The parallax calculation area including the element or the pixel thereof is included.
That the the unit parallax information generating means for generating unit parallax information from the parallax information of the parallax calculation regions adjacent to the parallax calculation region, the unit for the three-dimensional image based on the generated unit parallax information parallax generation information means An apparatus for converting a two-dimensional video into a three-dimensional video, comprising: video signal generating means for generating a first video signal and a second video signal having horizontal parallax from the two-dimensional video signal. Wherein said parallax information generating means includes a hand stage that generates a distance information of the parallax calculation for each region from the feature of the image, of the height position of the screen, perspective position represented by the distance information among the parallax calculation regions of lower than the closest height position, perspective position represented by the distance information for the parallax calculation region, from far-near position that is represented by the distance information of the parallax calculation region immediately thereabove the parallax calculation region which is farther than a predetermined value, so as to approach the perspective position represented by the distance information of the parallax calculation region immediately thereabove, and means for correcting the previous SL perspective information, parallax corrected 2. A means for converting the perspective information for each calculation area into disparity information for each parallax calculation area, wherein the two-dimensional image is converted into a three-dimensional image. apparatus. 3. A method of setting a plurality of parallax calculation areas in each field screen of a two-dimensional video signal in advance, and extracting a feature of an image from the two-dimensional video signal in each parallax calculation area for each of the parallax calculation areas. One step, a second step of generating disparity information for each disparity calculation area based on the features of the image extracted in the first step, and the disparity calculation including the pixel for each pixel Before the region or its pixels are included
A third step of generating unit parallax information from the parallax information of the parallax calculation area close to the parallax calculation area, and a third step having horizontal parallax for a three-dimensional video based on the unit parallax information generated in the third step. A fourth step of generating the first video signal and the second video signal from the two-dimensional video signal, the method comprising: converting a two-dimensional video into a three-dimensional video. Wherein said second step includes a Luz step to generate a perspective information of the parallax calculation for each region from the feature of the image, of the height position of the screen, perspective position represented by the distance information is most among the parallax calculation regions of the lower closer height, predetermined from the perspective position represented by the distance information of the parallax calculation region, the far near position that is represented by the distance information of the parallax calculation region immediately thereabove the parallax calculation region which is farther than the value, so as to approach the perspective position represented by the distance information of the parallax calculation region immediately thereabove, and correcting the previous SL perspective information, each parallax calculating corrected Converting the perspective information for each region into disparity information for each disparity calculation region. 2. The method according to claim 1, wherein the two-dimensional image is converted into a three-dimensional image. How to convert.