JPH1188467A - Communication control lsi and method for reducing power consumption of the communication control lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption when a protocol processing communication control LSI is used for a low speed channel or a channel with a low operating rate. SOLUTION: A frequency divider circuit 28 generates pluralities of frequencies lower than a frequency of an LSI clock 90, a line speed detection circuit 20 obtains a ratio of the generated frequencies to a frequency of a channel clock 91, a supply clock selection control circuit 24 and a selector 29 select a frequency division clock with a lowest frequency in matching with the channel speed and the selected clock is fed to a protocol processing section 3. Furthermore, a task execution monitor circuit 30, a synchronization state display circuit 41 and a process request monitor circuit 40 detect and monitor whether or not the execution is required and the supply clock selection control circuit 24 discriminates totally the information to interrupt the supply of the clock in matching with the channel speed to the protocol processing section 3 and to reduce the frequency of the supply clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power consumption reduction circuit, and more particularly to a power consumption reduction circuit of a communication protocol control LSI.

[0002]

2. Description of the Related Art A communication control LSI is incorporated in a data exchange or a communication control device to execute a communication protocol process.
It is generally known that a super LSI such as a communication control LSI has a CMOS structure, and that power consumption is directly proportional to a clock frequency.

On the other hand, the intervals at which factors requiring protocol processing occur are directly proportional to the communication line speed, that is, the line clock frequency, if the data length and frame type of the frames on the line are the same.

[0004] In a protocol process involving execution of software instructions by a microprocessor or the like, the instruction execution speed is directly proportional to the frequency of a clock supplied to the microprocessor.

Therefore, a direct proportional relationship is established between the frequency of the clock that must be supplied to perform the protocol processing and the frequency of the line clock, and a relationship also exists that is directly proportional to the power consumption.

[0006] Conventional communication control LSIs are designed with consideration for use in high-speed lines, heavy protocols, and high line utilization.

On the other hand, on the device side in which the communication control LSI is incorporated, it is necessary to accommodate an unspecified number of lines having various conditions, and the cost can be reduced by reducing the number of peripheral parts. A single frequency control clock is supplied from a clock source having a frequency.

First, the configuration of a conventional communication control LSI will be described with reference to FIG.

A communication control LSI for performing communication protocol processing of a layer at or above the link layer (level 2) includes a protocol processing unit 3 corresponding to a microprocessor (CPU) for performing communication protocol processing by software, and a protocol processing unit 3. A program memory unit 5 for storing a program to be executed, a work memory unit 6 for storing work data of the protocol processing unit 3, and control information and lines from a higher-level device (not shown) for controlling the communication control LSI. The upper interface unit 7 which performs DMA transfer control and input / output control for transferring the transmission data of the communication device, the report information to the higher-level device, and the reception data from the line. And a line connection unit 4 for performing the connection.

The LSI clock signal 90 has been supplied to the protocol processing unit 3 without performing frequency reduction by a frequency dividing circuit or the like.

In a conventional communication control LSI, for example, when used in an exchange, a terminal is usually used during a time period when the terminal is not operating, such as at night or on a holiday, or a standby device without connection to a line. Communication control LS even when used on the side
A clock is supplied to I.

That is, in the conventional communication control LSI, the CPU block for performing the protocol processing of the link layer is always controlled by the maximum operation clock in order to secure the throughput corresponding to the speed of the high-speed line. This does not change when a low-speed line is used or during idle processing when frame transmission / reception that does not require protocol processing is interrupted.

Therefore, the conventional communication control LSI has the following problems.

First, since the conventional communication control LSI is supplied with a clock having a constant frequency irrespective of the line speed, the power consumption becomes almost constant irrespective of the line speed. That is, the conventional communication control LSI consumes the same power even when the line speed is low as in the high speed.

Second, since a clock having a constant frequency is supplied irrespective of the protocol, the power consumption is substantially constant regardless of the protocol. In other words, even if the protocol actually being processed is a light process, the same power is consumed as the heaviest protocol that the communication control LSI can process.

Third, since a clock having a constant frequency is supplied irrespective of the line usage rate, power consumption is substantially constant regardless of the line usage rate. In other words, even if all the lines are actually unused, the same power is consumed as during congestion.

Fourth, since a clock having a constant frequency is supplied regardless of whether communication is actually performed, power is consumed even when communication is hardly performed. Examples include time zones such as nights and holidays when used in exchanges.

Fifth, since a clock having a constant frequency is supplied irrespective of the line speed, when an external memory for storing programs and data required for protocol processing is externally provided, an access time of a certain value or more is guaranteed. There is a need. That is, even if the line speed is low, a high-speed memory must be used.

[0019]

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication control LSI for processing a communication protocol with low power consumption.

The line connection is controlled by a line clock having a frequency equal to the line speed, and the upper interface is accessed only when necessary. For this reason, the power consumption of the line connection unit has already been reduced.

The power consumption of the protocol processing unit and the program memory unit and the work memory unit under the protocol processing unit are reduced.

Another object of the present invention is to provide a communication protocol processing communication which can easily obtain constituent parts and reduce the size and weight by reducing the number of parts of a device to be incorporated. The purpose is to provide a control LSI.

When the subordinate program memory unit / work memory unit has an external LSI configuration and the line speed is low, the use of a large-capacity low-speed memory is allowed, so that the availability of the components is improved and the device can be used. Reduce size and weight.

[0024]

According to the present invention, a line speed detecting circuit determines the maximum communication speed permitted by a communication control LSI, that is, the ratio of the line clock re-high frequency to the line clock actually supplied. The LSI power consumption is reduced by selecting one clock from a plurality of clock sources having a lower frequency obtained by dividing the LSI clock based on the ratio and supplying the clock to the protocol processing unit.

Also, the case where the in-synchronization display circuit displays the closed state of the line and the state of transmitting and receiving the synchronization pattern, and the state of waiting for the reception of the synchronization pattern of the receiving line,
When the processing request monitoring circuit indicates that DMA transfer of transmission / reception data is being performed, and when the task execution monitoring circuit displays a task generation waiting state, the clock supply to the protocol processing unit is interrupted to further consume the clock. Reduce power.

The power consumption reduction system of the present invention employs a line speed detection circuit (20 in FIG. 1) for obtaining a frequency ratio between an LSI clock (90 in FIG. 1) and a line clock (91 in FIG. 1).
And a task remaining number monitoring circuit (3 in FIG. 1) for executing task processing for protocol processing by dividing the task processing into a plurality of factors.
1) and a synchronization display circuit (41 in FIG. 1) for displaying and monitoring whether the line is blocking or transmitting / receiving a synchronization pattern.
Processing request monitoring circuit (40 in FIG. 1) for monitoring whether the line is transferring data requiring protocol processing.
And the various circuits (20, 30, 31, 41, 4 in FIG. 1)
Based on the input of 0), a specific protocol processing is performed by comprehensively judging the line speed of the communication control LSI (1 in FIG. 1), the lightness of the protocol, the line usage rate that changes every moment and the line usage rate according to the time zone. Clock selection control circuit (24 in FIG. 1) that variably controls the frequency of the clock supplied to the protocol processing unit (3 in FIG. 1) that performs the processing by software.
A frequency divider (28 in FIG. 1) for generating a plurality of clock sources having a low frequency; and a selector (FIG. 1) for selecting one clock source under the control of a supply clock selection control circuit from the plurality of clock sources. 29) for supplying a clock (via 102 in FIG. 1) having a frequency proportional to the line speed to the protocol processing unit (3 in FIG. 1) only when protocol processing is required; Supply a clock with a high frequency that is not proportional to the line clock frequency in order to prevent the interval required for protocol processing during continuous transmission and reception of short frames from narrowing and to avoid a sudden increase in the number of remaining tasks in the protocol processing unit and congestion. Means (2 in FIG. 9)
44) and access time storage indicating the proportion of the memory access time specified by the host device when the program memory section (5 in FIG. 1) and the work memory section (6 in FIG. 1) are connected to the outside of the LSI. A circuit (32 in FIG. 1) for suppressing supply of a clock having a high frequency for causing a memory having a low access speed to be in a congested state when connected is provided (245 in FIG. 1 and 245 in FIG. 9). .

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, referring to FIG.
The configuration of the embodiment will be described.

The clock control unit 2 including the frequency dividing circuit 28, the line speed detecting circuit 20, the supply clock selection control circuit 24, and the selector 29 is added as a new block, and is synchronized with the processing request monitoring circuit 40. The display circuit 41 is added to the line connection unit 4, and the task execution monitoring circuit 30, the remaining task number monitoring circuit 31, and the access time storage circuit 32 are added to the protocol processing unit 3.

Further, the connection between the LSI clock signal 90 and the protocol processing unit 3 is changed via the signal line 102 via the newly added clock control unit 2.

[Clock Control Unit 2] First, the purpose and overall operation of the additional block and circuit will be briefly described with reference to FIG.

In order to reduce power consumption in the protocol processing unit 3, the clock control unit 2 generates a plurality of clock sources having a lower frequency than the LSI clock 90 in the frequency dividing circuit 28,
The frequency of the LSI clock 90 is measured by the line speed detection circuit 20 to determine how many times the frequency of the line clock 91, and one clock having a frequency inversely proportional to a multiple of the measurement result, that is, a frequency proportional to the line speed, Under the control of the supply clock selection control circuit 24 from the plurality of clock sources, the clock is selected by the selector 29 and supplied to the protocol processing unit 3.

The clock control unit 2 further includes a line connection unit 4
During the synchronization display circuit 41 is during line blocking or synchronization operation,
And when the processing request monitoring circuit 40 indicates that the header of the frame on the line is not being transferred and that the task execution monitoring circuit 30 of the protocol processing unit 3 is performing idle processing without a task to be processed. , The control of interrupting the clock supply to the protocol processing unit 3 or switching to a lower frequency.

Further, when the task remaining number monitoring circuit 31 of the protocol processing unit 3 indicates a processing capacity shortage, that is, a congestion state indicating that the clock frequency supplied to the protocol processing unit 3 is too low, a higher frequency is set. Control to switch to.

Further, when the access time storage circuit 32 indicates that supply of a high frequency is prohibited, control is performed to switch to a lower frequency.

[Processing Request Monitoring Circuit 40 & Synchronizing Display Circuit 41] Next, the operation of the processing request monitoring circuit 40 and the synchronizing display circuit 41 added to the line connection unit 4 will be described with reference to FIGS. I do.

The state transition control circuit 44, the reception state register 42, and the transmission state register 43 are existing circuits. FIG. 3A shows an example of the operation on the reception side based on the flag synchronization method. FIG. 3B shows an example of the operation of FIG.
Is shown in the form of a state transition diagram.

The reception status register 42 stores the value of 4 in FIG.
This is a circuit for storing the current state number among a plurality of state numbers, which codes the synchronization on the receiving circuit side and the serial-parallel conversion state of the received data, etc., which are indicated by 01 to 405.

The transmission state register 43 stores the value of 4 in FIG.
The synchronization on the transmission line side indicated by reference numerals 20 to 425 and the parallel-to-serial conversion status of the transmission data are encoded.
This is a circuit for storing a current state number among a plurality of state numbers.

The state transition control circuit 44 determines the next state to be taken and performs various controls of the line connection unit 4 based on the current state number according to the state transition diagram based on the current state number and various transition factors (not shown). Circuit.

It is to be noted that the relationship is clarified by giving the same numbers to the output signals 401 to 405 and 420 to 425 from the transmission / reception state registers 42 and 43 and the numbers indicating the current state of the state transition diagram.

The processing request monitoring circuit 40 performs processing of a state where the state of the line connection unit 4 requires or immediately requires protocol processing, that is, processing of a header portion on a frame used for data transmission / reception on the line. State 404
And 422 are OR circuits.

The in-synchronization display circuit 41 is in a state in which the state of the line connection unit 4 does not absolutely require protocol processing, that is, 401, 402, 403, in which the line is blocked or synchronized for transmission and reception or the time file is being transmitted / received. 420, 4
This is a circuit that takes the OR condition of 21 and 425.

The character transmission state 423 and the character reception state 405 in FIG. 3 do not involve the protocol processing unit 3 due to the DMA transfer function expected to normally include data other than the header in the upper interface unit 7 in FIG. May be added to the OR condition of the in-synchronization display circuit 41. However, the case of including a higher-layer header or transfer by a program may be considered. Not included in the OR condition of 41.

[Task Execution Monitoring Circuit 30 & Remaining Task Monitoring Circuit 31] Next, the operation of the task execution monitoring circuit 30 and the remaining task monitoring circuit 31 added to the protocol processing unit 3 will be described with reference to FIGS. I do.

FIG. 5 shows a case in which the protocol processing unit 3 performs an operation like a real-time OS by dividing into an interrupt level and a base level by various instructions stored in the software, that is, the program memory unit 5 by a circuit equivalent to a CPU or a microprocessor. 5 is an example of a flowchart simply showing the task management relationship, in which the numbers indicating the processing boxes in FIG. 5 and the numbers of the input signal lines in FIG. 4 are the same.

The remaining task counter 33 is a function for counting the number of tasks remaining to be executed, which is the unit of execution of the protocol processing program. The addition and subtraction instructions of the protocol processing unit are implemented by hardware by using an up / down counter. Can be realized by software.
It is calculated by 306 and 328 in FIG. 5, and FIG. 4 shows a case of an 8-bit configuration as an example.

The remaining task number monitoring circuit 31 has a function of monitoring and displaying whether or not there is a congestion state based on the contents indicated by the remaining task number counter 33. For example, an AND condition of upper 4 bits is taken and divided into four levels. This shows the case of monitoring display.

The task execution monitoring circuit 30 has a function of monitoring and displaying whether or not the protocol processing unit 3 is in a state of operation, that is, whether or not there is no task to be executed and idling is in progress. The period from the end 301 to the end of the interrupt level processing 308 is monitored by the RS latch 380.
The period up to execution of the last instruction after detection by .about.387 is monitored by the RS latch 381, and the OR gate 382
Indicates to the outside that there is no interrupt processing or task processing to be executed.

[Line Speed Detecting Circuit 20] Next, the detailed operation of the line speed detecting circuit 20 will be described with reference to FIGS.

LSI clock 9 rather than line clock 91
Utilizing that the frequency of 0 is higher, a pulse signal of the LSI clock 90 input during one cycle of the line clock 91 is generated by the flip-flops 201 and 202 and the AND gate 203, and the number of pulses is counted by the counter 204. (In FIG. 6, for example, an 8-bit binary counter is used to reduce the number of bits in consideration of the number of bits, and the clock 108 reduced by the frequency dividing circuit 28 is input.) The line clock of the LSI clock 90 is counted. , And edit the result (in FIG. 6, for example, to divide the line speed into four groups, the output of the counter 204 is divided into OR gates 207, 208, 209, and 2 in units of 2 bits).
10 is input. ) And is connected to the supply clock selection control circuit 24 via the signal line 107.

For reference, FIG. 8 shows grouping in the circuit configuration in FIG. 2 as an example. In FIG. 8, the input of a 25 MHz LSI clock is permitted, the maximum processable communication speed is 6.144 Mbps, and the counter 204
The input after dividing the LSI clock frequency by 4 (１ ／) with 8 bits is connected to the signal line 108.

The reset signal 92 in the figure is based on the premise that the line clock 91 is input in an LSI reset state, but if it is not input, the reset signal 92 is ORed with a measurement start instruction signal from another route. Can be resolved by taking

[Supply Clock Selection Control Circuit 24] Next, the detailed operation of the supply clock selection control circuit 24 will be described with reference to FIG.

FIG. 9 shows that the power consumption of the protocol processing unit 3 is reduced to the utmost, and that the fifth problem described in the problem to be solved by the invention and the low-speed line predicted with the implementation of the present invention are reduced. It shows an example of a maximum hardware scale configuration that addresses the new problem of preventing the occurrence of congestion, which is a new issue that is allowed on high-speed lines but not allowed on low-speed lines when a clock with a frequency is supplied. By changing the combination of its own internal configurations, several tens of configurations are possible.

FIGS. 10 to 18 show typical embodiments which can be considered based on the magnitude of the hardware scale and the effect of reduction. FIG. 9 has the same configuration as the supply clock selection control circuit of FIG.

On the signal lines 107A to 107D, the highest rank reflecting the allowable maximum communication speed and the actual accommodating communication speed from the line speed detection circuit 20 or the frequency division number register 21 shown in FIG. Numerical information with the bit being on the 107A side is input.

On the signal line 104, a display circuit 4 during synchronization is provided.
When the polarity is from 1 to 0, 1-bit information indicating that no protocol processing is required is input.

On the signal line 103, the processing request monitoring circuit 4
When the polarity is 0 to 0, 1-bit information indicating that no protocol processing is required is input.

On the signal line 105, 1-bit information is input from the task execution monitoring circuit 30 when the polarity is 0, meaning that protocol processing is not required.

Numerical information is input to the signal lines 106A to 106D from the task remaining number monitoring circuit 31 so that the remaining number of tasks requiring protocol processing has the most significant bit on the 106A side.

When the task executing circuit 241, the line operating circuit 242, and the header processing circuit 243 indicate that the protocol processing is necessary on the signal line 104, 103 or 105, the clock 102 supplied to the protocol processing unit 3 is used. Numerical information on the signal lines 107A to 107D including the frequency information of
If all of the signal lines 104, 103 and 105 indicate that no protocol processing is required, the signal lines 107A to 107A
The numerical information on 7D is changed to “0”, that is, the frequency of the clock 102 is changed to 0, that is, an instruction to interrupt the supply of the clock 102, and relayed to the condition combination circuit 244.

The condition combination circuit 244 merely takes the logical loop of the input signal, but the signal lines 106A to 106D
If the upper numerical information is larger than the numerical information on the signal lines 107A to 107D, that is, if the remaining number of tasks requiring the processing in the protocol processing unit 3 increases and the congestion occurrence state is displayed, the clock 102 It has a function to convert to an instruction to increase the frequency of

Information indicating that high-speed clock supply is prohibited when the polarity is 1 is input from the access time storage circuit 32 to the signal lines 111A and 111B, and the high-speed clock prohibition circuit 245 converts the information into an instruction to lower the frequency of the clock 102. With the ability to

The switching signal editing circuit 246 is connected to the signal line 107
When the numerical information on the signal lines A to 107D or the signal lines 106A to 106D indicates a polarity 1 of a plurality of bits that are not a power of two, a signal in which only one bit has the polarity 1 is output on the switching control signals 110A to 110E of the selector 29. This is a variant detour to perform the editing such as grouping, which is basically composed of decoders and the number of higher-order output signal lines, or grouping of higher-order output signals by OR gates several times. A signal equal to the number of 110 is output.

FIGS. 20A and 20B show specific circuit examples of the switching signal editing circuit 246. FIG.

FIG. 20A shows an example in which the higher-order output signal of the decoder is simply output as a switching signal of selector 29, and FIG.
Is an example in which upper output signals of a decoder are grouped by OR gates two by two and grouped.

[Selector 29] Next, the operation of the selector 29 will be described with reference to FIG.

FIG. 21A is a circuit example in which only one of the selector input signals has a polarity of 1, and FIG. 21B is a circuit example in which a plurality of selector input signals have a polarity of 1. A flip-flop 291 at the subsequent stage of the selector has This is a waveform shaping flip-flop for preventing the clock from being broken or the width being narrowed to be in a mustache state.

[Division number designating register 21] The frequency dividing number designating register 21 is transmitted to the line speed detection circuit 20 shown in FIGS. 1 and 6 by the higher-level device (not shown) via the higher-level interface unit 7 and the signal line 113. The same information as that detected by the LSI clock 90, that is, a mode of setting the frequency magnification of the LSI clock 90 with respect to the line clock 91 is shown.

The parts other than the division number designation register 21 in FIG. 19 are the same as those in FIG.

[0071]

【Example】

(Embodiment 1) Next, an embodiment of the present invention will be briefly described with reference to the drawings, focusing on differences from the above-described embodiment.

FIG. 10 shows a first embodiment of the present invention, in which the in-synchronization display circuit 41 of the line connection unit 4 and the AND gate 1 of the line operation circuit 242 of the supply clock selection control circuit 24 are shown.
And the waveform shaping flip-flop. When the in-synchronization display circuit 41 detects that the line connection unit 4 is in the closed state, the polarity of the signal line 104 is set to 1 and the line operation circuit 2 is turned on.
This is a method for reducing the power consumption of the communication control LSI by closing the AND gate 42 and interrupting the clock supply to the protocol processing unit 3 by the signal line 102.

(Embodiment 2) FIG. 11 shows a second embodiment of the present invention.
And one AND gate of the task execution circuit 241 of the supply clock selection control circuit 24 and the waveform shaping flip-flop, and the remaining task number counter 33 and the task execution monitoring circuit 30 When the state where all the accompanying task processes are completed is detected, the polarity of the signal line 105 is set to 0 and the task executing circuit 24 is set.
This is a method for reducing the power consumption of the communication control LSI by closing one AND gate and interrupting the clock supply to the protocol processing unit 3 by the signal line 102.

(Embodiment 3) FIG. 12 shows a third embodiment of the present invention, in which the line speed detection circuit 20, the frequency divider 28, the selector 29, and the supply clock selection control circuit 24 of the clock controller 2 are switched. A signal editing circuit 246,
A plurality of clock sources obtained by dividing the LSI clock 90 by the frequency dividing circuit 28 are generated, the ratio between the LSI clock 90 and the line clock 91 is determined by the line speed detecting circuit 20, and the selector signal is switched by the switching signal editing circuit 246. Edit it into a signal,
This is a method for reducing the power consumption of a communication control LSI in which a low-frequency clock that matches the communication speed is selected from a plurality of clock sources by a selector 29 and supplied to a protocol processing unit 3.

(Embodiment 4) FIG. 13 shows a fourth embodiment of the present invention, in which a higher-level device (not shown) supplies a frequency-division designation register 21 via a higher-level interface unit 7 to a frequency-division circuit 28. Setting and instructing selection information from a plurality of clock sources obtained by dividing the LSI clock 90 by the
This is a power-consumption reduction method of a heterogeneous communication control LSI selected and supplied to the protocol processing unit.

(Embodiment 5) FIG. 14 shows a fifth embodiment of the present invention, in which the third embodiment of FIG. 12 or the fourth embodiment of FIG. 13 and the first embodiment shown in FIG. Combine with the example,
Line operating circuit 242 of supply clock selection control circuit 24
Is replaced with a plurality of AND gates.

(Embodiment 6) FIG. 15 shows a sixth embodiment of the present invention, which is similar to the third embodiment of FIG. 12 or the fourth embodiment of FIG. 13, the second embodiment of FIG. Communication control LS having a configuration in which the task execution circuit 241 of the supply clock selection control circuit 24 is replaced with a plurality of AND gates
This is a method for reducing the power consumption of I.

(Embodiment 7) FIG. 16 shows a seventh embodiment of the present invention.
3. Task execution monitoring circuit 30 and remaining task number monitoring circuit 31
And a switching signal editing circuit 24 of the frequency dividing circuit 28, the selector 29, and the supply clock selection control circuit 24 of the clock control unit 2.
The frequency dividing circuit 2 calculates the ratio between the maximum number of tasks that can be registered in the task execution queue and the number of tasks that are actually registered in the waiting state by the remaining task number monitoring circuit 31.
LS according to ratio from multiple clock sources made in 8
A clock having a lower frequency than the I clock 90
9 is a method for reducing the power consumption of the communication control LSI selected and supplied to the protocol processing unit 3.

(Embodiment 8) FIG. 17 shows an eighth embodiment of the present invention. The fifth embodiment shown in FIG. 14, the sixth embodiment shown in FIG. 15, and the seventh embodiment shown in FIG. This configuration has a configuration in which a part of the synchronizing display circuit 41 and the processing request monitoring circuit 40 are added to the line connection unit 4 and the header processing circuit 243 and the condition combination circuit 244 are added to the supply clock selection control circuit 24. This is a power consumption reduction method for a communication control LSI that performs the operation described in the embodiment of the present invention.

(Embodiment 9) FIG. 18 shows a ninth embodiment of the present invention.
Or, connect both to the outside of the communication control LSI, add the high-speed clock prohibition circuit 245 to the supply clock selection control circuit 24, and add the access time storage circuit 32 to the protocol processing unit 3.
And the operation of switching the clock supplied to the protocol processing unit 3 to a lower frequency than the selected clock in the eighth embodiment by the high-speed clock inhibiting circuit 245 when the access time of the external memory is slow. This is a method for reducing the power consumption of the communication control LSI to be performed.

(First Embodiment of Line Speed Detection Circuit 20)
FIG. 6 shows a first embodiment of the line speed detection circuit 20,
A line speed detection circuit having the configuration described in the embodiment of the present invention and having a function of counting the number of pulses of the LSI clock 90 input during one cycle of the line clock 91.

(Second Embodiment of Line Speed Detection Circuit 20)
FIG. 22 shows a second embodiment of the line speed detection circuit 20, and the configuration and operation will be described in detail with reference to FIGS.

The line speed detection circuit shown in FIG.
1A is an example of a circuit that can support both a clock whose one cycle is not equal in interval such as the line clock 911 of A and a clock whose one cycle is equal in interval such as the line clock 912.

During a period from immediately after the reset 92 is released until the AND gate 223 detects a constant value, the line clock 9
The number of 1 pulses is counted by the counter 221 to notify the AND gate 224 of the time corresponding to a fixed number of bits of the line clock, and the number of LSI clocks input within the time is counted by the counter 225 to obtain the line. The frequency ratio between the clock and the LSI clock is calculated.

The circuit of FIG. 22 multiplexes transmission / reception data of a plurality of lines into one transmission / reception data signal line in octet units, shares the data signal lines with a plurality of communication control LSIs, and separates the line clock signal lines. Each communication control L
This is an example in the case of connection to the SI, and it is possible to cope with various types of multiplexing by increasing the number of bits of the counter 221.

As described above, the present invention has been described based on the embodiments and examples. However, the present invention is not limited to these, and can be changed or improved within the ordinary knowledge of those skilled in the art. Of course there is.

[0087]

The first effect is that, by monitoring and detecting the internal state, the supply clock is interrupted and the power consumption of the entire LSI can be reduced.

The reason is that an LSI having a CMOS structure
This is because the power consumption is proportional to the frequency.

The second effect is that the power consumption of the entire LSI can be reduced by supplying a low frequency clock proportional to the line speed.

The reason is that an LSI having a CMOS structure
This is because the power consumption is proportional to the frequency.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a line connection unit of FIG. 1;

FIG. 3 is a state transition diagram showing the operation of the line connection unit of FIG.

FIG. 4 is a block diagram of a protocol processing unit of FIG. 1;

FIG. 5 is a flowchart illustrating an operation of a protocol processing unit in FIG. 1;

FIG. 6 is a block diagram of a line speed detection circuit of the clock control unit of FIG. 1;

FIG. 7 is a time chart of a line speed detection circuit of the clock control unit of FIG. 1;

FIG. 8 is a table illustrating grouping in the circuit configuration in FIG. 2;

FIG. 9 is a block diagram of a supply clock selection control circuit of the clock control unit of FIG. 1;

FIG. 10 is a block diagram of one embodiment of the present invention.

FIG. 11 is a block diagram of one embodiment of the present invention.

FIG. 12 is a block diagram of one embodiment of the present invention.

FIG. 13 is a block diagram of one embodiment of the present invention.

FIG. 14 is a block diagram of one embodiment of the present invention.

FIG. 15 is a block diagram of one embodiment of the present invention.

FIG. 16 is a block diagram of one embodiment of the present invention.

FIG. 17 is a block diagram of one embodiment of the present invention.

FIG. 18 is a block diagram of one embodiment of the present invention.

FIG. 19 is a block diagram showing another embodiment of the present invention.

FIG. 20 is a circuit diagram of the switching signal editing circuit of FIG. 9;

FIG. 21 is a circuit diagram of the selector of FIG. 1;

FIG. 22 is a block diagram of one embodiment of the present invention.

FIG. 23 is a time chart of the embodiment shown in FIG. 22;

FIG. 24 is an overall block diagram showing a conventional configuration.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Communication control LSI 2 Clock control unit 3 Protocol processing unit 4 Line connection unit 5 Program memory unit 6 Work memory unit 7 Upper interface unit 20 Line speed detection circuit 21 Division number designation register 24 Supply clock selection control circuit 28 Frequency division circuit 29 Selector 40 Processing request monitoring circuit 41 Synchronization display circuit 42 Receiving status register 43 Transmission status register 44 State transition control circuit 90 LSI clock input signal line 91 Line clock input signal line 92 Reset input signal line 102 to 113 Connection signal between internal blocks Line 241 Circuit during task execution 242 Circuit during line operation 243 Circuit during header processing 244 Condition combination circuit 245 High-speed clock inhibit circuit 246 Switching signal editing circuit 247 Decoder 291 Waveform shaping flip-flop

Claims (11)

[Claims] In a method for reducing power consumption of a communication control LSI including a protocol processing unit for executing a communication protocol process, a clock to the protocol processing unit is detected when a state in which a communication protocol process on a line is not required is detected. A method for reducing power consumption of a communication control LSI, characterized by interrupting supply. 2. A method for reducing the power consumption of a communication control LSI including a protocol processing unit for executing a communication protocol process, wherein the protocol processing unit detects that neither an interrupt nor a task process accompanying the interrupt has occurred. Interrupting the clock supply to the communication control LSI. 3. A method for reducing the power consumption of a communication control LSI having a protocol processing unit for executing a communication protocol processing, wherein a ratio between an allowable maximum communication speed and a line speed actually accommodated is determined. A method for reducing power consumption of a communication control LSI, wherein a proportional relationship is provided between the frequency of a clock and the frequency of a clock supplied to the protocol processing unit. 4. A method for reducing power consumption of a communication control LSI including a protocol processing unit that executes a communication protocol process, wherein the communication control LSI is configured to perform the communication based on an instruction from a higher-level device connected to a higher-level device of the communication device including the communication control LSI. A method for reducing power consumption of a communication control LSI, wherein a proportional relationship is provided between a frequency of a control clock of the control LSI and a clock frequency supplied to the protocol processing unit. 5. A communication control LSI according to claim 3, wherein said communication control LSI includes a protocol processing unit for executing a communication protocol process.
2. A method for reducing power consumption of an SI, and a communication control method according to claim 1.
A method for reducing power consumption of a communication control LSI, which is combined with a method of reducing power consumption of an SI. 6. A communication control LSI according to claim 3, wherein said communication control LSI includes a protocol processing unit for executing a communication protocol process.
3. A method for reducing power consumption of an SI, and a communication control L according to claim 2.
A method for reducing power consumption of a communication control LSI, which is combined with a method of reducing power consumption of an SI. 7. A power control method for a communication control LSI including a protocol processing unit for executing a communication protocol process, wherein a ratio between a maximum number of tasks that can be registered in a queue and a number of tasks waiting to be executed is obtained, and a ratio of an LSI control clock is determined. Between the frequency and the clock frequency supplied to the protocol processing unit,
A method for reducing power consumption of a communication control LSI, characterized by providing a proportional relationship with the determined ratio. 8. A communication control LSI according to claim 5, wherein said communication control LSI includes a protocol processing unit for executing communication protocol processing.
8. A method for reducing power consumption of an SI, and a communication control method according to claim 7.
A method for reducing power consumption of a communication control LSI, which is combined with a method of reducing power consumption of an SI. 9. The method for reducing power consumption of a communication control LSI according to claim 8, further comprising limiting a frequency of a clock supplied to said protocol processing unit. 10. A communication control LSI including a protocol processing unit for executing a communication protocol process, wherein the communication control LSI has a function of counting the number of control clock pulses of the communication control LSI input during one cycle of a line clock. Communication control LSI. 11. A communication control LSI including a protocol processing unit for executing a communication protocol processing, wherein the number of line clock pulses is counted until a predetermined value is reached, and the number of control clock pulses of the communication control LSI input during that time is counted. Communication control LS characterized by having a function of counting
I.