JPH1188180A - One-bit signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compress a bit stream by dividing a one-bit signal stream into words consisting of n bits and encoding the n-bit words into an encoded word with bits being smaller than n in number. SOLUTION: An encoder 40 divides a bit stream into the words with n-bits and the words are encoded based on the occurrence probability of the words so that the bit stream is compressed. The bit stream of a one-bit signal is divided into sets a, b and c which respectively consist of the n-bits and the encoder 40 and a histogram circuit 41 executes encoding, for example, in the first set (a) at first, in the second set (b) secondly and, then, in the third set (c). Encoding is executed in the set of the continuous n-bits in a window W provided with n-bit width, the bit stream is made to continuously flow in the window W and a succeeding M+1 bit is predicted and encoded based on a M-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal processing device for processing a 1-bit signal. Further, the present invention relates to n (≧
1) A signal processing apparatus for processing a 1-bit signal having the following delta-sigma modulator. Although the preferred embodiment of the present invention relates to audio signal processing and the present invention has been described in connection with an audio signal processing device, the present invention is not limited to an audio signal processing device.

[0002]

2. Description of the Related Art The background art of the present invention will be described with reference to FIGS. Analog signal,
It is known that an analog signal is converted into a digital signal by sampling at a frequency equal to or higher than the Nyquist frequency and quantizing the amplitude of the obtained sample with m bits. For example, when m = 8, the sample value is 8
Quantized with bit precision. Generally, m is 1 or more.

An analog / digital converter (hereinafter referred to as an AD converter) for quantizing an analog signal into a 1-bit digital signal.
Called C. ) Are known as “sigma-delta ADC” or “delta-sigma ADC”. here,
The term "delta-sigma" is used. Such delta-sigma ADCs are, for example, Craig Marvin
g Marven), Gillian Ewers
Author, 1993, Texas Instrument (Texas In
struments) “A Simple Approach to Digital Signal Proces
sing) "(ISBN 0-904.047-00-8).

In such an ADC, as shown in FIG. 1, a difference (delta) between an analog input signal and an integrated value (sigma) of a 1-bit output signal is represented by a 1-bit quantizer 3.
Supplied to The output signal comprises bits of logic 0 and logic 1, where logic 0 and logic 1 represent -1 and +1 as actual values, respectively. The integrator 2 accumulates the 1-bit output signal and outputs an accumulated value that follows the value of the analog input signal. The 1-bit quantizer 3 increases (+1) or decreases (-1) the accumulated value for each generated bit.
The sampling frequency of the ADC is set to a high frequency so that an output bit stream whose accumulated value follows the analog input signal can be generated.

[0005] The term "one bit" signal used in the claims and in the following description refers to, for example, delta-sigma A
Means a signal generated by DC and quantized with one digital bit precision. A delta-sigma modulator (hereinafter, referred to as DSM) is configured as an n-th filter that directly processes a 1-bit signal, and the n-th filter is a 10-th filter performed on October 7 to 10, 1993. N. At the 95th AES (Audio Engineering Society) conference. M. Casey (NM Casey), James A. S. A paper published by James AS Angus, "One Bit Diagonal Processing of Audio Signals (One Bit Di
gital Processing of Audio Signals) "-signal processing:
Speech Research Group, Electrical Division, York University, Hesslington, York Y01 5DD UK (Signal Processin
g: Audio Research Group, The Electronics Departme
nt, The University of York, Heslington, York YO1 5
DD England). Figure 2 shows the DSM
FIG. 3 is a block diagram showing a configuration of a third (n = 3) -order filter portion.

As shown in FIG. 2, the DSM has an input terminal 4 for inputting a 1-bit signal and an output terminal 5 for outputting a processed 1-bit signal. Each bit of the 1-bit signal is processed in synchronization with a predetermined clock (not shown) in the entire DSM. The output bit signal is generated by, for example, a 1-bit quantizer Q including a comparator having a threshold value of 0. The DSM has 1-bit multipliers a ₁ , a ₂ , a ₃ connected to the input terminal 4 and 1-bit multipliers connected to the output terminal 5.
Bit multipliers c ₁ , c ₂ , c ₃ and adders 6 ₁ , 6 ₂ , 6
₃ and integrators 7 ₁ , 7 ₂ , 7 ₃ .

The 1-bit multipliers a _{1 to} a ₃ and c _{1 to} c ₃ provide p-bit coefficients A ₁ to A ₁ to the supplied 1-bit signal.
Multiplied by A _3, C ₁ -C _3, respectively, the multiplication value of p bits obtained are added by an adder ₆₁ through _3, the addition value obtained is supplied to the integrator 7 _{1-7 3.} The adder 6 _2, 6 ₃ of the intermediate stage, the output of the preceding integrator is also added, respectively. The final stage is a 1-bit multiplier a ₄ connected to the input terminal 4, and an adder 6 _4, 1-bit multiplier a _4,
Multiplied by the coefficient A ₄ p-bit input 1-bit signal, the adder 6 ₄ adds the output of the preceding integrator 7 ₃ of this multiplied value. Then, the obtained addition value is supplied to the 1-bit quantizer Q.

In DSM, two's complement arithmetic is used to represent the number of positive and negative p bits. When a positive value is input, the 1-bit quantizer Q quantizes it to +1 (logic 1), and when a negative value is input, quantizes it to -1 (logic 0) and outputs it. I do. In a paper by Casey and Angus, "A 1-bit processor produces a 1-bit output signal containing an audio signal that is unacceptably obscured by noise, so ... Must be done. " The noise obscuring the audio signal is quantization noise generated by the 1-bit quantizer Q.

The 1-bit quantizer Q has a first input terminal to which an audio signal is supplied and a second input terminal to which a random bit stream (quantization noise) having substantially no correlation with the audio signal is supplied. And an adder having In this model, the audio signal input through the input terminal ₄ is output from the output terminal 5 by the 1-bit multipliers a _{1 to} a ₄ .
And are fed back by 1-bit multipliers c _{1 to} c ₃ . Therefore,
Factor A ₁ to A ₄ in the feed-forward path, defines the zero point in the z-transform of the transfer function of the audio signal, the coefficient C ₁ -C ₃ in the feedback path defines an electrode in the z-transform of the transfer function.

The noise signal is fed back from the 1-bit quantizer Q by the 1-bit multipliers c _{1 to} c ₃ , so that the coefficients C _{1 to} C ₃ define the poles of the transfer function of the noise signal. Factor _{A 1 ~A 4, C 1 ~C} 3 is determined so that the circuit stability amongst other desired properties.

[0011] Factor C ₁ -C _3, for example as shown by the solid line 31 in FIG. 3, it is defined so as to minimize by removing the quantization noise in the audio band. Coefficients A _{1 to} A ₄ , C _{1 to} C ₃
Is also determined so as to obtain desired audio signal characteristics.

The coefficients A _{1 to} A ₄ and C _{1 to} C ₃ can be determined as follows. a) For example, a transfer function of a desired filter characteristic having a noise removing function is z-transformed to obtain H (z). b) Convert H (z) to coefficients.

This is described in “Theory and Practical Implementat of a 5th Order Sigma-Delta A / D Converter”.
ion of a Fifth Order Sigma-Delta A / D Converte
r) ", Audio Engineering Society
Journal, volume 39, no. 7/8, 1991, July / August, Earl. double. Adams et al. (Journal of A
udioEngineering Society, Volume 39, no.7 / 8, 1991
July / August by RW Adamset al.), And the method described in the above-mentioned article by Angus and Casey,
It can be carried out. A specific method for determining the coefficient will be described in a separate sheet.

Attached Sheet Calculation of Coefficients This attached sheet outlines a process of analyzing a fifth-order DSM and a process of calculating a coefficient capable of obtaining a desired filter characteristic.

As shown in FIG. 8, the fifth-order DSM includes a multiplier for coefficients a to f, an adder 6, an integrator 7, and a coefficient A to
E multiplier. The integrators 7 each have a unit delay time. The integrator 7 outputs signals s to w, respectively. The signal x [n] is input to the DSM. Here, [n] represents one sample in a continuous sample synchronized with the clock. The quantizer Q outputs the signal y
[n], and this signal y [n] is also the output signal of the DSM. An analysis is performed based on a model that considers the quantizer Q to operate as a simple adder that adds random noise to a signal. Therefore, the quantizer Q is ignored in this analysis.

The output signal y [n] at sample [n] is
The input signal x [n] is multiplied by a coefficient f, and the output signal w [n] of the preceding integrator 7 is added thereto.
[n] = fx [n] + w [n]. When the same principle is applied to each output signal of the integrator 7, the following equation 1 is obtained.

Y [n] = fx [n] + w [n] w [n] = w [n−1] + ex [n−1] + Ey [n−1] + v [n−1] v [n] = v [n-1] + dx [n-1] + Dy [n-1] + u [n-1] u [n] = u [n-1] + cx [n-1] + Cy [n-1] + t [n -1] t [n] = t [n-1] + bx [n-1] + By [n-1] + s [n-1] s [n] = s [n-1] + ax [n-1] + Ay [n-1] Expression 1 When these Expressions 1 are z-transformed, the following Expression 2 is obtained.

Y (z) = fX (z) + W (z) W (z) (1-z ⁻¹ ) = z ⁻¹ (eX (z) + EY (z) + V (z)) V (z) ( 1-z ^-1 ) = z ^-1 (dX (z) + DY (z) + U (z)) U (z) (1-z ^-1 ) = z ^-1 (cX (z) + CY (z) + T ( z)) T (z) (1-z ^-1 ) = z ^-1 (bX (z) + BY (z) + S (z)) S (z) (1-z ^-1 ) = z ^-1 (aX ( z) + AY (z)) Expression 2 In the z-conversion expression 2, when Y (z) is solved as a single function of X (z), the following expression 3 is obtained.

[0019]

(Equation 1) The transfer function of DSM is Y (z) / X (z).
Is represented by a series of z. The first line on the right side of Expression 4 can be expressed as shown in the second line based on Expression 3.

[0020]

(Equation 2)In Equation 4, the coefficient α is set so as to satisfy the desired transfer function.
_n, Β_nAnd the coefficient α ₀~ Α_FiveFrom the coefficients f to a and the coefficient β
₀~ Β_FiveTo derive the coefficients EA. In the numerator of the second line on the right side
Z⁰Is only f, so that f = α₀In
You.

Next, from the numerator of the first line on the right side, α ₀ (1-z
^-1) Subtracting ^{_{5, α 0 + α 1 z}} -1 ··· + ··· α 5 z -5 -
α ₀ (1-z ⁻¹ ) ⁵ is obtained. Similarly, f (1-z ^-1 ) ⁵ is subtracted from the numerator of the second line on the right side. At this time, the term of z ^-1 is e
This e is equal to the corresponding α ₁ in the first line on the right side.

The above process is repeated for all the terms of the numerator of the equation (4) to obtain coefficients d to a. This process is repeated for all the terms of the denominator of Expression 4 to obtain the coefficients E to
Ask for A.

[0023]

According to the present invention, there is provided a signal processing apparatus for processing a 1-bit signal, comprising: a dividing means for dividing a stream of a 1-bit signal into words of n (>> 1) bits; Encoding means for encoding the word into an encoded word having a smaller number of bits than n bits.

A bit stream of a 1-bit signal, in particular D
Since the bit stream of the 1-bit signal generated by the SM is close to a random sequence of 0s and 1s and has no redundancy or correlation, a compression technique using redundancy and / or correlation between signals is used. Does not seem to be suitable for However, according to the invention, a succession of bits is
It occurs less frequently than other bit sequences, and in fact, such bit sequences are very rare, if at all, especially in audio signals. For example, a long series of +1 or -1 is very unlikely to occur because it represents the maximum positive or negative amplitude of the signal. Therefore, in the present invention, the bit stream is compressed by dividing the bit stream into n-bit words and encoding the words based on the probability of occurrence.

In one embodiment, an n-bit word comprises a mutually exclusive set of n bits. In another embodiment, an n-bit window through which a stream of 1-bit signals passes continuously is used. Each successive different set of n bits in the window is encoded.

Other encodings, such as predictive encoding, can be used to compress a 1-bit bit stream. That is, a window having a length of (n-1) bits is used, and the next n-th bit is predictively coded based on (n-1) bits in this window. Another encoding method uses n bits contiguous with the previous Q bits and uses a window with a Q bit width greater than n to encode a subset of the length of n bits in the Q bits. .

Further, a signal processing apparatus for processing a 1-bit signal according to the present invention includes an n-th (≧ 1) -order delta-sigma modulator (hereinafter, referred to as DSM) having n-stage integrators.
An encoder for reducing a bit rate of a 1-bit signal based on a state variable of each integrator.

Since the continuation of the signal depends on the processing performed on the signal, the encoding of the 1-bit signal can be performed efficiently based on information of a processing device that generates the 1-bit signal. D expressed as a value accumulated in the integrator of the DSM
Coding can be performed efficiently by using the SM state variables.

In the embodiment, the power of the quantization noise is spread over a wider band by increasing the sampling frequency of the 1-bit signal, and the noise in the signal band is reduced. In an embodiment, the encoder encodes a 1-bit signal with a higher sampling frequency to reduce the data amount of the 1-bit signal. This reduces, for example, the storage required to record the signal on a tape or disk, or the bandwidth required to transmit the signal on the transmission channel.

Another one-bit signal processing device according to the present invention is a signal processing means for processing a one-bit signal, an encoder for compressing the processed signal based on a state variable of the signal processing means, and a connection to the encoder. Transmission channel and / or storage means for receiving the processed and encoded signal.

The present invention is based on the new recognition that compression is possible regardless of its random nature. Embodiments of the present invention relate to data sources that can be used to control compression.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a 1-bit signal processing device according to the present invention will be described in detail with reference to FIGS. As shown in FIG. 4A, a 1-bit signal is supplied to the encoder 40 via the input terminal 44. The encoder 40 compresses the bitstream by dividing the bitstream into n-bit words and encoding the words based on the probability of occurrence of the words. The occurrence probability is evaluated by the histogram circuit 41, and the histogram circuit 41 creates a histogram of word occurrence frequencies. The encoded bit stream is supplied to a channel 42 such as a tape recorder, a disc player, and a transmission channel. By encoding a 1-bit signal, the required recording capacity or bandwidth of a recording medium can be reduced. The decoder 43 and the histogram circuit 46 decode the coded word supplied from the channel 42 by the reverse process corresponding to the coding process. Histogram circuit 41 creates a table in which the supplied uncompressed n-bit words are mapped to less than the corresponding compressed n-bit words.

As shown in FIG. 4B, encoding is performed on mutually exclusive sets of n bits. As shown in FIG. 4B, the bit stream of the 1-bit signal is divided into sets a, b, and c, each consisting of n bits. The encoder 40 and the histogram circuit 41 perform encoding on, for example, first the first set a, then the second set b, and then the third set c.

As shown in FIG. 4C, the encoding is performed on a contiguous set of n bits in a window W having a width of n bits. The bit stream is the window W
Flows continuously through Therefore, FIG. 4Ci, FIG.
As shown in i, the set of n bits is encoded, then the bit stream moves by one bit, and the next set of n bits, including the n-1 bits of the immediately preceding set, is encoded.

As shown in FIG. 4D, the width of the window W may be Q bits larger than n,
Is encoded based on the bits of the previous contiguous set of n bits. As shown in FIG. 4E, the encoding is predictive, and the next (M + 1) th bit is predictively encoded based on the M bits.

As shown in FIG. 5, the 1-bit signal is a delta-sigma modulator (hereinafter referred to as DSM).
And related applications (UK Application No. 9624674.9 (I-
96-16), 9624671.5 (I-96-2)
4), 9624673.1 (I-96-25), Patent Attorney No. P / 1508GB, P / 1509GB, P / 151
0GB) by a delta-sigma modulator. The DSM includes at least one integrator 71, 72 as shown in FIG.
And a delay unit 51 that delays the output of the adder 52 by a unit time and feeds it back to the adder 52. Then, the adder 52 accumulates (integrates) the one-bit signal. The value of the adder 52 of each integrator 71 is a DSM state variable.
In this embodiment, the state variables are supplied to the encoder 53 and subjected to an encoding process. The encoder 53 is a DSM
Compresses the bitstream based on the state variables of
The coded bit stream is transmitted by a channel 42 to a decoder 54 that reproduces the original 1-bit signal, and information for decoding is superimposed on the coded bit stream.

As shown in FIG. 6, the sampling frequency of the 1-bit signal supplied through the input terminal 60 is 64
f _s . Here, f _s is a standard sampling frequency of the digital audio signal, and f _s = 44.1 k
Hz or 48 kHz. The up-converter 61
And inserting with overlapping sample values in the bit stream by inserting the sample values of 0, increasing the sampling frequency for example 128f _s. By increasing the sampling frequency, the noise power is spread over a wide band.

In the specific example of FIG. 6, a one-bit signal is processed by one or more DSMs 62 and 63 connected in cascade, and the data of the DSM 34 is compressed in order to compress the data as described with reference to FIG. Encoder 6 based on state variables
4. The encoded signal is supplied to the channel 42 in the same manner as described with reference to FIG.

The signal reproduced by the channel 42 is decoded by a decoder corresponding to the encoder 64.
FIG. 7 is a diagram showing a configuration of an audio signal processing system to which encoding and decoding are applied according to an embodiment of the present invention. In FIG. 7, a 1-bit audio signal is, for example, a D signal shown in FIG.
It is supplied to a signal processor 70 using SM. The encoder 71 for compressing the bit stream operates in cooperation with the signal processor 70, and the compression is controlled by the state variables of the signal processor 70. Then, the compressed data stream is supplied to the transmission channel and / or the storage device 72. The compressed data stream is recovered from the transmission channel and / or storage device 72, decoded by the decoder 73, and further processed by the processor 74.

The efficiency of the encoding is increased by operating the encoder 71 in conjunction with the processor 70. In the prior art applied to an n-bit signal where n >> 1, the encoding at the encoder 71 is not related to the processing at the processor 70, and instead the encoding and decoding is performed at the processor 70 The processing is performed in the transmission channel and / or the storage device 72 regardless of the processing.

Here, the encoders 40, 41, 53,
64 and the decoders 43, 46, 54, 65 will not be described in detail. These are the technical categories of coding and decoding experts for data reduction. An example of an encoder and decoder is GB-A-1023029 (IBM) which shows a predictive encoder that predicts consecutive N bits following an M bit sequence with a continuous M bit sequence.
U.S. Pat. No. 4,516,246 (Prentice Corporation), which has shown that a character-based input data stream is encoded in a compressed form using a histogram of data stream samples to determine the frequency of occurrence of characters in the stream. Corporation)). The code for character M + 1 is generated at the encoder and its length is the inverse of the frequency of occurrence of character M + 1 in the previous M characters in the sample. Decoding is achieved by forming a comparable sample window in the decoder to which the estimated index of the input character to be decoded is applied.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conventional delta-sigma modulator.

FIG. 2 is a block diagram showing a configuration of a conventional delta-sigma modulator configured as an n-order filter.

FIG. 3 is a diagram illustrating noise removal characteristics.

FIG. 4A is a schematic block diagram of an encoding / decoding device according to an embodiment of the present invention, and B to E are a signal diagram and a window diagram showing a set of bits used in the embodiment of the present invention. It is.

FIG. 5 is a schematic block diagram of another encoding / decoding device according to an embodiment of the present invention.

FIG. 6 is a schematic block diagram of still another encoding / decoding device according to an embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a signal processing system according to the present invention.

FIG. 8 is a block diagram showing a configuration of a delta-sigma modulator configured as a fifth-order filter.

 ──────────────────────────────────────────────────続 き Continuation of the front page (31) Priority claim number 9624673 1 (32) Priority date November 27, 1996 (33) Priority claim country United Kingdom (GB) (31) Priority claim number 97246621.9 (32) ) Priority date November 20, 1997 (33) Priority country United Kingdom (GB) (72) Inventor Easty Peter Charles Katy 130 UK Exda Brewery Sally Weybridge Brooklands The Heights (No Address) Sonny United Kingdom Within the Limited (72) Inventor Slight Christopher Katy 130 UK Exda Brewery Sally Weybridge Brooklands The Heights (No Address) Sony United Kingdom Limited The inner (72) inventor soap Peter Damian UK Katie 13 0 Ekkusuda Brieuc Surrey Weybridge Bull Kkuranzu The Heights (no address) Sony United Kingdom Rimite Tsu in the de

Claims (14)

[Claims] 1. A stream of a 1-bit signal is represented by n (>>)
1) A signal processing apparatus comprising: a dividing unit that divides a word into bits; and an encoding unit that encodes the n-bit word into an encoded word having a smaller number of bits than n bits. 2. The signal processing apparatus according to claim 1, wherein said word is encoded based on its occurrence probability. 3. The signal processing apparatus according to claim 2, further comprising a histogram generation unit configured to generate a histogram of the occurrence frequency of the word, wherein the encoding unit encodes the word based on the histogram. 4. The signal processing apparatus according to claim 1, wherein said n-bit word is composed of mutually exclusive sets of n bits. 5. The method according to claim 1, wherein said dividing means comprises a window through which said stream of 1-bit signals passes continuously, and each word comprises a bit in said window.
The signal processing device according to claim 1. 6. The dividing means comprises a window through which the stream of 1-bit signals passes continuously, wherein the window has a length of Q bits where Q is greater than n, and each window has a length of Q bits. The signal processing apparatus according to claim 1, wherein a word is a subset of the Q bits, and is encoded depending on other Qn bits in a window before and after the n-bit word. 7. The method of claim 1, wherein n-1 bits of each word are used to predict the nth bit of said word.
A signal processing device according to claim 1. 8. An n (≧ 1) order delta-sigma modulator (DSM) having n stages of integrators, and an encoder for reducing a bit rate of a 1-bit signal based on a state variable of the integrator. A signal processing device comprising: 9. The apparatus according to claim 1, further comprising means for increasing a sampling frequency of the one-bit signal, wherein the DSM processes the one-bit signal having the increased sampling frequency, and the encoder reduces a data amount of the one-bit signal. Item 10. The signal processing device according to Item 8. 10. A signal processing apparatus for decoding a 1-bit signal encoded by the signal processing apparatus according to claim 1, wherein the signal comprises decoding means for decoding an encoded word. Processing equipment. 11. The signal processing apparatus according to claim 10, further comprising a histogram generation unit that generates a histogram of the frequency of occurrence of the encoded word, wherein the decoding unit decodes the encoded word based on the histogram. . 12. A signal processing means for processing a 1-bit signal, an encoder for compressing a processed signal based on a state variable of the signal processing means, and a signal processed and encoded connected to the encoder. 1-bit signal processing system comprising: 13. The apparatus of claim 12, further comprising: a decoder for expanding the encoded one-bit signal received from the transmission channel and / or the storage means; and means for utilizing the expanded one-bit signal. 1-bit signal processing system. 14. An audio signal processing device comprising the signal processing device or system according to claim 1.