JPH1188056A - Direct digital frequency synthesizer, phase synchronizing frequency synthesizer, and transmitting and receiving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low spurious and compact direct digital frequency synthesizer, etc. SOLUTION: This frequency synthesizer 100C contains a phase accumulator 10 and a phase/amplitude conversion means 20C. The accumulator 10 accumulates the inputted frequency setting data and outputs the phase data (θ1 +θ2 ) as its accumulation result. A memory 21B of the means 20C outputs the amplitude data (sin (2πθ1 )) on a sine wave based on a higher order bit (θ1 ) of the phase data. An amplitude correction value calculation means 22A calculates the amplitude correction value (cos (2πθ1 ).(2πθ2 )) based on the coefficient that is used to an approximation means of the cosine wave corresponding to the bit (θ1 ) and also on the bit (θ1 ) and a lower order bit (θ2 ) and outputs this calculated correction value. Then an adder 23 adds together the amplitude data (sin (2πθ1 )) on a sine wave and the correction value (cos (2πθ1 ).(2πθ2 )) and outputs this addition result. As a result, the size and the cost of the synthesizer 100C can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct digital frequency synthesizer (hereinafter, abbreviated as "DDS") used in a transmission / reception apparatus of a wireless communication system. In particular, the present invention relates to a DDS that achieves miniaturization and low spurious. In addition, a phase-locked frequency synthesizer using the DDS as a reference oscillator (hereinafter referred to as “PLL”).
Synthesizer ". ). Further, the present invention relates to a transmission / reception device using the DDS or PLL synthesizer as a reference oscillator.

[0002]

2. Description of the Related Art In the following description, “Θ” or “θ” is used as a symbol representing phase data. The “Θ” or “θ” is a discrete value ranging from 0 to 1.

A conventional DDS (direct digital frequency synthesizer) will be described with reference to FIGS. 12, 13 and 14. FIG. FIG. 12 shows, for example, the IEEE 35th. Ann. Frequency Control Sympos held in May 1981.
A. published in pages 406 to 414 of the ium papers.
FIG. 2 is a block diagram showing a configuration of a conventional DDS shown in L. Bramble, “Direct Digital Frequency Synthesis”.
FIG. 13 is a diagram illustrating a relationship between an error due to the termination of the phase data and spurious. FIG. 14 is a diagram showing the relationship between the spurious level and the memory capacity with respect to the word length of the phase data.

In FIG. 12, 100 is a DDS (direct digital frequency synthesizer), 200 is a reference clock (f _ck ), and 300 is frequency setting data setting means.

In FIG. 1, reference numeral 10 denotes a phase accumulator, 20 denotes a phase / amplitude conversion means, and 30 denotes a digital signal.
-Digital-Analog Converter
AC ”. ). Furthermore, in general, the phase
The amplitude conversion means 20 includes a sine wave memory 21 in which phase data is used as an address and sine wave amplitude data is stored.
Is used.

In the DDS 100, first, the phase accumulator 10 accumulates frequency setting data k (word length L bits). This accumulation result (word length L bits)
Are output as phase data Θ. Next,
In the sine wave memory 21, the sine wave amplitude data s
in (2πΘ) (word length N bits). Then, it is converted into an analog waveform in the DAC 30 (output frequency f _d ). The above digital operation is performed using the reference clock 2
This is performed in synchronization with 00.

The output frequency f of the DDS 100 shown in FIG.
_d is given by the following equation (1). Here, f _ck is the output frequency of the reference clock 200.

F _d = k · f _ck / 2 ^L (1)

As is clear from equation (1), this DD
In S100, by increasing the word length of the frequency setting data k to multiple bits, high frequency resolution can be easily obtained without deteriorating other characteristics. In DDS100,
Since the output wave is generated by digital operation, there is an advantage that the frequency can be changed at high speed.

The capacity S of the memory 21 of the DDS 100 is given by the following equation (2). Here, M is the word length of the phase data Θ, and N is the word length of the sine wave amplitude data.

S = 2 ^M · N (bits) Equation (2)

For example, if M = 14 bits and N = 12 bits, S ≒ 197 kbit. Therefore, DDS
The memory 21 becomes dominant for a chip size of 100. Therefore, in order to reduce the chip size and cost, it is necessary to reduce the capacity S of the memory 21.

In order to reduce the capacity S of the memory 21, the DDS 100 (word length M of the phase data Θ) <
(Word length L of frequency setting data k). As a result, a truncation error occurs in the phase data 生 じ る as shown in FIG. Then, spurious noise due to the truncation error as shown in FIG. FIG. 14 shows the relationship between the spurious level and the memory capacity with respect to the word length M of the phase data Θ. As can be seen from FIG.
The spurious level and the memory capacity have a conflicting relationship, and the word length M of the phase data Θ is determined in consideration of these.

One of the techniques for alleviating the spurious and suppressing the capacity of the memory 21 is described in 49 of the papers of the IEEE Journal of Solid State Circuits held in August 1984.
DASunderland, "C, published on pages 7 to 505
MOS / SOS Frequency Synthesizer LSI Circuit for Spre
ad Spectrum Communications ". In this method, the memory capacity is reduced by using the symmetry relationship of every 90 degrees of the sine wave. FIG. 15 shows another conventional method using this method. 1 shows the configuration of the DDS.

In FIG. 15, 100A is a DDS (direct digital frequency synthesizer), and 300 is frequency setting data setting means.

In the same figure, 10 is a phase accumulator, 20A is a phase / amplitude conversion means, 30 is a DAC,
40 and 50 are one's complement arithmetic means. In the figure, FIG.
The same or corresponding parts are denoted by the same reference numerals.

Further, the memory of the phase / amplitude conversion means 20A stores amplitude data corresponding to a phase of 0 to 90 °, and stores amplitude data corresponding to a phase of 0 to 360 °. The memory capacity of the memory 21 becomes 1/4.

Next, the operation of the DDS 100A shown in FIG. 15 will be described. The DDS 100A shown in FIG. 15 accumulates frequency setting data k (word length L bits) in the phase accumulator 10, similarly to the DDS 100 shown in FIG. Then, it outputs the upper bit Θ (word length M bits) of the accumulation result (word length L bits). The upper two bits of this Θ are output to one's complement arithmetic means 40 and one's complement arithmetic means 50, respectively.

In the one's complement operation means 40, the lower bits Θ ′ (= Θ−Θ ″) of Θ and the least significant bit (L
SB), the time waveform 2 shown in FIG. 15 is converted into the time waveform 3. Next, the phase / amplitude conversion means 20A converts Θ ′ into sine wave amplitude data sin (2π （′) (word length N−1 bits). Then, in the one's complement operation means 50, the sine wave amplitude data sin (2π
From the most significant bit (MSB) of Θ ′) and Θ ″, conversion from the time waveform 4 of FIG. 15 to the time waveform 5 is performed. The converted data is used as the output data of DDS100A,
At 0, it is converted to an analog waveform. Although not shown in FIG. 15, the above digital operation is performed using the reference clock 200
It is performed in synchronization with.

Further, in the method of DASunderland's document, the capacity of the memory used for the phase / amplitude calculation means is further reduced while suppressing the occurrence of spurious signals by using an approximate expression of a sine wave. FIG. 16 shows another configuration of another conventional DDS when an approximate expression of a sine wave is used.

In FIG. 16, 100B is a DDS (direct digital frequency synthesizer), and 300 is frequency setting data setting means.

In the same figure, 10 is a phase accumulator, 20B is a phase / amplitude conversion means, 30 is a DAC,
40 and 50 are one's complement arithmetic means. In the figure, FIG.
15 and the same or corresponding parts are denoted by the same reference numerals.

Further, in the figure, 21A represents θ ₁ and θ ₂
Are used as addresses, and sine wave amplitude data sin (2πθ
₁ + _{2πθ 2)} sine wave memory being stored, 22 as an address and theta ₁ and theta _3, amplitude correction data cos (2
πθ ₁ ) · sin (2πθ ₃ ) is stored in the memory for amplitude correction values, and 23 is an adder.

Next, an approximate expression of a sine wave used in the DDS 100B of FIG. 16 is shown. The upper bit of the phase data Θ ′ (word length M−2 bits) in the output of the one's complement arithmetic means 40 is θ ₁ (word length M ₁ bit), the middle bit is θ ₂ (word length M ₂ bits), and the lower bit is Assuming that the bits are θ ₃ (word length M ₃ bits), the relationship of θ ₁ ≫θ ₂ ≫θ ₃ is satisfied, so that the sine wave sin (2πΘ ′) can be approximated by the following equation (3). In the phase / amplitude calculation means 20B shown in FIG. 16, the capacity of the memory is reduced by using this approximate condition.

Sin (2πΘ ′) = sin (2πθ ₁ + 2πθ ₂ + 2πθ ₃ ) ≒ sin (2πθ ₁ + 2πθ ₂ ) + cos (2πθ ₁ ) · sin (2πθ ₃ ) Equation (3)

Next, the operation of the phase / amplitude calculation means 20B shown in FIG. 16 will be described. First, the upper M ₁ bits, middle M ₂ bits, and lower M ₃ bits of the output data Θ ′ of the one's complement arithmetic means 40 are phase data θ ₁ , θ ₂ , and θ ₃ , and the sine wave memory 21A and the amplitude correction The data is output to the value memory 22. Next, in the sine wave memory 21A,
Let θ ₁ and θ ₂ be sine wave amplitude data sin (2πθ ₁ + 2π
θ ₂ ) (word length N bits). Further, in the amplitude correction value memory 22, θ ₁ and θ ₃ are converted into amplitude data of the amplitude correction value cos (2πθ ₁ ) · sin (2πθ ₃ ).
(Word length N bits). And the adder 23
, Sin (2πθ ₁ + 2πθ ₂ ) and cos (2π
θ ₁ ) · sin (2πθ ₃ ) and outputs the added data to the one's complement arithmetic means 50. Although not shown in FIG. 16, the above digital operation is performed using the reference clock 200
It is carried out in synchronization with.

Next, an example of calculation of the effect of memory reduction by the configuration of FIG. 16 will be described. At this time, the maximum value of the spurious level due to the termination of the phase data is -72d.
DDS having the configuration shown in FIGS. 12 and 16 so as to be about Bc.
To design. In the case of the DDS 100 of FIG. 12, M = 1
With 2 bits and N = 10 bits, the memory becomes $ 41 kbit. On the other hand, in the case of DDS100B in FIG. 16, M ₁
= 4 bits, M ₂ = 4 bits, M ₃ = 4 bits, N = 10
In bits, the memory is $ 5.1 kbit. Therefore, the DDS 100B of FIG. 16 has an effect that the memory capacity is reduced to 1/8 of that of the DDS 100 of FIG.

[0028]

The DDS 100 shown in FIG.
B is 1/8 the memory capacity of the DDS 100 of FIG.
Can be reduced to However, if the number of bits of the phase data Θ is increased in order to further suppress spurious due to the phase data truncation error, the number of bits of the addresses of the memories 21A and 22 is also increased. Therefore, there is a problem that the capacities of the memories 21A and 22 increase in proportion to the power of two.

As another method of generating a sine wave, C
There is a method using a digital operation such as an ORDIC algorithm. With this method, it is possible to reduce the capacity of the memory. However, when the number of bits of the phase data 化 is increased in order to reduce the spurious, there is a problem that the processing time of the DDS increases because the scale of the arithmetic circuit increases and the amount of operation increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a direct digital frequency synthesizer, a phase-locked frequency synthesizer, and a transceiver capable of reducing the size of a circuit and reducing spurs. The aim is to obtain a device.

[0031]

According to the present invention, there is provided a direct digital frequency synthesizer comprising: a phase accumulator for accumulating input frequency setting data and outputting an accumulation result as phase data (θ ₁ + θ ₂ ); Based on the upper bit (θ ₁ ) of the sine wave (sin (2
πθ ₁ )), a coefficient used for the approximation means of the cosine wave corresponding to the upper bit (θ ₁ ) of the phase data, and the upper bit (θ ₁ ) and lower bit (θ ₂ ) of the phase data. Amplitude correction value (cos (2πθ ₁ )
Amplitude correction value calculating means for calculating and outputting (2πθ ₂ )), amplitude data (sin (2πθ ₁ )) of the sine wave and the amplitude correction values (cos (2πθ ₁ ) · (2πθ ₂ ))
And a phase / amplitude conversion means having an adder for adding and outputting.

Further, in the direct digital frequency synthesizer according to the present invention, the amplitude correction value calculating means outputs a coefficient used as a cosine wave approximating means corresponding to the upper bit (θ ₁ ) of the phase data; Cosine wave calculating means for calculating and outputting an amplitude correction value (cos (2πθ ₁ )) based on the coefficient and the upper bit (θ ₁ ) of the phase data, and amplitude correction based on the lower bit (θ ₂ ) of the phase data and 2πθ2 calculating means for calculating output values (2πθ _2), it is intended to include a multiplier for multiplying the amplitude compensation value (cos (2πθ ₁₎₎ and said amplitude correction value (2πθ _2).

Further, in the direct digital frequency synthesizer according to the present invention, the amplitude correction value calculating means includes a lower bit truncating means for outputting an upper bit (θ ₁ ) of the upper bit (θ ₁ ) of the phase data; a memory for outputting a coefficient used for the approximation means of the cosine wave corresponding to the upper bits of the upper bits (theta _1), said coefficients and amplitude correction value based on the upper bits (theta ₁₎ of the phase data (c
os (2πθ ₁ )), a cosine wave calculating means for calculating and outputting an amplitude correction value (2πθ ₂ ) based on the lower bits (θ ₂ ) of the phase data, and a 2πθ2 calculating means for calculating and outputting the amplitude correction value (2πθ ₂ ). cos (2πθ ₁ )) and the amplitude correction value (2πθ ₂ ).

Further, in the direct digital frequency synthesizer according to the present invention, the 2πθ2 calculating means calculates and outputs (8 · θ ₂ ) based on the lower bit (θ ₂ ) of the phase data; Output (8 · θ ₂ )
And a plurality of lower bit truncating means for respectively outputting the upper bits of the above, and an adder for adding outputs of the plurality of lower bit truncating means.

Further, in the direct digital frequency synthesizer according to the present invention, the multiplier may be arranged so that the amplitude correction value (2
a plurality of lower bit truncation means for outputting the upper bits of the [pi] [theta] _2), a plurality of switches through or blocks the upper bits of the amplitude correction value (cos (2πθ ₁₎ the amplitude correction value based on) (2πθ ₂₎ , And an adder for adding the upper bits of the amplitude correction value (2πθ ₂ ) passed through the plurality of switches.

Further, in the direct digital frequency synthesizer according to the present invention, the multiplier outputs a plurality of lower bit truncating means for outputting upper bits of the amplitude correction value (cos (2πθ ₁ )); 2π
a plurality of switches through or blocks the upper bits of the amplitude correction value on the basis of _{θ 2) (cos (2πθ 1} )),
The amplitude correction value (cos) passed through the plurality of switches
(2πθ ₁ )).

A phase-locked frequency synthesizer according to the present invention is a phase-locked frequency synthesizer comprising a voltage-controlled oscillator, a variable frequency divider, a phase comparator, and a loop filter. With a direct digital frequency synthesizer.

The transmitting and receiving apparatus according to the present invention receives a received wave in a high frequency band with a receiving antenna, converts the frequency of the received wave into an intermediate frequency band by using a receiving mixer, and transmits the transmitted wave in the intermediate frequency band. A transmission / reception device which converts the frequency to a high frequency band with a transmission mixer and transmits the same with a transmission antenna, comprising the direct digital frequency synthesizer according to any one of the above, as a reference oscillator of the reception mixer and the transmission mixer. It is.

Further, the transmitting and receiving apparatus according to the present invention receives a received wave in a high frequency band with a receiving antenna, converts the received wave into an intermediate frequency band using a receiving mixer, and converts the received wave into an intermediate frequency band. A transmission / reception device that converts a transmission wave into a high-frequency band with a transmission mixer and transmits the converted wave with a transmission antenna, comprising the above-described phase-locked frequency synthesizer as the reception mixer and the reference oscillator of the transmission mixer. .

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 shows a direct digital frequency synthesizer (DDS) according to Embodiment 1 of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG. In the drawings, the same reference numerals indicate the same or corresponding parts.

The DDS 10 according to the conventional configuration shown in FIG.
0B, the amplitude correction value cos (2π
θ ₁ ) · sin (2πθ ₃ ) ≪sine wave sin (2πθ ₁ +
Note that 2πθ ₂ ). That is, the amplitude correction value cos (2πθ ₁ ) · sin (2πθ ₃ ) is a sine wave si
This value is sufficiently smaller than n (2πθ ₁ + 2πθ ₂ ), and does not significantly contribute to the accuracy of the amplitude data of the sine wave sin (2πθ ₁ ).

Therefore, in the first embodiment, the calculation of the amplitude correction value is more roughly approximated, so that the capacity of the memory used for the DDS is reduced by using a digital arithmetic unit having a simple configuration. That is, the first embodiment is different from FIG.
6 is an invention about simplification of the phase / amplitude conversion means 20B.

In FIG. 1, reference numeral 100C denotes a DDS (direct digital frequency synthesizer), and 300 denotes frequency setting data setting means.

In the same figure, 10 is a phase accumulator, 20C is a phase / amplitude conversion means, and 30 is a DAC.

Further, in the same figure, 21B is a sine wave memory, 22A is an amplitude correction value calculating means, and 23 is an adder. Further, reference numeral 24 denotes a memory storing coefficients used for a cosine wave calculating means described later, 25 denotes a cosine wave calculating means, 26
Is a 2πθ2 calculating means, and 27 is a multiplier. In this figure, a memory 21 is used as a means for calculating a sine wave sin (2πθ ₁ ).
B is used.

Next, an approximate expression of a sine wave used in the DDS 100C shown in FIG. 1 is shown. Phase accumulator 10
Is the upper bit of the output data of θ ₁ (word length M ₁ bit)
And the lower bit is θ ₂ (word length M ₂ bits),
1> θ ₁ ≫θ ₂ and the sine wave sin (2πθ ₁ + 2π
θ ₂ ) can be approximated by the following equation (4). Where cos
(2πθ ₂ ) ≒ 1 and sin (2πθ ₂ ) ≒ 2πθ ₂
Is used.

[0047] _{sin (2πθ 1 + 2πθ 2)} = sin (2πθ 1) · cos (2πθ 2) + co s (2πθ 1) · sin (2πθ 2) ≒ sin (2πθ 1) + cos (2πθ 1) · (2 πθ 2・ ・ ・ ・ ・ ・ Equation (4)

Next, the operation of the first embodiment will be described. In the DDS 100C, first, the phase accumulator 10 accumulates frequency setting data k (word length L bits). This accumulation result (word length L bits)
Upper M ₁ bit theta _1, the lower bits M ₂ bits and theta _2, the sine wave memory 21B of the phase-amplitude conversion means 20C of
And the amplitude correction value calculating means 22A.

Next, in the sine wave memory 21B, the theta ₁ as input data, the sine wave amplitude de - data sin
(2πθ ₁ ) (word length N bits). Also,
In the memory 24, θ ₁ is used as input data, and the coefficients α ₀ , α ₁ ,..., Α _n for cosine wave calculation means are output to the cosine wave calculation means 25. The arithmetic means 25 converts the coefficients α ₀ , α ₁ ,..., Α _n and θ ₁ as input data and converts them into cosine wave amplitude data cos (2πθ ₁ ) (word length N bits). On the other hand, the amplitude correction value calculation means 22A
In πθ2 calculating means 26 converts the theta ₂ in (2πθ ₂₎ (word length N bits).

Then, the multiplier 27 of the amplitude correction value calculation means 22A multiplies cos (2πθ ₁ ) by (2πθ ₂ ), and obtains the amplitude correction value cos (2π
θ ₁ ) · (2πθ ₂ ) is output to the adder 23. Next,
In the adder 23, sin (2πθ ₁ ) and cos (2
πθ ₁ ) · (2πθ ₂ ) and outputs the result as output data of the DDS 100C. Finally, in DAC 30,
Convert to analog waveform. Although not shown in FIG. 1, the above digital operation is performed in synchronization with the reference clock 200.

The cosine wave calculating means 25 in FIG. 1 simplifies the calculation of the cosine wave cos (2πθ ₁ ) by dividing θ ₁ into a plurality of sections and linearly approximating the cosine wave in the section. I have. performing the calculation of the cosine wave with a rough approximation, such as a straight line in each section of the theta _1. That is, accurate calculations can be performed without using polynomial series expansion. The approximation described here is, for example, a first-order approximation to the phase data θ ₁ (cos (2πθ ₁ ) ≒ α ₀ + α ₁ · θ ₁ , n = 1)
And

FIG. 2 shows a cosine wave c for the phase data θ ₁ .
An example of approximation of a cosine wave when os (2πθ ₁ ) and θ ₁ are divided into five sections will be described. In the figure, the dotted line represents the amplitude waveform of the cosine wave before approximation, and the solid line represents the amplitude waveform of the cosine wave after approximation.

FIG. 3 shows an example of the correspondence between the phase data θ ₁ and the coefficients α ₀ and α ₁ used in the cosine wave calculating means 25.
The phase data θ ₁ is an address of the memory 24,
Coefficients α ₀ and α ₁ corresponding to θ ₁ are stored in the memory 24. FIG. 3 shows that the above-mentioned phase data θ ₁ is θ ₁
Code corresponding to 000000,0000001,.
.. represented by 1111111 (this becomes an address of the memory 24), and a coefficient α ₀ corresponding to each of them.
And α ₁ . For example, if the phase data is θ ₁ = 00
0000, the address 0000 of the memory 24
000 is specified. When θ ₁ = 00000000, α ₀ = 1 and α ₁ = 0 are output.

By obtaining the coefficients using the memory 24 in this manner, the processing time can be reduced as compared with the method of performing calculations. That is, the time required for changing the frequency setting data can be reduced. Therefore, DDS100
This has the effect of increasing the frequency switching speed of C.

In FIG. 2, the number of sections divided by θ ₁ is five. However, the greater the number of sections, the more accurate cosine waves can be obtained. Therefore, the number of sections to be divided into θ ₁ is 5 or more (maximum 2 ^M1-1 : the power is M
May be a ₁ -1), it exhibits the same or more effects.

In the above description, the approximation of the cosine wave is a first-order approximation. However, the same or more effects can be obtained by using a polynomial approximation.

Although FIG. 1 does not use the symmetrical relationship of the sine wave at every 90 °, it can be applied.
In this case, the phase / amplitude conversion means 20C in FIG. 1 may be replaced with the phase / amplitude conversion means 20B in FIG. The replacement has the effect of reducing the capacity of the memory to 1/4 as in the conventional case.

Furthermore, the above description does not limit the specific hardware configuration of the cosine wave calculating means 25. However, even if the hardware is a logic circuit or a memory,
A process based on software such as a DSP or a CPU may be used, and the same effect is obtained.

Embodiment 2 In the first embodiment, the coefficients α ₀ and α ₁ corresponding to the phase data θ ₁ are stored in the memory 24. However, if the bit length of the phase data θ ₁ is 16 bits, about 66 k × coefficient α
A word length (bit) capacity of ₀ and α ₁ is required. Second embodiment is to solve the problems relating, in which thinning the address of the memory 24 by using the upper bits of the phase data theta _1.

Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 4 shows a direct digital frequency synthesizer (D) according to Embodiment 2 of the present invention.
FIG. 3 is a block diagram showing a configuration of DS).

In FIG. 4, reference numeral 28 denotes a means for terminating the lower bits of the phase data θ ₁ . In the figure, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals.

Next, the operation of the second embodiment will be described. In the amplitude correction value calculating means 22B of the second embodiment, the lower-order bit cutoff means 28 uses the phase data θ ₁ as input data and stores the upper-order bits of θ _{1 in} the memory 24.
Output to In this memory 24, the phase data θ ₁
And outputs coefficients α ₀ and α ₁ corresponding to the upper bits of.

FIG. 5 shows addresses of the memory 24 and internal values. As shown in FIG. 5, the memory 24 stores coefficients α ₀ and α ₁ having the upper bit of θ ₁ as an address. Although not shown in FIG. 4, the above digital operation is performed in synchronization with the reference clock 200.

The coefficient α ₀ using the upper bits of the phase data θ ₁
And by performing the selection of alpha _1, it is possible to reduce the capacity of the memory. For example, if the word length of the phase data θ ₁ is 1
In the case of 6 bits, the required memory capacity is about 66 k × the word length (bits) of the coefficients α ₀ and α ₁ , but if the word length is set to θ ₁ of 6 bits, the required memory capacity is 6 bits.
The word length (bit) is 4 × coefficient α ₀ and α ₁ . As described above, by reducing the memory capacity, a low-cost memory can be used, so that manufacturing cost can be reduced. Further, as in the first embodiment, since the coefficient is extracted using the memory in this manner, the processing time can be reduced as compared with the method of performing the calculation. That is, the time required for changing the frequency setting data can be reduced. Therefore,
This has the effect of increasing the frequency switching speed of the DDS 100D.

Next, an example of calculation of the effect of memory reduction by the configuration of FIG. 4 will be described. At this time, the maximum value of the spurious level due to the termination of the phase data is set to -72 dB.
The DDS 100D having the configuration shown in FIG. 4 is designed to be about c. When the amplitude correction value calculation means 22B of the DDS 100D shown in FIG.
0.4 k bits. This has the effect of halving the memory of the DDS 100B in FIG. 16 when the symmetrical relationship of every 90 ° of the sine wave is not used. Therefore, there is an effect that the cost is reduced.

The above description does not limit the specific hardware configuration of the digital operation. However, even if the hardware is a logic circuit or a memory, the processing is based on software such as a DSP or a CPU. The same effect may be obtained.

Embodiment 3 Embodiment 3 of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration of 2πθ2 calculating means of a direct digital frequency synthesizer (DDS) according to Embodiment 3 of the present invention.

2πθ of the DDS of the first and second embodiments
The two operation means 26 multiplies θ ₂ by 2π. In general, since the amount of processing performed by the multiplier is large, it is difficult to operate the synthesizer at high speed.

The third embodiment solves such a problem. In the third embodiment, showing the 2πθ2 calculating means with a reduced amount of processing operations by performing an approximation of 2π · θ _2. An approximate expression of 2π · θ ₂ used in the third embodiment is shown below.

[0070] _{2π · θ 2 ≒ 8 · {} (θ 2/2) + (θ 2/4) + (θ 2/32) + (θ 2/256) + (θ 2/4096)} ··· formula (5)

In FIG. 6, reference numeral 26A denotes 2πθ2 calculating means in the amplitude correction value calculating means.

In the same figure, reference numeral 26a denotes 8θ2 calculating means, 26b, 26c, 26d, 26e, and 26f denote lower bit truncating means, and 26g denotes an adder.

Next, the operation of the third embodiment will be described. DDS 2πθ2 calculation means 26 according to Embodiment 3
In A, the phase data θ is calculated by the 8θ2 calculating means 26a.
₂ as input data, and outputs the output data 8Shita ₂ low-order bits truncation means 26B～26f. Performs truncation of lower bits of the lower bit truncation unit in 26b~26f 8θ _2, the adder 26g upper bits of 8Shita ₂
Output to The adder 26g adds the output data of the lower-order bit termination means 26b to 26f. Although not shown in FIG. 6, the above digital operation is performed in synchronization with the reference clock 200.

In the synthesizer having this configuration, since an arithmetic circuit such as the lower-order bit truncation means 26b to 26f and the adder 26g which does not perform complicated arithmetic processing is used, the circuit scale of the 2πθ2 arithmetic means 26A and the amount of arithmetic processing are optimized. There is an advantage that can be achieved. Therefore, there is an effect that the cost is reduced.
In addition, since a memory or the like is not used, there is an effect that the size is reduced.

The above description does not limit the specific hardware configuration of the digital operation. However, even if the hardware is a logic circuit or a memory, the processing is based on software such as a DSP or a CPU. The same effect may be obtained.

Embodiment 4 Embodiment 4 of the present invention will be described with reference to FIG. FIG. 7 is a block diagram showing a configuration of a multiplier of a direct digital frequency synthesizer (DDS) according to Embodiment 4 of the present invention.

The amplitude correction value calculator 22A of the DDS 100C shown in FIG. 1 includes a multiplier 27 together with a cosine wave calculator 25 and a sine wave calculator (2πθ2 calculator 26). In general, since the amount of processing performed by the multiplier 27 is large, it is difficult to operate the synthesizer at high speed.

The fourth embodiment is to solve such a problem. In the fourth embodiment, a multiplier will be described in which the processing amount of the operation is reduced by using a lower bit truncation unit or an adder.

Next, a calculation formula of the multiplication used in the fourth embodiment will be described. Here, c _{n-1 to} c ₀ are cos (2π
θ ₁ ) is a coefficient (0 or 1) when represented by a binary number. Here, first, cos (2πθ ₁ ) is represented by a binary number, and rewritten as the second line of the equation (6). From this equation (6), by using the amplitude data of cos (2πθ ₁ ) as a switch control signal and adding 2πθ _{2 in} which the lower bits are cut off, a multiplier using lower bit cutoff means or an adder can be obtained. Can be configured.

[0080] _{cos (2πθ 1) · (2πθ} 2) ≒ (c n-1 · 2 n-1 + c n-2 · 2 n-2 + ··· + c 1 · 2 + c 0) · (2πθ 2) / 2 _{^{n = c n-1 · (}} 2 n-1 · 2πθ 2/2 n) + ··· + c 1 · (2 · 2πθ 2/2 n) + c 0 · (2πθ 2/2 n) ··· formula ( 6)

In FIG. 7, reference numeral 27A denotes a multiplier in the amplitude correction value calculating means.

In the same figure, 27a (27aa,
.., 27az) are lower-order bit termination means, 27b
(27ba,..., 27bz) are switches (SW),
27c is an adder.

Next, the operation of the fourth embodiment will be described. In DDS multiplier 27A according to the fourth embodiment, the lower bit truncation unit 27Aa～27az, as input data 2Paishita _2, and outputs the upper bits of 2Paishita ₂ to switch 27Ba～27bz. These switches 27ba to 27bz use cos (2πθ ₁ ) as a control signal. Then, the adder 27c adds and outputs the output data of the switches 27ba to 27bz.

In the multiplier 27A having this configuration, (2πθ ₂ )
To the control signals of the switches 27ba to 27bz,
os (2πθ ₁ ) is converted to lower-order bit truncation means 27aa to
The same effect can be obtained by inputting to 27az.

In the synthesizer of this configuration, the lower-order bit discontinuing means 27aa to 27az and the switches 27ba to 2
Since an arithmetic circuit that does not perform complicated arithmetic processing such as 7bz and the adder 27c is used, there is an advantage that the circuit scale of the multiplier 27A and the amount of arithmetic processing can be optimized. Therefore, there is an effect that the cost is reduced. Further, since a memory, a DSP, or the like is not used, there is an effect of downsizing.

The above description does not limit the specific hardware configuration of the digital operation. However, even if the hardware is a logic circuit or a memory, the processing is based on software such as a DSP or a CPU. The same effect may be obtained.

Embodiment 5 Embodiment 5 of the present invention will be described with reference to FIGS. 8 and 9 are diagrams showing a configuration of a phase-locked frequency synthesizer according to Embodiment 5 of the present invention.

In FIG. 8, reference numeral 400 denotes a DDS100C
(The DDS 100D of each of the above embodiments may be used.) A reference oscillator 500, frequency division number setting data setting means 500, and a PLL synthesizer (phase-locked frequency synthesizer) 600.

In the same figure, 610 is a phase comparator, 620 is a loop filter, 630 is a voltage controlled oscillator (hereinafter abbreviated as “VCO”), and 640 is a variable frequency divider.

As shown in FIG. 9, DDS 100C (100D,...), Reference clock 200, local oscillator 410, mixer 420,
Reference oscillator 4 including BPF 430 and amplifier 440
00A.

Next, the operation of the fifth embodiment will be described. In the PLL synthesizer having the configuration shown in FIG.
The PLL synthesizer 60 adjusts the frequency of the output wave of the VCO 630 divided by N by the variable frequency divider 640 to the frequency of the output wave of the reference oscillator 400 having the DDS 100C.
0 works. The output frequency f ₀ of the PLL synthesizer 600 is given by the following equation (7). Here, N is the frequency division number of the variable frequency divider 640.

F ₀ = N · f _d Equation (7)

In the synthesizer having the configuration shown in FIG. 8, the output frequency f ₀ of PLL synthesizer 600 is D
This is N times the output frequency f _d of the DS100C (N · f _d ). In the PLL synthesizer 600, the output frequency can be switched at intervals of f _d by changing the frequency division number N of the variable frequency divider 640 based on the frequency division number setting data. In the PLL synthesizer 600, the output frequency f _d can be switched at intervals of (N · f _ck / 2 ^L ) by changing the frequency setting data k of the DDS 100C.

Generally, in order to finely set the output frequency of the PLL synthesizer, the output frequency of the reference oscillator must be lowered. Accordingly, the variable frequency division number N
And the phase noise increases. But D
When the reference oscillator 400 having the DS 100C is used for the PLL synthesizer 600, the output frequency can be finely set by switching the frequency setting data of the DDS 100C. Therefore, the use of the PLL synthesizer having the configuration shown in FIG. 8 has the effects of reducing phase noise and speeding up frequency switching. Further, the use of the PLL synthesizer 600 has an effect that a high frequency that cannot be output by the DDS 100C can be generated.

Embodiment 6 FIG. Embodiment 6 of the present invention will be described with reference to FIG. FIG. 10 is a diagram showing a configuration of a transmitting and receiving apparatus according to Embodiment 6 of the present invention.

In FIG. 10, 710 and 720 are antennas, 711 and 721 are RF band amplifiers, 712 and 722 are RF band band-pass filters (RFBPF), 713 and 72.
3 is a mixer, 714 and 724 are IF band amplifiers, 715,
725 is an IF band pass filter (IFBPF). Reference numeral 400 denotes a reference oscillator having the DDS100C.

Next, the operation of the sixth embodiment will be described. In the receiving apparatus having the configuration shown in FIG. 10, a reception wave in a high frequency band is received by antenna 710. And
The frequency of the received wave is converted to an intermediate frequency band using mixer 713.

In the transmitting device, the transmission wave in the intermediate frequency band is frequency-converted by mixer 723 into a high frequency band.
Then, the signal is transmitted by the antenna 720.

In the transmission / reception apparatus shown in FIG.
Fine frequency conversion can be performed using the reference oscillator 400 (400A) having 0C. Therefore, the frequency channel step of the transmission / reception device can be narrowed, and there is an effect that economic efficiency is improved in terms of frequency utilization efficiency.

Embodiment 7 FIG. Embodiment 7 of the present invention will be described with reference to FIG. FIG. 11 is a diagram showing a configuration of the transmitting / receiving apparatus according to Embodiment 7 of the present invention.

In FIG. 11, 710 and 720 are antennas, 711 and 721 are RF band amplifiers, 712 and 722 are RF band band-pass filters (RFBPF), 713 and 72.
3 is a mixer, 714 and 724 are IF band amplifiers, 715,
725 is an IF band pass filter (IFBPF). Reference numeral 600 denotes a PLL synthesizer including the reference oscillator 400 having the DDS 100C.

Next, the operation of the seventh embodiment will be described. In the receiving apparatus having the configuration shown in FIG. 11, a reception wave in a high frequency band is received by antenna 710. And
The frequency of the received wave is converted to an intermediate frequency band using mixer 713.

In the transmitting device, the transmission wave in the intermediate frequency band is frequency-converted by mixer 723 into a high frequency band.
Then, the signal is transmitted by the antenna 720.

In the transmission / reception apparatus shown in FIG.
Since the PLL synthesizer 600 including the reference oscillator 400 having 0C is used, fine frequency conversion can be performed. Therefore, the frequency channel step of the transmission / reception device can be narrowed, and there is an effect that economic efficiency is improved in terms of frequency utilization efficiency.

[0105]

As described above, the direct digital frequency synthesizer according to the present invention comprises: a phase accumulator for accumulating input frequency setting data and outputting the accumulation result as phase data (θ ₁ + θ ₂ ); Based on the upper bit (θ ₁ ) of the data, the sine wave amplitude data (si
n (2πθ ₁ )), a coefficient used for approximation means for a cosine wave corresponding to the upper bit (θ ₁ ) of the phase data, the upper bit (θ ₁ ) and the lower bit (θ ₂ ) of the phase data Correction value (cos (2πθ ₁ ) based on
An amplitude correction value calculating means for calculating and outputting (2πθ ₂ ));
And the amplitude data of the sine wave (sin (2πθ ₁ ))
And the amplitude correction value (cos (2πθ ₁ ) · (2π
Since there is provided a phase / amplitude conversion means having an adder for adding and outputting θ ₂ )), the size and cost can be reduced.

Further, in the direct digital frequency synthesizer according to the present invention, as described above, the amplitude correction value calculation means uses the coefficient used for the cosine wave approximation means corresponding to the upper bit (θ ₁ ) of the phase data. A memory for outputting, a calculating means of a cosine wave for calculating and outputting an amplitude correction value (cos (2πθ ₁ )) based on the coefficient and an upper bit (θ ₁ ) of the phase data, and a lower bit (θ _{2) of the} phase data 2πθ2 calculating means for calculating and outputting the amplitude correction value (2πθ ₂ ) based on the amplitude correction value (cos
(2πθ ₁ )) and a multiplier for multiplying the amplitude correction value (2πθ ₂ ), so that it is possible to reduce the size and cost.

Further, in the direct digital frequency synthesizer according to the present invention, as described above, the amplitude correction value calculating means includes a lower bit truncating means for outputting an upper bit of the upper bit (θ ₁ ) of the phase data. a memory for outputting a coefficient used for the approximation means of the cosine wave corresponding to the upper bits of the upper bits of the phase data (theta _1), the coefficients and the upper bits of the phase data (theta ₁₎
Cosine wave calculating means for calculating and outputting an amplitude correction value (cos (2πθ ₁ )) on the basis of the above, and 2πθ2 calculating means for calculating and outputting an amplitude correction value (2πθ ₂ ) based on the lower bit (θ ₂ ) of the phase data. , The amplitude correction value (cos (2πθ)
₁ )) and a multiplier for multiplying the amplitude correction value (2πθ ₂ ), so that the size can be reduced and the frequency can be switched at high speed.

Further, as described above, the direct digital frequency synthesizer according to the present invention has the 2πθ2
A calculating means for calculating and outputting (8 · θ ₂ ) based on lower bits (θ ₂ ) of the phase data; and a plurality of lower bits for respectively outputting higher bits of the calculating output (8 · θ ₂ ) Since it includes a bit truncation unit and an adder that adds the outputs of the plurality of lower-order bit truncation units, it is possible to reduce the circuit scale, and achieve an effect of achieving high speed, downsizing, and cost reduction.

As described above, in the direct digital frequency synthesizer according to the present invention, the multiplier outputs a plurality of lower-order bits of the amplitude correction value (2πθ ₂ ); Based on the value (cos (2πθ ₁ )), the amplitude correction value (2π
θ ₂ ) includes a plurality of switches that pass or block the upper bits, and an adder that adds the upper bits of the amplitude correction value (2πθ ₂ ) that have passed through the plurality of switches, so that the circuit scale can be reduced. This has the effect of increasing speed, reducing size, and reducing cost.

Further, as described above, in the direct digital frequency synthesizer according to the present invention, the multiplier outputs a plurality of lower-order bits for outputting the upper-order bits of the amplitude correction value (cos (2πθ ₁ )); Based on the amplitude correction value (2πθ ₂ ), the amplitude correction value (cos
(2πθ ₁ )) includes a plurality of switches that pass or block the upper bits, and an adder that adds the upper bits of the amplitude correction value (cos (2πθ ₁ )) that have passed through the plurality of switches. Smaller, faster,
There is an effect that downsizing and cost reduction can be achieved.

As described above, the phase-locked frequency synthesizer according to the present invention comprises a voltage-controlled oscillator, a variable frequency divider, a phase comparator, and a loop filter. Since the direct digital frequency synthesizer described in any of the above items is provided, the resolution of the output frequency can be increased, the speed can be increased, and the phase noise can be reduced.

As described above, the transmission / reception apparatus according to the present invention receives a reception wave in a high frequency band with a reception antenna, converts the reception wave into an intermediate frequency band using a reception mixer, and converts the reception wave into an intermediate frequency band. In a transmitting / receiving apparatus for converting a transmission wave in a frequency band to a high frequency band with a transmission mixer and transmitting the transmission wave with a transmission antenna, the direct digital frequency according to any of the above as the reception mixer and the reference oscillator of the transmission mixer. Since the synthesizer is provided, there is an effect that the resolution of the output frequency can be increased.

Further, as described above, the transmission / reception apparatus according to the present invention receives a reception wave in a high frequency band with a reception antenna, converts the reception wave into an intermediate frequency band using a reception mixer, and In a transmitting / receiving apparatus that converts a transmission wave in an intermediate frequency band to a high-frequency band with a transmission mixer and transmits the converted signal with a transmission antenna, the above-described phase-locked frequency synthesizer is used as a reference oscillator of the reception mixer and the transmission mixer. With this arrangement, the resolution of the output frequency can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DDS according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing an approximation method of a cosine wave according to the first embodiment of the present invention.

FIG. 3 is a diagram showing one example of correspondence between phase data and coefficients of an approximate expression according to the second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a DDS according to Embodiment 2 of the present invention.

FIG. 5 is a diagram showing contents of a memory of a DDS amplitude correction value calculating means according to Embodiment 2 of the present invention.

FIG. 6 shows 2π of DDS according to Embodiment 3 of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a θ2 calculation unit.

FIG. 7 is a block diagram showing a configuration of a DDS multiplier according to Embodiment 4 of the present invention.

FIG. 8 is a block diagram showing a configuration of a PLL synthesizer according to Embodiment 5 of the present invention.

FIG. 9 is a block diagram showing a configuration of a PLL synthesizer according to Embodiment 5 of the present invention.

FIG. 10 is a block diagram showing a configuration of a transmitting / receiving apparatus according to Embodiment 6 of the present invention.

FIG. 11 is a block diagram showing a configuration of a transmitting / receiving apparatus according to Embodiment 7 of the present invention.

FIG. 12 is a block diagram showing a configuration of a conventional DDS.

FIG. 13 is a diagram showing errors and spurs due to truncation of phase data according to the conventional DDS.

FIG. 14 is a diagram illustrating a relationship between a spurious level and a memory capacity with respect to a word length of phase data according to a conventional DDS.

FIG. 15 is a block diagram showing a configuration of another conventional DDS.

FIG. 16 is a block diagram showing the configuration of another conventional DDS.

[Explanation of symbols]

10 phase accumulator, 20C, 20D phase / amplitude conversion means, 30 DAC, 21B memory for sine wave,
22A, 22B amplitude correction value calculating means, 23 adder, 2
4 memory, 25 cosine wave calculation means, 26, 26A
2πθ2 calculation means, 27, 27A multiplier, 28 lower-order bit truncation means, 100C, 100D DDS (direct digital frequency synthesizer), 300 frequency setting data setting means, 400 reference oscillator, 500 division number setting data setting means, 600 PLL synthesizer, 7
10, 720 antenna, 711, 721 RF band amplifier, 712, 722 RF band band-pass filter (RF
BPF), 713, 723 Mixer, 714, 724
IF band amplifier, 715, 725 IF band band pass filter (IFBPF).

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoji Isoda 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation

Claims (9)

[Claims] 1. A phase accumulator for accumulating input frequency setting data and outputting the accumulation result as phase data (θ ₁ + θ ₂ ); and a sine wave amplitude data based on upper bits (θ ₁ ) of the phase data. A memory for outputting (sin (2πθ ₁ )), a coefficient used for approximation means for a cosine wave corresponding to the upper bit (θ ₁ ) of the phase data, the upper bit (θ ₁ ) and the lower bit (θ ₂ ) of the phase data ) Based on the amplitude correction value (c
os (2πθ ₁ ) · (2πθ ₂ )) and an amplitude correction value calculating means, and amplitude data of the sine wave (sin (2πθ ₁ ))
And the amplitude correction value (cos (2πθ ₁ ) · (2π
and a phase / amplitude conversion means having an adder for adding and outputting θ ₂ )). 2. The memory according to claim 2, wherein said amplitude correction value calculating means outputs a coefficient used for a cosine wave approximation means corresponding to a high-order bit (θ ₁ ) of said phase data, and a high-order bit of said coefficient and said phase data. calculating means for calculating and outputting an amplitude correction value (cos (2πθ ₁ )) based on θ ₁ ); and calculating 2πθ2 for calculating and outputting an amplitude correction value (2πθ ₂ ) based on the lower bit (θ ₂ ) of the phase data. _2. The direct digital frequency synthesizer according to claim 1, further comprising: an arithmetic unit; and a multiplier for multiplying the amplitude correction value (cos (2πθ ₁ )) and the amplitude correction value (2πθ ₂ ). Wherein the amplitude correction value calculation means includes abort means lower bits to output the upper bits of the upper bits (theta ₁₎ of the phase data, the upper bits of the upper bits (theta ₁₎ of the phase data A memory for outputting a coefficient used for a corresponding cosine wave approximating means, and a cosine wave calculating means for calculating and outputting an amplitude correction value (cos (2πθ ₁ )) based on the coefficient and the upper bit (θ ₁ ) of the phase data A 2πθ2 calculating means for calculating and outputting an amplitude correction value (2πθ ₂ ) based on the lower bit (θ ₂ ) of the phase data; the amplitude correction value (cos (2πθ ₁ )) and the amplitude correction value (2πθ ₂ ) 2. A direct digital frequency synthesizer according to claim 1, further comprising: 4. The 2πθ2 calculating means calculates (8 · θ2) based on a lower bit (θ ₂ ) of the phase data.
8 ₂ arithmetic means for calculating and outputting θ ₂ ), a plurality of lower bit truncating means for respectively outputting upper bits of the arithmetic output (8 · θ ₂ ), and an adder for adding outputs of the plurality of lower bit truncating means 4. The direct digital frequency synthesizer according to claim 2, further comprising: 5. The amplitude correction value (cos (2πθ ₁ )) based on the amplitude correction value (cos (2πθ ₁ )) and a plurality of lower bit truncation means for outputting a higher-order bit of the amplitude correction value (2πθ ₂ ). A plurality of switches that pass or block the upper bits of 2πθ ₂ ); and the amplitude correction value (2πθ) that has passed through the plurality of switches.
Direct digital frequency synthesizer according to claim 2 or 3, wherein the including an adder for adding the high-order bit of the _2). 6. The multiplier comprises: a plurality of lower-order bit truncation means for outputting upper bits of the amplitude correction value (cos (2πθ ₁ )); and the amplitude correction value (2πθ ₂ ) based on the amplitude correction value (2πθ ₂ ). a plurality of switches that pass or block the upper bits of cos (2πθ ₁ )), and the amplitude correction value (cos
4. A direct digital frequency synthesizer according to claim 2, further comprising an adder for adding the higher-order bit of (2πθ ₁ )). 7. A phase-locked frequency synthesizer comprising a voltage-controlled oscillator, a variable frequency divider, a phase comparator, and a loop filter, wherein a direct oscillator according to any one of claims 1 to 6 is used as a reference oscillator. A phase-locked frequency synthesizer comprising a digital frequency synthesizer. 8. A reception wave in a high frequency band is received by a reception antenna, and the reception wave is frequency-converted into an intermediate frequency band using a reception mixer, and a transmission wave in the intermediate frequency band is converted into a high frequency wave by a transmission mixer. A transmission / reception device that converts a frequency into a band and transmits the frequency using a transmission antenna, comprising a direct digital frequency synthesizer according to any one of claims 1 to 6 as a reference oscillator of the reception mixer and the transmission mixer. A transmission / reception device characterized by the above-mentioned. 9. A reception wave in a high frequency band is received by a reception antenna, and the reception wave is frequency-converted into an intermediate frequency band using a reception mixer, and a transmission wave in the intermediate frequency band is converted into a high frequency wave by a transmission mixer. A transmission / reception device for converting a frequency into a band and transmitting the converted signal with a transmission antenna, comprising: the phase-locked frequency synthesizer according to claim 7 as a reference oscillator of the reception mixer and the transmission mixer.