JPH1187637A - Semiconductor device and method of its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a pattern, wherein space and line near a design rule is 1:1 at a memory cell part and to form a pattern equal to or less than the design rule at a random logic circuit part, in a semiconductor device where a memory cell and random logic circuit are placed in mixture. SOLUTION: Films 6 and 8 to be patterned are formed on a semiconductor substrate 2, and on the film a silicon nitride film is formed. The silicon nitride film is patterned to form a mask pattern 10b, further, a protective film which covers a part of the mask pattern 10b so as not to be etched is formed. Such a mask pattern 10b without protective film is etched isotropically to form a mask pattern 10c of a specified dimension. After removing the protective film, the films 6 and 8 to be patterned are etched with the mask patterns 10b and 10c as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a memory cell and a peripheral circuit or a random logic circuit on the same semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, attention has been paid to a semiconductor device in which a memory cell and a random logic circuit are mixedly mounted on the same semiconductor substrate. In this semiconductor device, large-capacity memory cells are formed in an LSI chip in an array,
A random logic circuit is formed on the SI chip.
The random logic circuit requires an isolated pattern (isolated pattern) as shown in FIG. 4A, while the memory cell requires a periodic repetitive pattern (an isolated pattern) as shown in FIG. Periodic pattern) is required.

Usually, when a pattern is formed in a semiconductor device, a photolithography method is used. In this photolithography method, a pattern is transferred to a photoresist film by a light exposure method, a resist pattern is formed by this transfer, and then etching is performed using the resist pattern as a mask.

However, under the condition that a pattern in the vicinity of the processable size is to be processed by the photolithography method, the proximity effect or the light intensity of the light is used because the size of the fine processing pattern and the wavelength of the light used in the exposure apparatus are almost the same. An interference effect occurs.

In a semiconductor device in which a memory cell and a random logic circuit are mounted on the same semiconductor substrate,
When the exposure conditions of photolithography optimized for the periodic pattern of the memory cell are used for the semiconductor substrate,
For an isolated pattern of a random logic circuit, the optimum exposure conditions are different, and the proximity effect or light interference effect deteriorates the manufacturing process margin. Therefore, in a conventional semiconductor device,
Since exposure is performed under irradiation conditions that take into account both the memory cell and the random logic circuit, the gate pattern of the memory cell is often finer than the gate pattern of the random logic circuit (peripheral circuit). .

[0006]

However, in the above-mentioned hybrid type semiconductor device, if a large-capacity memory is to be integrated and manufactured by the above-described photolithography method, a line near the minimum processable dimension is formed in the memory cell. It is necessary to form a gate pattern having a space of approximately 1: 1. On the other hand, in the peripheral circuit portion where the random logic circuit is formed, the operation speed of the semiconductor device must be improved, so that it is equivalent to that in the memory cell, or 10%.
It is desired to form a fine gate pattern as thin as about%.

FIG. 14 shows the relationship between the exposure amount and the defocus (dose focus margin) optimized for the periodic pattern and the relationship for the isolated pattern. In the drawing, a region surrounded by a solid line is a relationship between the exposure amount and the defocus when a dimensional change of ± 10% is particularly allowed. From this, it can be seen that the optimum exposure conditions are different between the periodic pattern and the isolated pattern.

As described above, since the optimum dose focus margins are different, if a fine periodic pattern and an isolated pattern satisfying the above requirements are simultaneously formed, one dose margin is lost. Therefore, it is very difficult to simultaneously form a target fine periodic pattern and an isolated pattern.

In view of the above, the present invention has been made in view of the above-mentioned problem, and in a semiconductor device having a memory cell and a random logic circuit (peripheral circuit) on the same semiconductor substrate, a portion where the memory cell is formed Then, the space part and the line part near the design rule are almost 1: 1
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a pattern having the following design rule can be formed and a pattern having a design rule or less can be formed in a portion where a random logic circuit (peripheral circuit) is formed.

In the above-described semiconductor device, a memory cell and a gate electrode of a random logic circuit (peripheral circuit) are formed, an interlayer insulating film is successively deposited on the entire surface of the semiconductor substrate, and then a memory having a fine repetitive pattern is formed. For the cell portion, a self-aligned contact process for forming an opening in the interlayer insulating film that is self-aligned with the gate electrode is generally employed. Here, when the opening is formed, it is necessary to provide an insulating film serving as an etching stopper on the gate electrode so as not to erode the conductive film forming the gate electrode. However, if such an insulating film is also formed on the gate electrode of the random logic circuit portion, the parasitic capacitance between the gate electrode and the wiring tends to increase, and the operation speed tends to be hindered.

Therefore, the present invention provides a semiconductor device having a memory cell and a random logic circuit (peripheral circuit) on the same semiconductor substrate, forming a gate electrode, forming an interlayer insulating film, and then forming an opening for a self-align contact. When forming the portion, an insulating film having a sufficient thickness as an etching stopper is formed on the gate electrode in the memory cell portion, and an increase in parasitic capacitance between the gate electrode and the wiring is suppressed in the random logic circuit portion. To provide a semiconductor device.

[0012]

According to another aspect of the present invention, there is provided a semiconductor device having a memory cell and a peripheral circuit or a random logic circuit on the same semiconductor substrate. A first silicon nitride film is stacked on the gate electrode of the MIS-FET forming the peripheral circuit or the random logic circuit, and the first silicon nitride film is formed on the gate electrode of the MIS-FET forming the memory cell. A second silicon nitride film thicker than the silicon nitride film is stacked.

Further, in the semiconductor device according to the present invention, the MIS-FE
The gate electrode of T has a stacked structure of a lower polysilicon film and an upper refractory metal silicide film or a refractory metal film.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a film to be patterned on a semiconductor substrate; forming a mask material film on the film to be patterned; Forming a first mask pattern by patterning the first mask pattern; forming a protective film covering a portion of the first mask pattern so that the first mask pattern is not etched; Forming a second mask pattern having a predetermined dimension by isotropically etching the first mask pattern, and removing the protective film, and then using the first and second mask patterns as a mask to form the film to be patterned. Etching step.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a memory cell and a peripheral circuit or a random logic circuit on the same semiconductor substrate. Forming a film to be patterned on the film to be patterned; forming a mask material film on the film to be patterned; patterning the mask material film to form a first mask pattern; A step of forming a protective film covering the first mask pattern so that the first mask pattern is not etched; and a step of isotropically etching the first mask pattern in the peripheral circuit or the random logic circuit portion to a predetermined level. Forming a second mask pattern having dimensions and removing the protective film, and then forming the first and second mask patterns. Characterized by comprising the step of etching the film to be patterned as a disk.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fourth aspect, wherein the first mask pattern forms the MIS-FE forming the memory cell.
The second mask pattern is formed with substantially the same size as the gate electrode of T, and the second mask pattern is formed with substantially the same size as the gate electrode of the MIS-FET constituting the peripheral circuit or the random logic circuit. The film to be patterned is patterned using the mask pattern as a mask to form a gate electrode of the memory cell portion and the peripheral circuit or random logic circuit portion.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the third to fifth aspects, the mask material film is a silicon nitride film, and the protective film is a silicon oxide film. It is characterized by being.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the third to fifth aspects, the mask material film is a silicon oxide film and the protective film is a silicon nitride film. It is characterized by being.

According to a eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the third to fifth aspects, the mask material film is a photoresist film and the protective film is a silicon oxide film. Alternatively, it is a silicon nitride film.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a structure of a semiconductor device according to a first embodiment of the present invention.

This semiconductor device has a silicon semiconductor substrate 2
FIG. 4 showing a gate insulating film 4 formed thereon and a random logic circuit portion formed on the silicon semiconductor substrate 2.
(A), a pattern having an isolation (isolation pattern) as shown in FIG. 1A, wherein a polysilicon film 6, a tungsten silicide (WSi) film 8, and a silicon nitride film 10b are stacked on the gate insulating film 4 in this order. 4B is a repetitive pattern (periodic pattern) having a periodicity as shown in FIG. 4B of the gate electrode and the memory cell portion formed on the silicon semiconductor substrate 2. It has a polysilicon film 6, a tungsten silicide (WSi) film 8, and a gate electrode laminated in the order of a silicon nitride film 10c thicker than the silicon nitride film 10b.

Further, the semiconductor device includes an interlayer insulating film 14 formed on the gate electrode and the gate insulating film 4 of the silicon semiconductor substrate 2 and having an opening for a self-aligned contact. Conductive film 16 which is in contact with the diffusion layer of the memory cell and is in contact with the diffusion layer of the random logic circuit portion at the other opening.
And P well regions 18 and 20 and N well region 22 formed in silicon semiconductor substrate 2 and element isolation region 24
And

In the above-described semiconductor device, the silicon nitride film 10c provided on the gate electrode of the memory cell has a thickness sufficient to function as an etching stopper when forming an opening for self-aligned contact in the interlayer insulating film 14. have. On the other hand, the silicon nitride film 10b provided on the gate electrode of the random logic circuit does not need to act as an etching stopper as described above, and reduces the parasitic capacitance between the gate electrode and the conductive film 16 to increase the operation speed. For this purpose, the thickness is smaller than that of the silicon nitride film 10c. In the semiconductor device of the present embodiment, the thickness of the silicon nitride film 10b is set to, for example, 30 to 100.
[Nm], and the thickness of the silicon nitride film 10c is, for example, 50 to 150 [nm]. Further, instead of the tungsten silicide (WSi) film 8, a high melting point metal such as a tungsten (W) film or a high melting point metal silicide such as a titanium silicide (TiSi) film may be formed.

As described above, according to the semiconductor device of the present embodiment, the thickness of the silicon nitride film on the gate electrode in the memory cell portion is larger than the thickness of the silicon nitride film on the gate electrode in the random logic circuit portion. When forming an opening for a self-aligned contact, the silicon nitride film on the gate electrode in the memory cell portion has a sufficient thickness to function as an etching stopper.

Next, a method of manufacturing the semiconductor device according to a second embodiment of the present invention will be described with reference to a method of manufacturing a CMOS circuit. 2 (a), (b) to FIG.
(A), (b) is sectional drawing of each manufacturing process which shows the manufacturing method of the said semiconductor device.

First, on a P-type silicon semiconductor substrate 2,
An element isolation region is formed. This formation method includes a selective oxidation method in which an oxide film is formed only in the element isolation region by oxidation after selection, or a method in which a silicon groove is formed by performing reactive etching only in the element isolation region, and then an insulating film is formed in the silicon groove. There is a buried element isolation method which is formed by burying.

Here, formation of an element isolation region by a buried element isolation method will be described. As shown in FIG. 2A, a P-type silicon semiconductor substrate 2 having a resistivity of 1 to 5 [Ω · cm] is thermally oxidized in a high-temperature oxidizing atmosphere of about 950 ° C. A silicon oxide film 30 having a thickness of about 20 [nm] is formed on the substrate 2. Further, a silicon nitride film 32 is formed on this silicon oxide film 30 to a thickness of about 100 nm by LPCVD. FIG. 2A shows a cross section of the silicon semiconductor substrate 2 so far.

Subsequently, a resist pattern having an element isolation region opened is formed on the silicon nitride film 32 by photolithography. Then, the silicon nitride film 32 and the silicon oxide film 30 are etched by a reactive ion etching method.

Thereafter, as shown in FIG. 2B, after the resist pattern is removed, the silicon nitride film 32 having a depth of about 100 to 300 [nm] is formed by reactive ion etching using the silicon nitride film 32 as a mask pattern. To form Further, on the silicon surface of the silicon groove 34,
Silicon oxide film 3 of about 5 to 20 [nm] by thermal oxidation
6 is formed. Further, an insulating film is deposited on the entire surface of the silicon semiconductor substrate 2 to fill the silicon groove 34.
Here, a silicon oxide film 38 such as an LPTEOS film is buried by an LPCVD method. FIG. 2B shows a cross section of the silicon semiconductor substrate 2 so far. In the following drawings, the illustration of the silicon oxide film 36 formed on the side and bottom surfaces of the silicon groove 34 is omitted.

Then, the embedded silicon oxide film 38 is planarized by a CMP method (chemical mechanical polishing). At this time, the silicon nitride film 32 functions as a stopper material at the time of polishing (at the time of CMP) by the CMP method, and the silicon oxide film 38 made of the LPTEOS film on the element formation region can be removed. Although a planarization method in which a stopper is not formed in the element isolation region is used here, if necessary, for example, a polysilicon film is formed only on a wide element isolation region and used as a stopper during CMP. You may. Thereafter, the silicon nitride film 32 protecting the element formation region is removed using hot phosphoric acid, thereby completing the formation of the element isolation region 24.

Next, as shown in FIG. 3A, the silicon oxide film 30, which is a dummy oxide film in the element formation region on the silicon semiconductor substrate 2, is peeled off with an NHF solution. Thereafter, the silicon surface on the silicon semiconductor substrate 2 is oxidized by about 20 [nm] by a thermal oxidation method to form a buffer silicon oxide film. Then, the P well regions 18 and 20 and the N well region 22 are It is formed by an injection method.
For the P-well regions 18 and 20, boron is
It is formed by ion implantation at a dose of about 2 × 10 ¹³ [cm ⁻² ] at 50 to 350 [KeV]. As for the N-well region 22, phosphorus is applied to about 2 × 1 at about 500 KeV.
It is formed by ion implantation at a dose of 0 ¹³ [cm ⁻² ].
Further, after the buffer silicon oxide film is peeled off by the NHF solution, a silicon oxide film 4 of about 5 nm is formed on the element formation region. FIG. 3A shows a cross section of the silicon semiconductor substrate 2 so far.

Subsequently, as shown in FIG. 3 (b), a thickness of about 100 to
A polysilicon film 6 of 200 [nm] is deposited. Then, the polysilicon film 6 is doped with impurities.
Thereafter, a high melting point metal silicide such as tungsten silicide (WSi) 8 is deposited on the polysilicon film 6. Further, a tungsten silicide (WSi) film 8
A silicon nitride film 10 is deposited thereon by about 50 to 150 [nm]. FIG. 3B shows a cross section of the silicon semiconductor substrate 2 so far. Instead of the tungsten silicide (WSi) film 8, a high melting point metal such as a tungsten (W) film or a high melting point metal silicide such as titanium silicide (TiSi) may be deposited.

A resist pattern is formed by photolithography on the thus formed silicon nitride film 10 having a laminated structure. As the photolithography method, a reduction exposure apparatus using an excimer laser as a light source is used. In some cases, a coating type antireflection film may be formed before forming the resist pattern.

FIG. 4A is a diagram showing a pattern layout of a gate electrode pattern in a random logic circuit portion (isolated pattern portion), and FIG. 4B is a memory cell portion (periodic pattern portion). FIG. 3 is a diagram showing a pattern layout of a gate electrode pattern of FIG. The target size of the gate electrode pattern 40 in the memory cell portion is the minimum size determined by the design rule. On the other hand, the gate electrode pattern 4 in the random logic circuit portion
The target size of No. 2 is smaller than the target size of the gate electrode pattern 40 in the memory cell portion.

With respect to the target dimensions of such a pattern layout, a mask is created by giving the same conversion difference between the memory cell part and the random logic circuit part, and the gate electrode pattern 40 of the memory cell part is formed. When trying to resolve the gate electrode pattern 42 in the random logic circuit portion under the optimal exposure conditions, the resolution cannot be adjusted to the target dimensions because the focus margin is extremely small. The conversion difference is a dimensional difference between the pattern size of the mask and the target size of the pattern layout.

Therefore, in the random logic circuit portion composed of the isolated pattern, as shown in FIG. 5A, a conversion difference is given to the target size of the gate electrode pattern 42, which is the actual gate size, and this gate electrode pattern 42
A mask pattern is created with a pattern 44 that is thicker than that. On the other hand, as shown in FIG. 5B, in the memory cell portion composed of a periodic pattern that is a regular repetitive pattern, the gate electrode pattern 4 is hardly added with little conversion difference.
A mask pattern is created with a target size of 0. As described above, by increasing the pattern size of the mask for forming the gate electrode pattern 42 in the random logic circuit portion, the exposure margin can be improved to 1.5 [μm].

As described above, photolithography is performed by giving a conversion difference to the mask pattern. As shown in FIG. 6A, in the random logic circuit portion, a resist pattern 44a thicker than the target size of the gate electrode pattern 42 is formed. Form. On the other hand, in the memory cell portion, a resist pattern 40a having substantially the same size as the target size of the gate electrode pattern 40 is formed.

Then, as shown in FIG. 6B, tungsten silicide (W
The silicon nitride film 10 on the Si) film 8 is patterned to form silicon nitride films 10a and 10b. After that, the resist patterns 40a and 44a are peeled off.

Subsequently, as shown in FIG. 7A, a new oxide film 46 is deposited on the silicon semiconductor substrate 2 by the CVD method, and the silicon oxide film 46 is formed on the silicon nitride films 10a and 10b and tungsten silicide (WSi). Oxide film 46 on film 8
To form Thereafter, as shown in FIG. 7B, the oxide film 46 is removed only in the region where the silicon nitride film 10a is formed in the random logic circuit portion by photolithography, and the silicon nitride film in the memory cell portion is removed. The oxide film 46 is left as a protective film in a region where the film 10b is formed.

Subsequently, as shown in FIG. 8A, the silicon nitride film 10a is isotropically etched using hot phosphoric acid to form a silicon nitride film 10c. At this time, the dimension of the silicon nitride film 10c is adjusted to the target dimension (desired gate length dimension) 42 by adjusting the etching time.

Next, the silicon nitride film 1 in the memory cell portion
The oxide film 46 protecting Ob is removed, and the silicon nitride film 10b and the silicon nitride film 10c are used as a mask by a RIE method using a mixed gas of HBr and oxygen or chlorine or oxygen as an etching gas. As shown in FIG. 8B, the tungsten silicide (WSi) film 8 and the polysilicon film 6 are vertically processed. Through the above steps,
The formation of the gate electrodes of the memory cell portion and the random logic circuit portion is completed.

As described above, according to the method of manufacturing a semiconductor device of the second embodiment, when forming fine gate electrode patterns of memory cells and random logic circuits on the same semiconductor substrate, It is possible to form a target gate electrode pattern without losing the focus margin which is a problem when forming a fine pattern by the method. Further, in the semiconductor device manufactured by this manufacturing method, after forming a gate electrode and forming an interlayer insulating film, when forming an opening for a self-aligned contact, an etching stopper is formed on the gate electrode in a memory cell portion. As an insulating film having a sufficient thickness.

After the gate electrode is formed by the above-described manufacturing method, the semiconductor device as shown in FIG. 1 is formed by ion implantation into the diffusion layer or by using a self-aligned contact by a well-known method. It may be formed.
Further, in the case of a stacked dynamic memory, as is well known, a capacitor electrode having a storage node is thereafter formed. In the case of a memory cell using a trench cell, a gate electrode may be formed by the above-described steps after forming a trench capacitor portion. In the second embodiment, a silicon semiconductor substrate has been described as an example, but the present embodiment is applicable to a semiconductor substrate other than silicon such as gallium arsenide.

Next, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to a method of manufacturing a CMOS circuit. 9 (a), 9 (b) to 11
(A), (b) is sectional drawing of each manufacturing process which shows the manufacturing method of this semiconductor device.

First, an element isolation region is formed on a P-type silicon semiconductor substrate 52. The method of forming the element isolation region is the same as that of the second embodiment. further,
Since the steps from the formation of the element isolation region to the formation of the well region are the same as those in the second embodiment, the description is omitted here.

Next, as shown in FIG. 9A, after a silicon oxide film 54 of about 5 [nm] is formed on the element forming region, a thickness of about 100 to 200 [nm] is formed by LPCVD.
Of polysilicon film 56 is deposited. Then, the polysilicon film 56 is doped with impurities. After that, a tungsten silicide (W
Si) Refractory metal silicide such as 58 is deposited. Further, on the tungsten silicide (WSi) film 58,
A silicon oxide film 60 is deposited in a thickness of about 50 to 150 [nm]. As in the second embodiment, a high melting point metal such as a tungsten (W) film or a high melting point metal silicide such as titanium silicide (TiSi) is deposited instead of the tungsten silicide (WSi) film 58. May be.

A resist pattern is formed by photolithography on the silicon oxide film 60 having the laminated structure thus formed. The method of forming the resist pattern is the same as in the second embodiment,
For the same reason, in the random logic circuit portion composed of the isolated pattern, as shown in FIG. 5A, a conversion difference is given to the target size of the gate electrode pattern 42 which is the actual gate size, and this gate electrode pattern A mask pattern is created using a pattern 44 thicker than 42.
On the other hand, as shown in FIG. 5B, in the memory cell portion composed of a periodic pattern that is a regular repetitive pattern, as shown in FIG.
Create a mask pattern with target dimensions of As described above, by increasing the pattern size of the mask for forming the gate electrode pattern 42 in the random logic circuit portion, the exposure margin can be improved to 1.5 [μm].

As described above, photolithography is performed by giving a conversion difference to the mask pattern. As shown in FIG. 9A, in the random logic circuit portion, a resist pattern having a size larger than the target size of the gate electrode pattern 42 is used. 44a is formed. On the other hand, in the memory cell portion, a resist pattern 40a having substantially the same size as the target size of the gate electrode pattern 40 is formed.

Then, as shown in FIG. 9B, tungsten silicide (W
The silicon oxide film 60 on the Si) film 58 is patterned to form silicon oxide films 60a and 60b. After that, the resist patterns 40a and 44a are peeled off.

Subsequently, as shown in FIG. 10A, a new silicon nitride film 62 is deposited on the silicon semiconductor substrate 52 by the plasma CVD method, and the silicon oxide film 6 is formed.
0a, 60b, and tungsten silicide (WS
i) A silicon nitride film 62 is formed on the film 58. Thereafter, as shown in FIG. 10B, the silicon nitride film 62 is removed using hot phosphoric acid only in the region where the silicon oxide film 60a of the random logic circuit portion is formed by the photolithography method. The silicon nitride film 62 is left as a protective film in a part of the region where the silicon oxide film 60b is formed.

Subsequently, as shown in FIG. 11A, the silicon oxide film 60a is isotropically etched using a dilute hydrofluoric acid treatment method to form a silicon oxide film 60c.
At this time, by adjusting this etching time,
The size of the silicon oxide film 60c is adjusted to the target size (desired gate length size) 42.

Next, the silicon oxide film 6 in the memory cell portion
The silicon nitride film 62 protecting Ob is removed using hot phosphoric acid, and a mixed gas of HBr and oxygen, or chlorine or oxygen is used as an etching gas using the silicon oxide film 60b and the silicon oxide film 60c as a mask. R
As shown in FIG. 11B, the tungsten silicide (WSi) film 58 and the polysilicon film 56 are vertically processed by the IE method. Through the above steps, the formation of the gate electrodes in the memory cell portion and the random logic circuit portion is completed.

As described above, according to the method of manufacturing a semiconductor device of the third embodiment, when forming fine gate electrode patterns of memory cells and random logic circuits on the same semiconductor substrate, It is possible to form a target gate electrode pattern without losing the focus margin which is a problem when forming a fine pattern by the method.

After the gate electrode is formed by the above-described manufacturing method, a semiconductor device equivalent to that shown in FIG. 1 is formed by ion implantation or the like into a diffusion layer by a generally well-known method. I just need. Further, in the case of a stacked dynamic memory, as is well known, a capacitor electrode having a storage node is thereafter formed.
In the case of a memory cell using a trench cell, a gate electrode may be formed by the above-described steps after forming a trench capacitor portion. Note that this third
In the above embodiments, a silicon semiconductor substrate has been described as an example, but the present embodiment is also applicable to semiconductor substrates other than silicon such as gallium arsenide.

Next, a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to a method of manufacturing a CMOS circuit. 12 (a), (b), FIG.
(A), (b) is sectional drawing of each manufacturing process which shows the manufacturing method of this semiconductor device.

First, an element isolation region is formed on a P-type silicon semiconductor substrate 72. The method of forming the element isolation region is the same as in the second and third embodiments. Further, the steps from the formation of the element isolation region to the formation of the well region are the same as those of the second and third embodiments, and thus the description thereof is omitted.

Next, as shown in FIG. 12A, a silicon oxide film 74 having a thickness of about 5 [nm] is formed on the element formation region, and then a thickness of about 100 to 200 [n] is formed by LPCVD.
m] of the polysilicon film 76 is deposited. Then, the polysilicon film 76 is doped with an impurity. afterwards,
On this polysilicon film 76, a high melting point metal silicide such as tungsten silicide (WSi) 78 is deposited. Furthermore, a tungsten silicide (WSi) film 78
A silicon nitride film 80 is deposited thereon to about 100 [nm]. As in the second and third embodiments, instead of the tungsten silicide (WSi) film 78, a high melting point metal such as a tungsten (W) film or a high melting point metal such as titanium silicide (TiSi) is used. Silicide may be deposited.

A resist pattern is formed by photolithography on the silicon nitride film 80 having the laminated structure thus formed. The method of forming the resist pattern is the same as in the second and third embodiments. For the same reason, in the random logic circuit portion made of an isolated pattern, as shown in FIG.
A conversion difference is given to the target size of the gate electrode pattern 42, which is the actual gate size, and a mask pattern is created with a pattern 44 thicker than the gate electrode pattern 42. On the other hand, in a memory cell portion composed of a periodic pattern which is a regular repetitive pattern, as shown in FIG. .
As described above, by increasing the pattern size of the mask for forming the gate electrode pattern 42 in the random logic circuit portion, the exposure margin can be improved to 1.5 [μm].

As described above, photolithography is performed by giving a conversion difference to the mask pattern. As shown in FIG. 12A, in the random logic circuit portion, a resist pattern having a size larger than the target size of the gate electrode pattern 42 is used. 44a is formed. On the other hand, in the memory cell portion, a resist pattern 40a having substantially the same size as the target size of the gate electrode pattern 40 is formed.

Subsequently, the CV is placed on the silicon semiconductor substrate 72.
A new silicon oxide film 82 is deposited by the D method or the SORD method or the like, and the resist patterns 40a and 44a
A silicon oxide film 82 is formed on the silicon nitride film 80. Thereafter, as shown in FIG. 12B, the silicon oxide film 82 is removed by a dilute hydrofluoric acid treatment method only in a region of the random logic circuit portion where the resist pattern 44a is formed by a photolithography method. The silicon oxide film 82 is left as a protective film in the memory cell portion where the resist pattern 40a is formed.

Further, as shown in FIG. 13A, the resist pattern 44a is isotropically etched by RIE using oxygen gas or CDE (chemical dry etching) to form a resist pattern 44c. . At this time, the dimension of the resist pattern 44c is adjusted to the target dimension (desired gate length dimension) 42 by adjusting the etching time.

Next, the silicon oxide film 82 protecting the resist pattern 40a in the memory cell portion is removed by a dilute hydrofluoric acid treatment method, and the resist pattern 40a is removed.
Using the resist pattern 44c as a mask, the silicon nitride film 80, the tungsten silicide (WSi) film 78, and the polysilicon film 76 are vertically processed by reactive ion etching as shown in FIG. afterwards,
The resist patterns 40a and 44a are peeled off. Through the steps described above, the formation of the gate electrodes in the memory cell portion and the random logic circuit portion is completed.

As described above, according to the method of manufacturing a semiconductor device of the fourth embodiment, when forming fine gate electrode patterns of a memory cell and a random logic circuit on the same semiconductor substrate, It is possible to form a target gate electrode pattern without losing the focus margin which is a problem when forming a fine pattern by the method.

After the gate electrode is formed in this manner, a semiconductor device may be formed by ion implantation into a diffusion layer, a self-aligned contact, or the like by a generally well-known method. Further, in the case of a stacked dynamic memory, as is well known, a capacitor electrode having a storage node is thereafter formed. In the case of a memory cell using a trench cell, a gate electrode may be formed by the above-described steps after forming a trench capacitor portion.

In the fourth embodiment, the silicon nitride film 80 is formed on the gate electrode, and the silicon oxide film 8 is formed on the protection film.
2, the silicon nitride film may be replaced with a silicon oxide film, and the silicon oxide film 82 may be replaced with a silicon nitride film. In this case, the removal of the silicon nitride film may be performed using hot phosphoric acid. In the fourth embodiment, a silicon semiconductor substrate has been described as an example, but the present embodiment is also applicable to semiconductor substrates other than silicon such as gallium arsenide.

Further, the first to fourth embodiments have the following features.
Although all the description has been given of the case of a semiconductor device in which a memory cell and a random logic circuit are mixed, particularly for a memory in which a random logic is not mixed, a peripheral circuit portion and a memory cell portion of a memory cell requiring high-speed operation as in the case of the random logic circuit The present invention is also very effective when forming the gate electrodes simultaneously. Further, the present invention is applicable not only to the formation of the gate electrode but also to the formation of other wiring layers, and can be carried out in various modifications without departing from the scope of the present invention.

[0067]

As described above, according to the present invention, in a semiconductor device having a memory cell and its peripheral circuit or a random logic circuit on the same semiconductor substrate, the design rule is applied to the portion where the memory cell is formed. A method of manufacturing a semiconductor device, in which a pattern in which a space portion and a line portion in the vicinity are approximately 1: 1 can be formed, and a pattern below a design rule can be formed in a portion where a peripheral circuit or a random logic circuit is formed. Can be provided. Further, according to the present invention, in a semiconductor device having a memory cell and its peripheral circuit or random logic circuit on the same semiconductor substrate, after forming a gate electrode and forming an interlayer insulating film, an opening for a self-align contact is formed. When forming, an insulating film having a sufficient thickness as an etching stopper is formed on the gate electrode in the memory cell portion, and an increase in parasitic capacitance between the gate electrode and the wiring is suppressed in the peripheral circuit or the random logic circuit portion. Semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a structure of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view of each manufacturing process showing a method for manufacturing a semiconductor device as a second embodiment.

FIG. 3 is a cross-sectional view of each manufacturing step showing a method of manufacturing a semiconductor device as a second embodiment.

FIG. 4 is a plan view showing a pattern layout of a gate electrode pattern.

FIG. 5 is a plan view showing a pattern layout of a gate electrode pattern.

FIG. 6 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device as a second embodiment.

FIG. 7 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device as a second embodiment.

FIG. 8 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device as the second embodiment.

FIG. 9 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device as a third embodiment.

FIG. 10 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device as a third embodiment.

FIG. 11 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device as a third embodiment.

FIG. 12 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device as a fourth embodiment.

FIG. 13 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device as a fourth embodiment.

FIG. 14 is a diagram showing the relationship between exposure dose and defocus (dose focus margin) optimized for a conventional periodic pattern and an isolated pattern.

[Explanation of symbols]

2, 52, 72 ... silicon semiconductor substrate 4, 54, 74 ... gate insulating film 6, 56, 76 ... polysilicon film 8, 58, 78 ... tungsten silicide (WSi) film 10, 10a, 10b, 10c, 32, 62 , 80: Silicon nitride film 14: Interlayer insulating film 16: Conductive film 18, 20: P well region 22: N well region 24: Element isolation region 30, 36, 38, 60, 60a, 60b, 82: Silicon oxide film 34 ... silicon grooves 40, 42 ... gate electrode patterns 40a, 44a, 44c ... resist patterns 44 ... patterns 46 ... oxide films

Claims (8)

[Claims] 1. A semiconductor device having a memory cell and a peripheral circuit or a random logic circuit on the same semiconductor substrate, wherein M is a component of the peripheral circuit or the random logic circuit.
A first silicon nitride film is stacked on the gate electrode of the IS-FET, and a second silicon film having a thickness greater than that of the first silicon nitride film is formed on the gate electrode of the MIS-FET constituting the memory cell. A semiconductor device having a nitride film laminated thereon. 2. The device according to claim 1, wherein the gate electrode of the MIS-FET has a laminated structure of a lower polysilicon film and an upper refractory metal silicide film or a refractory metal film. Semiconductor device. 3. A step of forming a film to be patterned on a semiconductor substrate; a step of forming a mask material film on the film to be patterned; and a step of patterning the mask material film to form a first mask pattern. Forming a protective film covering a portion of the first mask pattern so that the first mask pattern is not etched; and isotropically etching the first mask pattern on which the protective film is not formed to a predetermined value. Forming a second mask pattern having dimensions; and, after removing the protective film, etching the film to be patterned using the first and second mask patterns as masks. Semiconductor device manufacturing method. 4. A method for manufacturing a semiconductor device having a memory cell and a peripheral circuit or a random logic circuit on the same semiconductor substrate, comprising: forming a film to be patterned on the semiconductor substrate; Forming a first mask pattern by patterning the mask material film, and forming the first mask pattern so that the first mask pattern in the memory cell portion is not etched. Forming a protective film covering the pattern; forming the second mask pattern of a predetermined size by isotropically etching the first mask pattern in the peripheral circuit or the random logic circuit portion; After removing the film, the film to be patterned is etched using the first and second mask patterns as a mask. A method of manufacturing a semiconductor device, comprising: 5. The first mask pattern has substantially the same size as a gate electrode of a MIS-FET constituting the memory cell, and the second mask pattern constitutes the peripheral circuit or the random logic circuit. Formed in substantially the same size as the gate electrode of the MIS-FET to be patterned, patterning the film to be patterned using the first and second mask patterns as masks, and forming a gate of the memory cell portion and the peripheral circuit or random logic circuit portion. The method for manufacturing a semiconductor device according to claim 4, wherein an electrode is formed. 6. The method according to claim 3, wherein the mask material film is a silicon nitride film, and the protective film is a silicon oxide film. 7. The method of manufacturing a semiconductor device according to claim 3, wherein said mask material film is a silicon oxide film, and said protective film is a silicon nitride film. 8. The method according to claim 3, wherein the mask material film is a photoresist film, and the protective film is a silicon oxide film or a silicon nitride film. .