JPH1187612A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same which is capable of mounting and highly integrating a load element having a highly precise resistance along with a transistor on itself. SOLUTION: By selectively removing a polycrystalline silicon film, a silicon oxide film 101, and a semiconductor substrate deposited on the semiconductor substrate by etching, a groove having a predetermined surface depth is formed on the substrate. The silicon oxide film is deposited on the substrate having the groove and is then planarized. A resistor 102a with its circumference filled in by an separating insulation film 104a and patterned linearly is formed in a region Rre to be formed by the load element, and an separating insulation film 104b surrounding an active region is formed in a region Rtr to be formed. After partially covering the top of the resistor by an etching stopper film 105, a metallic film 106 is deposited, and a terminal electrode of the load element and an upper and lower electrode of the gate electrode of the transistor are formed by patterning the metal film and the polycrystalline silicon film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a load element disposed on a semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, active elements such as transistors arranged in an LSI and load elements such as resistors are formed on a common semiconductor substrate, thereby consolidating the entire semiconductor device constituting the LSI. What is to be attempted is well known in the art.

FIGS. 11A to 11D are cross-sectional views showing a general manufacturing process of a semiconductor device in which a transistor and a load element are formed on a semiconductor substrate.

First, in a step shown in FIG. 11A, an element isolation 504 surrounding an active region is formed on a semiconductor substrate 500 by a LOCOS method. In FIG. 11, the active region is a transistor formation region Rtr, and the region above the element isolation 504 is a load device formation region Rre. Thereafter, the surface of the semiconductor substrate is oxidized to form a gate insulating film 501 of the MOS transistor.
Is formed, and a polycrystalline silicon film 502 serving as a gate electrode is formed over the entire surface of the substrate.

Next, in a step shown in FIG. 11B, a photoresist film 508 covering a region where a gate electrode is to be formed and a region where a resistor is to be formed is formed. By etching the polycrystalline silicon film as a mask, a gate electrode 509 is formed.
And the resistor 510 of the load element.

Next, in a step shown in FIG. 11C, after removing the photoresist film 508, an interlayer insulating film 513 is formed on the entire surface of the substrate. At this time, the periphery of the gate electrode 509 and the resistor 510 is filled with an insulating film.

Next, in the step shown in FIG. 11D, after forming a contact hole reaching the resistor 510 and the gate electrode 509 in the interlayer insulating film 513, a contact 511 for filling the contact hole is formed. A metal wiring 512 extending over 513 is formed.

Through the above steps, a semiconductor device in which a MOS transistor having a gate electrode 513 and a load element having a resistor 510 are provided on a common semiconductor substrate 500 is formed.

[0009]

However, the structure of a load element having a resistor on the LOCOS isolation as described above has the following problems.

[0010] With the recent miniaturization of semiconductor devices, element isolation has become difficult due to bird's beaks.
The transition from the S-type isolation structure to the trench isolation structure is in progress. In this case, a wide trench isolation region is required to form a resistor on the trench isolation as in the above-described conventional semiconductor device. However, when forming the trench isolation region, a planarization process such as CMP (chemical mechanical polishing) or dry etching is performed after depositing an insulating film on the substrate in which the trench is formed. It is difficult to flatten the film with high precision by CMP or the like.
In other words, the central portion of the trench isolation region is often dented or uneven on the entire surface in many cases, and it is difficult to form a resistor with high accuracy on such a trench isolation having poor flatness.

Further, the conventional structure in which the resistor of the load element and the gate electrode of the transistor are formed of a common conductive film has the following problems.

With the recent miniaturization of semiconductor devices, MO
Signal delay due to an increase in wiring resistance of the gate electrode of the S transistor has become a problem. Therefore, in order to reduce the resistance value of the gate electrode, instead of a conventional polycrystalline silicon single-layer film or a laminated film of a metal silicide layer and a polycrystalline silicon layer, as a material constituting the gate electrode,
For example, a laminated film of a polycrystalline silicon film and a refractory metal film is used. Therefore, when a load element is formed by a conventional process of patterning this conductor film after depositing a stacked film to be a gate electrode and a resistor,
In order to obtain a high-resistance load element required for low power consumption in circuit operation, it is necessary to extremely increase the wiring length of the laminated film serving as a resistor, and as a result, the occupied area of the load element area increases. However, high integration of the semiconductor device is hindered.

A first object of the present invention is to provide a semiconductor device having a load element with a high accuracy and a small occupation area while employing a trench isolation structure.

A second object of the present invention is to provide a semiconductor device in which a load element and a transistor are mounted on a common semiconductor substrate while occupying a small area of the load element, and a method of manufacturing the same.

[0015]

In order to achieve the first object, the present invention provides means relating to the first semiconductor device according to the first to third aspects of the present invention.

In order to achieve the second object,
According to the present invention, means relating to the second semiconductor device according to claims 4 to 10 and means relating to the method of manufacturing a semiconductor device according to claims 11 to 18 are provided.

According to a first aspect of the present invention, there is provided a semiconductor device having at least one load element formed on a semiconductor substrate. A groove formed so as to project a linear substrate region on the surface side, and a first conductive film formed on the linear substrate region so as to have the same planar shape as the substrate region. The semiconductor device includes a resistor of the load element, and a separating insulating film that fills the groove and the side of the resistor.

Thus, the linear first member constituting the resistor is formed.
Is in an isolated state on the convex substrate region surrounded by the groove. Therefore, the semiconductor substrate surface between the adjacent resistors is far away from the resistors, and the generation of a leak current between the resistors via the semiconductor substrate is suppressed. In addition, since the parasitic capacitance of the resistors is mostly composed of components generated between the resistors, the parasitic capacitance is reduced as compared with the case where the impurity diffusion region exists in the semiconductor substrate region between the resistors. Therefore, a load element that can be integrated and has a high performance can be obtained.

According to a second aspect of the present invention, in the first aspect, the resistor of the load element is formed in a zigzag shape including a plurality of straight portions and a corner portion connecting the straight portions on a plane. In addition, a terminal electrode made of a second conductor film having a specific resistance smaller than that of the first conductor film and covering a portion of the straight portion of the resistor other than a substantially uniform length and the corner portion is formed. Further provisions may be made.

With this structure, the resistance value at the corner of the first conductor film where the shape easily collapses can be neglected while forming the zigzag-shaped resistor at a high density in a small area, thereby providing a stable resistance. This results in a load element having a value.

According to a third aspect of the present invention, in the second aspect, a plurality of load elements having the linear portions having the same length are arranged in parallel to one input terminal, and Can be configured to be output through each of the load elements.

Thus, even if the length of the first conductive film is shifted with a certain tendency due to the characteristics in the process, the ratio of the resistance values of the load elements does not change. A semiconductor device capable of supplying a voltage with small variations can be obtained.

According to a second aspect of the present invention, as set forth in the fourth aspect, in the first aspect, the first semiconductor film is formed on a part of the resistor of the load element more than the first conductor film. A terminal electrode made of a second conductor film having a small specific resistance is provided, and a separation groove formed on the main surface side of the semiconductor substrate so as to protrude a substrate region serving as an active region; And a gate electrode formed in the active region and formed of a lower electrode made of the first conductive film and an upper electrode made of the second conductive film. And a transistor.

Thus, a load element having a small occupied area can be obtained by forming the first conductor film from a material having a large specific resistance. On the other hand, the lower electrode of the gate electrode is also composed of the first conductor film, but the upper electrode of the gate electrode is composed of the second conductor film having a low resistance. The operation of the transistor is favorably maintained even if the transistor is formed of a material having a large value.

According to a fifth aspect, in the fourth aspect, the resistor is formed continuously with the lower electrode of the gate electrode, and the terminal electrode is connected to the upper electrode of the gate electrode. Can be formed in advance.

As a result, the area occupied by the entire semiconductor device is further reduced.

According to a sixth aspect of the present invention, in the fifth aspect, the gate electrode of the transistor is formed on the active region at a narrow portion functioning as a gate and at both ends of the narrow portion. It can be configured to have a wide portion that does not function as a gate.

Thus, even if the position of the gate electrode of the transistor is shifted, the gate width defined by the length of the narrow portion is constant, so that the characteristics of the transistor are kept constant.

According to a seventh aspect, in the fourth aspect, a source / drain region is formed on both sides of the gate electrode in the active region, and an interlayer insulating layer is provided above the resistor and the transistor. A film is formed, and a contact hole penetrating through the interlayer insulating film and reaching one of the source / drain regions and the terminal electrode of the resistor is buried in the contact hole. And a conductor film for connection.

Thus, the area occupied by the entire semiconductor device is further reduced.

According to an eighth aspect of the present invention, in any one of the fourth to seventh aspects, the first conductor film is made of polysilicon, and the second conductor film is made of refractory metal. Can be configured.

Thus, a semiconductor device having a transistor having a low-resistance gate electrode and a load element having a high resistance and a small occupying area can be obtained.

According to a ninth aspect of the present invention, in the eighth aspect, a portion of the first conductive film to be a lower electrode of the gate electrode is doped with a high-concentration impurity so that the load element of the load element is removed. It is possible to have a specific resistance smaller than that of the portion serving as the resistor.

Thus, the depletion of the lower electrode of the gate electrode is suppressed, so that the driving force of the transistor is increased. In one of the above, the second conductor film can be constituted by a laminated film of a refractory metal film and a barrier conductor film thereunder.

Thus, the reaction between the refractory metal atoms and the semiconductor atoms in the semiconductor substrate can be suppressed.

According to a method of manufacturing a semiconductor device of the present invention, a first conductive film is formed on a semiconductor substrate having a load element forming region and a transistor forming region. And selectively removing the first conductor film and a region from the surface of the semiconductor substrate to a predetermined depth from the first conductor film in the load element formation region. A second step of forming a substrate region serving as an active region in the transistor formation region and a groove for leaving the first conductive film thereon, and a third step of filling the groove with an isolation insulating film. Process and
A fourth step of depositing a second conductor film on the substrate, and a fifth step of patterning the second conductor film in the load element formation region to form a terminal electrode connected to the resistor Patterning the first and second conductor films in the transistor formation region to form a gate electrode using the first conductor film as a lower electrode and the second conductor film as an upper electrode. And a process.

According to this method, in the load element forming region, a linear resistor made of the first conductor film surrounded by the isolation insulating film buried in the trench and the low-resistance second resistor in contact with the resistor. Is formed, and a gate electrode having a lower electrode made of a first conductive film and an upper electrode made of a low-resistance second conductive film is formed in a transistor formation region. Therefore, the load element and the transistor occupying a small area are formed on a common semiconductor substrate.

According to a twelfth aspect of the present invention, in the semiconductor device according to the eleventh aspect, prior to the fourth step, an insulating film for an etching stopper covering a region of the resistor other than a region in contact with the terminal electrode. And the fifth and sixth steps can be performed continuously using a common etching mask.

According to this method, when patterning the first and second conductor films, the etching stopper insulating film must be formed on the first conductor film serving as a resistor in the load element formation region. Thus, the gate electrode can be formed without adversely affecting the resistor.

According to a thirteenth aspect, in the twelfth aspect, the step of forming the etching stopper insulating film can be performed after the first step and before the second step. .

According to this method, the number of steps can be further reduced.

According to a twelfth aspect, in the twelfth aspect, the step of forming the etching stopper insulating film is performed after the third step and before the fourth step. Is also good.

According to a fifteenth aspect, in the twelfth aspect, in the first step, a polycrystalline silicon film is deposited as the first conductor film, and before the fourth step, The method may further include a step of introducing an impurity into the first conductor film using the etching stopper film as a mask.

According to this method, a transistor having a high driving force is formed.

According to a sixteenth aspect, in any one of the eleventh to fifteenth aspects, the load element formation region and the transistor formation region are adjacent to each other, and in the second step, The first conductor film is integrally left over the load element formation region and the transistor formation region, and the fifth and sixth steps are performed by integrating the terminal electrode of the load element and the upper electrode of the gate electrode. Can be performed as

According to this method, a semiconductor device occupying an extremely small area while mounting the load element and the transistor is formed.

According to a seventeenth aspect, in the fifteenth and fifteenth steps, in the fifth and sixth steps, the gate electrode in the transistor formation region has a narrow portion functioning as a gate of the transistor and both ends thereof. The first and second conductor films can be patterned so as to have a wide portion that does not function as a gate.

According to this method, even if the position of the gate electrode varies due to misalignment in the photolithography process, the gate width is kept constant, so that a transistor having stable characteristics is formed.

As set forth in claim 18, in any one of claims 11 to 15, the load element formation region and the transistor formation region are adjacent to each other, and after the sixth step, Forming an impurity diffusion region on both sides of the gate electrode in the transistor formation region, depositing an interlayer insulation film on a substrate, and forming the impurity diffusion region of the terminal electrode and the transistor formation region in the interlayer insulation film. The method may further include a step of forming a common contact hole reaching the region, and a step of depositing a conductive material in the contact hole.

According to this method, a semiconductor device having an extremely small occupation area while mounting a load element and a transistor is formed.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, in order to explain the structure of a semiconductor device according to the first embodiment, a manufacturing process of the semiconductor device will be described with reference to FIGS. However,
1 (a) to 1 (c), 2 (a) to 2 (c) and 3
In (a) and (b), the left figure shows the load element formation region Rre.
The right view is a cross-sectional view of the load element formation area Rre and the transistor formation area Rtr at the center of the left figure.

First, in a step shown in FIG. 1A, a silicon oxide film 10 serving as a gate insulating film is formed on a semiconductor substrate 100.
1 and a portion of the gate electrode and a resistor, for example, 100
A polycrystalline silicon film 102 having a thickness of about nm is deposited.

Next, in the step shown in FIG. 1B, the polycrystalline silicon film 102, the silicon oxide film 101 and the semiconductor substrate 100 are removed while leaving a region where a resistor is to be formed and a region to be an active region. The groove 103 is formed by removing the substrate surface from the substrate surface to a predetermined depth (for example, a depth of about 300 nm) by dry etching. At this time, in the load element formation region Rre, a linear substrate region having a predetermined width surrounded by the groove 103 protrudes and remains, and a resistor 102a made of a linear polycrystalline silicon film is formed thereon. On the other hand, in the transistor formation region Rtr, a substrate region to be a rectangular active region protrudes and remains, and a rectangular polycrystalline silicon film 102b is formed thereon.

Next, in the step shown in FIG.
A silicon oxide film 104 having a thickness of about 500 nm is deposited on the entire surface of the substrate including

Next, in the step shown in FIG. 2A, the silicon oxide film 104 is removed by, for example, dry etching until the resistor 102a and the polycrystalline silicon film 102b are exposed on the surface. By this step, in the load element formation region Rre, the periphery of the resistor 102a is surrounded by the isolation insulating film 104a, and in the transistor formation region Rtr, the isolation insulating film 104b surrounding the active region is formed.

Next, in a step shown in FIG. 2B, an insulating film for an etching stopper such as a silicon nitride film is deposited on the entire surface of the substrate to a thickness of about 100 to 150 nm.
Dry etching is performed using the photoresist film 108a formed on the insulating film as a mask, and the etching stopper film 105 is removed leaving a portion on the resistor 102a of the load element. In this step, the etching stopper insulating film on both ends of the resistor in the load element formation region Rre and the transistor formation region Rtr has been removed. Using the etching stopper film 105 as a mask, 1 ×
By implanting at a dose of about 10 ¹⁵ cm ² ,
Both ends of the resistor 102a serving as a contact region of the load element and the polycrystalline silicon film 1 in the transistor formation region Rtr
02b.

Next, in a step shown in FIG. 2C, a low-resistance metal material having a thickness of about 100 nm made of, for example, tungsten is formed on the entire surface of the substrate including the load element formation region Rre and the transistor formation region Rtr. A metal film 106 is formed.

Next, in the step shown in FIG.
Dry etching is performed using the photoresist film 108b formed on the mask 06 as a mask, and a region including both ends of the resistor 102a to be a contact region of the load element and its periphery in the metal film 106 and a gate electrode of the MOS transistor are formed. The area is removed leaving behind. At the same time, in the transistor formation region Rtr, the polysilicon film 102
b is patterned into the same shape as the metal film. By this step, the resistor 102 is formed in the load element formation region Rre.
A terminal electrode 106a is formed over both sides of the insulating insulating film 104a and the etching stopper film 105. The lower electrode 102c made of a polycrystalline silicon film and the upper electrode 1 made of a metal film are formed in the transistor formation region Rtr.
06b is formed.

Thereafter, in the step shown in FIG. 3B, source / drain regions are formed on both sides of the gate electrode 120 by implanting high-concentration impurity ions by a general well-known process, and an interlayer is formed on the entire surface of the substrate. After the formation of the insulating film 110, a contact 111 that penetrates through the interlayer insulating film 110 and reaches the terminal electrode or the gate electrode 120 of the load element is formed. By forming a metal wiring 112 for connecting a gate electrode of a MOS transistor or a source / drain terminal as necessary for a circuit operation, a semiconductor device having a load element and a MOS transistor can be provided. Can be formed.

According to the manufacturing method of this embodiment, the resistor 102 a of the load element and the lower electrode 102 of the gate electrode 120 are used.
Since c and c can be formed from the common polycrystalline silicon film 102, there is no need to separately form a polycrystalline silicon film for the resistor of the load element, and the number of steps can be reduced.

In order to reduce the area occupied by the load element, it is preferable to use a high-resistance polycrystalline silicon film. However, the polycrystalline silicon film 102 is patterned by forming an isolation insulating film 104b in the transistor formation region Rre. Can be performed at the same time as patterning. Therefore, a new fine patterning process is not required, and only the patterning of the etching stopper film 105, which does not require much fineness, needs to be newly added. Therefore, it is possible to suppress an increase in the process cost for forming the load element.

The load element of this embodiment has the following advantages over the structure of the conventional load element.

First, in the load element of the present embodiment, the high-concentration impurities for forming the source / drain regions are not directly implanted into the semiconductor substrate in the load element formation region Rre. The entire Rre also functions as an element isolation region. Therefore, similarly to the conventional load element shown in FIG. 11, the element isolation region can be effectively used. In this case, instead of the LOCOS isolation in the conventional semiconductor device, it is possible to form a resistor on a wide oxide film constituting the element isolation. Since the flatness of the film surface deteriorates, it is difficult to accurately adjust the resistance value of the load element. On the other hand, in the present embodiment, since the resistor in the load element formation region Rre and the oxide film around the resistor are mixed in a fine pattern, it is easy to maintain good flattening accuracy.

Second, there are the following advantages as compared with the conventional load element formed on a semiconductor substrate.
4A and 4B are cross-sectional views showing the structures of a load element formed on a conventional semiconductor substrate and a load element of the present embodiment, respectively.

In the case of the conventional load element shown in FIG.
Semiconductor substrate 6 on which high-concentration impurity diffusion region 602 is formed
01, a resistor 604 made of a polycrystalline silicon film is formed via an oxide film 603, and the periphery thereof is
05 is satisfied. Therefore, between the resistor 604 and the high-concentration impurity diffusion region 602, parasitic capacitances C1 and C2 and a leak path shown in FIG. On the other hand, in the load element of the present embodiment, high-concentration impurities for forming the source / drain regions are not injected into the semiconductor substrate 100, and as shown in FIG. Since an oxide film constituting the isolation insulating film exists between the semiconductor substrate regions immediately below, no leak path occurs between the two, and the parasitic capacitance C0 is small.

In this embodiment, the doping of impurities into the polycrystalline silicon film 102b is performed by arsenic ion implantation, but phosphorus or boron may be similarly doped by ion implantation.

In the present embodiment, the connection between the contact region of the load element and the MOS transistor is performed through the contact hole and the metal wiring.
Depending on the layout, the terminal electrode 106a on the contact region of the load element can be directly connected to the gate electrode 120 of the MOS transistor via a common contact.

(Second Embodiment) FIGS. 5A to 5C and 6A to 6C are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment. is there. In the present embodiment, the load element formation region Rre and the transistor formation region Rtr are adjacent to each other.

First, in a step shown in FIG. 5A, a silicon oxide film 10 serving as a gate insulating film is formed on a semiconductor substrate 100.
1 and the thickness of a part of the gate electrode and the resistor is 100
a polycrystalline silicon film 102 having a thickness of about 100 nm
An etching stopper insulating film 107 made of a silicon nitride film having a thickness of about 150 nm is sequentially formed.

Next, in a step shown in FIG. 5B, an insulating film 107 for an etching stopper, a polycrystalline silicon film 102, a silicon oxide film are left except for a region where a resistor is to be formed and a region to be an active region. 101 and semiconductor substrate 10
A groove is formed by removing 0 from the substrate surface to a predetermined depth (for example, a depth of about 300 nm) by dry etching. At this time, the load element forming region R
From the re to the transistor formation region Rtr, a linear substrate region having a predetermined width and a rectangular substrate region surrounded by the groove are projected and remain in a continuous state. On each substrate region, a resistor 102a made of a linear polycrystalline silicon film and a rectangular polycrystalline silicon film 102b are continuously formed, and the resistor 102a and the polycrystalline silicon film 102b are Then, a linear etching stopper film 107a and a rectangular etching stopper film 107b are formed. afterwards,
A silicon oxide film 104 having a thickness of about 500 nm is deposited on the entire surface of the substrate including the groove.

Next, in the step shown in FIG. 5C, the etching stopper film 107 is formed by dry etching, for example.
silicon oxide film 1 until a and 107b are exposed on the surface.
04 is removed. By this step, the load element formation region R
re and the transistor forming region Rtr.
The periphery of 2a and the active region is surrounded by the isolation insulating film 104c.

Next, in the step shown in FIG. 6A, dry etching is performed using the photoresist film 108c formed on the substrate as a mask, and both ends of the linear etching stopper film 107a in the load element formation region Rre. And a rectangular etching stopper film 1 in the transistor forming region Rtr
07b is removed. At this time, the resistor 102a
Are exposed, and the rectangular polycrystalline silicon film 102b is exposed. Thereafter, arsenic ions are implanted at a dose of, for example, about 1 × 10 ¹⁵ cm ² using the etching stopper films 107a and 107b as a mask, thereby forming a resistor 102a serving as a contact region of a load element in the polycrystalline silicon film. The resistance of the rectangular polycrystalline silicon film 102b including both ends and the region to be the gate electrode of the MOS transistor is reduced.

Next, in a step shown in FIG. 6B, a low-resistance high-melting point metal material such as tungsten having a thickness of about 100 nm is formed on the entire surface of the substrate including the load element formation region Rre and the transistor formation region Rtr. After forming the metal film, dry etching is performed using the photoresist film 108d formed on the metal film as a mask. By this process,
Resistor 1 serving as a contact region of load element in metal film
The region including both ends and the periphery thereof and the region serving as the gate electrode of the MOS transistor are removed.
At the same time, the rectangular polycrystalline silicon film 102b in the transistor formation region Rtr is patterned into the same shape as the metal film. In the load element formation region Rre, the resistor 102
A terminal electrode 106a is formed on one end of and at the periphery thereof. On the active region of the transistor forming region Rtr, a lower electrode 102d made of a substantially H-shaped polycrystalline silicon film is formed. And, this lower electrode 10
2d and the other end of the resistor 102b,
Upper electrode 10 of the gate electrode of the V-shaped MOS transistor
6c is formed. That is, the transistor formation region R
In tr, the lower electrode 10 made of a polycrystalline silicon film is used.
A gate electrode 120 having 2d and an upper electrode 106c made of a metal film is formed. On the other hand, the upper electrode 10
6c functions as a terminal electrode of the load element in a portion straddling the end of the resistor 102a of the load element.

Thereafter, in a step shown in FIG. 6C, source / drain regions are formed on both sides of the gate electrode 120 by implanting high-concentration impurity ions by a general well-known step, and an interlayer is formed on the entire surface of the substrate. After the formation of the insulating film 110, a contact 111 that penetrates through the interlayer insulating film 110 and reaches the terminal electrode or the gate electrode 120 of the load element is formed. By forming a metal wiring 112 for connecting a gate electrode of a MOS transistor or a source / drain terminal as necessary for a circuit operation, a semiconductor device having a load element and a MOS transistor can be provided. Can be formed.

According to the manufacturing method of this embodiment, the first
Similarly to the embodiment, the resistor 102a of the load element and the lower electrode 102d of the gate electrode 120 can be formed from the common polycrystalline silicon film 102, so that the number of steps can be reduced and the load can be reduced. When a high-resistance polycrystalline silicon film is used to reduce the occupied area of the element, an increase in the process cost for forming the load element can be suppressed.

In addition, the terminal electrode on the end of the resistor 102a serving as the contact region of the load element and the upper electrode of the gate electrode 120 of the MOS transistor are continuously formed of a common metal film. Since no element isolation region is required, an increase in the area due to the connection between the load element and the gate electrode of the MOS transistor can be suppressed.

In particular, by forming the gate electrode 120 in a substantially H-shape, the gate width on the active region is constant even if the position of the gate electrode 120 is shifted due to a mask shift in a photolithography process. There is an advantage that the characteristics of the MOS transistor are kept constant.

In this embodiment, the impurity is doped into the polycrystalline silicon film 102b by ion implantation of arsenic. However, phosphorus or boron may be doped by ion implantation in the same manner.

The shape of the gate electrode does not necessarily have to be H-shaped. For example, the same effect can be exerted even in a shape in which the width is increased on one side with respect to the straight central portion.

(Third Embodiment) FIGS. 7A to 7C and FIGS. 8A to 8C are a plan view and a sectional view showing a manufacturing process of a semiconductor device according to a third embodiment. is there. In the present embodiment, the load element formation region Rre and the transistor formation region Rtr are adjacent to each other.

First, in a step shown in FIG. 7A, a silicon oxide film 10 serving as a gate insulating film is formed on a semiconductor substrate 100.
1 and the thickness of a part of the gate electrode and the resistor is 100
a polycrystalline silicon film 102 having a thickness of about 100 nm
An etching stopper film 107 made of a silicon nitride film having a thickness of about 150 nm is sequentially formed.

Next, in the step shown in FIG. 7B, the etching stopper film 107 and the polycrystalline silicon film 1 are left except for a region where a resistor is to be formed and a region to be an active region.
02, the silicon oxide film 101 and the semiconductor substrate 100
A groove is formed by removing the substrate from the substrate surface to a predetermined depth (for example, a depth of about 300 nm) by dry etching. At this time, from the load element formation region Rre to the transistor formation region Rtr, a linear substrate region having a predetermined width and a rectangular substrate region surrounded by the groove are continuously formed. On each substrate region, a resistor 102a made of a linear polycrystalline silicon film and a rectangular polycrystalline silicon film 102b are continuously formed, and the resistor 102a and the polycrystalline silicon film 102b are Then, a linear etching stopper film 107a and a rectangular etching stopper film 107b are formed. Thereafter, a silicon oxide film 10 having a thickness of about 500 nm is formed on the entire surface of the substrate including the groove.
4 is deposited.

Next, in the step shown in FIG. 7C, the etching stopper film 107 is formed by dry etching, for example.
silicon oxide film 1 until a and 107b are exposed on the surface.
04 is removed. By this step, the load element formation region R
re and the transistor forming region Rtr.
The periphery of 2a and the active region is surrounded by the isolation insulating film 104c.

Next, in the step shown in FIG. 8A, dry etching is performed using the photoresist film 108e formed on the substrate as a mask, and both ends of the linear etching stopper film 107a in the load element formation region Rre. And a rectangular etching stopper film 1 in the transistor forming region Rtr
07b is removed. At this time, the resistor 102a
Are exposed, and the rectangular polycrystalline silicon film 102b is exposed. Thereafter, arsenic ions are implanted at a dose of, for example, about 1 × 10 ¹⁵ cm ² using the etching stopper films 107a and 107b as a mask, thereby forming a resistor 102a serving as a contact region of a load element in the polycrystalline silicon film. The resistance of the rectangular polycrystalline silicon film 102b including both ends and the region to be the gate electrode of the MOS transistor is reduced.

Next, in a step shown in FIG. 8B, a low-resistance metal material having a thickness of about 100 nm made of, for example, tungsten is formed on the entire surface of the substrate including the load element formation region Rre and the transistor formation region Rtr. After forming the metal film, dry etching is performed using the photoresist film 108f formed on the metal film as a mask. By this process,
Resistor 1 serving as a contact region of load element in metal film
The region including both ends and the periphery thereof and the region serving as the gate electrode of the MOS transistor are removed.
At the same time, the rectangular polycrystalline silicon film 102b in the transistor formation region Rtr is patterned into the same shape as the metal film. In the load element formation region Rre, the terminal electrodes 106 are provided on both ends of the resistor 102a and the periphery thereof.
a is formed. On the active region of the transistor formation region Rtr, a lower electrode 102e made of a linear polycrystalline silicon film and an upper electrode 1 made of a metal film having the same shape are formed.
A gate electrode 120 made of 06d is formed. At this time, one end of the resistor 102a, which is a contact region of the load element, is adjacent to the source / drain region of the MOS transistor.

Then, in a step shown in FIG. 8C, source / drain regions are formed on both sides of the gate electrode 120 by implanting high-concentration impurity ions by a general well-known process, and an interlayer After forming the insulating film 110, a contact 111 that penetrates the interlayer insulating film 110 and is connected to a terminal electrode or a gate electrode 120 of the load element is formed.
At this time, one contact 111 is formed over one terminal electrode 106a of the load element and one of the source / drain regions of the MOS transistor. By forming a metal wiring 112 for connecting a gate electrode of a MOS transistor or a source / drain terminal as necessary for a circuit operation, a semiconductor device having a load element and a MOS transistor can be provided. Can be formed.

According to the manufacturing method of this embodiment, the first
Similarly to the embodiment, the resistor 102a of the load element and the lower electrode 102e of the gate electrode 120 can be formed from the common polycrystalline silicon film 102, so that the number of steps can be reduced and the load can be reduced. When a high-resistance polycrystalline silicon film is used to reduce the occupied area of the element, an increase in the process cost for forming the load element can be suppressed.

In addition, one terminal electrode 106 of the load element
Since a is connected to the source / drain region of the MOS transistor by a common contact 111, an element isolation region is not required therebetween. For this reason, it is possible to suppress an increase in area due to the connection between the load element and the source / drain terminals.

In this embodiment, the doping of impurities into the polycrystalline silicon film 102b is performed by arsenic ion implantation, but phosphorus or boron may be similarly doped by ion implantation.

(Fourth Embodiment) FIGS. 9A to 9C
14A is a plan view of a semiconductor device according to a fourth embodiment, a cross-sectional view taken along line IXb-IXb in the plan view, and an equivalent circuit diagram of the semiconductor device.

As shown in FIG. 9A, the semiconductor device of the present embodiment has a first load element (resistance R1) and a second load element (resistance R2). Each load element has a resistor 102a shown in FIG. 9B, and the resistance value is defined by the shape of the resistor 102a. Each resistor 102a is formed in a zigzag shape on a plane, including a plurality of straight portions parallel to each other, and a corner portion for connecting the straight portions in series to be integrated. At each corner of the resistor 102a,
A low-resistance terminal electrode 106a made of a metal film is formed, and the high-resistance region of the resistor 102a of the load element is limited to a linear portion. That is, the terminal electrode 10
The specific resistance 6a is the resistance of the resistor 10 made of a polycrystalline silicon film.
Since the specific resistance is extremely small as compared with the specific resistance of the resistor 2a,
The configuration is such that the resistance value of the load element can be set by the total length of the linear portions 02a.

The present semiconductor device constitutes, for example, a part of a step-down power supply circuit, and divides an input voltage by a value determined by a ratio (R1 / R2) of resistance values of the first and second load elements. It is configured to press and output. That is, as shown in FIG. 9 (c), the voltage signal V0 input from the terminal electrode 106Y drops according to the resistance value of each load element, and becomes a low voltage signal V1, V2 from each terminal electrode 106X, 106Z. Is output.

Here, as shown in FIG. 9B, each of the load elements is connected to one straight portion of the resistor 102a.
It has a cross-sectional structure as shown in the first embodiment. In other words, one resistor 102a (width w1 or w2, width w1 or w2, 1) made of a polycrystalline silicon film linearly patterned by the isolation insulating film 104b filling a groove (not shown) reaching a predetermined depth of the semiconductor substrate 100. Height h0
(Common)). Then, an etching stopper film 1 for defining the lengths l1 and l2 of the high-resistance region of the resistor 102a on the region excluding both ends of the resistor 102a.
A terminal electrode 106a for signal connection is provided at both ends of the resistor 102a. In addition,
On the entire surface of the substrate, an interlayer insulating film 110 is formed. Although not shown, a metal wiring connected to the terminal electrode 106a via a contact is formed on the interlayer insulating film 110.

According to the structure of the load element of the present embodiment, in addition to the basic effects of the above-described first embodiment, the resistance value is formed at the corner where the resistance value is liable to greatly change due to variation in shape in the manufacturing process. Since the terminal electrode 106 made of a metal film that is negligibly small is formed and the resistance value is defined only by the linear portion of the resistor 102a, which is easy to form a relatively stable shape, a high integration by the meandering shape is achieved. And a load element having a stable resistance value.

However, a portion of the terminal electrode 106a which is an end of the resistor 102a may be formed in the middle of the linear portion. In that case, the resistance value of the load element is determined by the total length obtained by adding the length of the end portion to the number of linear portions that are entirely in the high resistance region.

Particularly, in the case of the semiconductor device arranged in the step-down power supply circuit of the present embodiment, the lengths of the high resistance regions of the resistors 102a of the first and second load elements are equal (11 = l).
2) Therefore, the resistance ratio of the load element that determines the output voltage is given by the following equation (1): R1 / R2 = (n1 × 11 / w1) / (n2 × 12 / w2) = (n1 / w1) / (n2 / w2) given by (1). Therefore, the resistance ratio of the load element does not depend on the lengths l1 and l2 of the high-resistance region, but is determined by the number of linear portions of the zigzag-shaped resistor 102a.
The following remarkable effects can be exhibited.

FIGS. 10A to 10C are cross-sectional views showing the process shown in FIG. 2B during the manufacturing process of the first embodiment in more detail. However, the structure in a cross section orthogonal to the cross section in FIG. FIG. 10 (a)
As shown in FIG. 7, after the insulating film 105x for an etching stopper is deposited on the entire surface in a state where the resistor 102a is formed on the semiconductor substrate 100, a photoresist film 108a is formed on the insulating film 105x for the etching stopper. Is done. Then, etching is performed using the photoresist film 105a as a mask, and the etching stopper insulating film 105x is patterned into a rectangular etching stopper film 105 as shown in FIG. 2B. At this time, ideally, as shown in FIG. 10B, the end of the photoresist film 108a coincides with the end of the etching stopper film 105, and the dimension l of the photoresist film 108a is Should be the length dimension. However, in reality, the etching stopper film 105 often recedes due to the etching process. In such a case, the dimension of the etching stopper film 105 is (l-Δl) as shown in FIG. become. That is, the length of the high resistance region in the linear portion of the resistor 102a defined by the etching stopper film 105 is 1−
Since it is Δl, the resistance values R1 and R2 are represented by the following equation: R1 = ρ · n1 (11−Δ1) / w1 · h0 R2 = ρ · n2 (12−Δl) / w2 · h0 .

Here, when l1 = l2, l1-Δ
l = l2-Δl. Accordingly, the ratio of the resistance value of each load element is expressed by the following equation (2). = (N1 / w1) / (n2 / w2) (2) This equation (2) is exactly the same as the above equation (1), and the etching stopper film 1 during etching is
This shows that the ratio of the resistance values of the first and second load elements does not change even if the retraction of the load element 05 occurs. Therefore, there is no variation in output voltage due to the presence or absence or magnitude of the recess of the etching stopper film 105 due to the etching process, and a stable output voltage can be obtained.

Note that such a phenomenon similar to the recession of the etching stopper film may occur when a manufacturing process different from that of the present embodiment is used. Also in this case, as in the present embodiment, even if an error occurs in the length of the high-resistance region due to a variation in the process, the ratio of the divided voltages is always kept equal.

In each of the above embodiments, the silicon nitride film is formed as the etching stopper film covering the resistor. However, the present invention is not limited to such an embodiment, and instead of the silicon nitride film, a polycrystalline silicon film may be used. A film made of an insulating material having a high etching selectivity with respect to the silicon film may be formed.

[0101]

According to the first aspect of the present invention, a linear resistor formed on a substrate region surrounded by a groove and an isolation insulating film filling the groove and the sides of the resistor are formed on the semiconductor substrate. Is provided, it is possible to provide a semiconductor device provided with a load element having high performance which can be integrated with less leakage current and parasitic capacitance between the resistors.

Each of claims 2 to 1 cited in claim 1
According to 0, the following effects can be exhibited in addition to the effects of the first aspect.

According to the second aspect, in the first aspect, the resistor of the load element is formed in a zigzag shape on a plane, and the low-resistance terminal electrode covering the corner portion is provided. And the characteristics can be stabilized.

According to claim 3, in claim 2, a plurality of load elements are arranged in parallel to one input terminal, and the input voltage signal is divided through each load element and output. Therefore, it is possible to provide a semiconductor device capable of supplying a voltage with a small variation in output voltage.

According to a fourth aspect, in the first aspect, the lower electrode formed of the first conductor film common to the resistor of the load element and the first electrode common to the terminal electrode of the load element are formed on the semiconductor substrate. Since a transistor having an upper electrode composed of two conductive films is further provided, a semiconductor device in which a load element with a small occupied area and a transistor with good operation characteristics are mounted on a common semiconductor substrate is provided. be able to.

The structure of claim 4 is the structure of claims 11, 12, 1
It can be easily realized by the method of manufacturing a semiconductor device according to 3 or 14.

According to claim 5, in claim 4, the terminal electrode of the resistor is formed continuously with the gate electrode of the transistor, so that the occupied area of the entire semiconductor device can be further reduced.

The structure of claim 5 can be easily realized by the method of manufacturing a semiconductor device of claim 16.

According to a sixth aspect of the present invention, in the fifth aspect, the structure has a linear portion functioning as a gate of the transistor and a wide portion not functioning as a gate at both ends of the transistor. It is possible to stabilize transistor characteristics with respect to variations.

The structure of claim 6 can be easily realized by the method of manufacturing a semiconductor device of claim 17.

According to claim 7, in claim 4, the terminal electrode of the load element and the source / drain region of the transistor are connected by a common contact, so that the occupation area of the whole semiconductor device is further reduced. be able to.

The structure of claim 7 can be easily realized by the method of manufacturing a semiconductor device of claim 18.

According to claim 8, in claim 4 or the like,
Since the first conductive film is made of polysilicon and the second conductive film is made of refractory metal, a transistor having a low-resistance gate electrode and a load element having a high resistance and a small occupation area are shared by a common semiconductor substrate. Can be provided above.

According to the ninth aspect, in the eighth aspect, a structure in which a high-concentration impurity is introduced into a portion of the first conductor film to be a lower electrode of the gate electrode to reduce the resistance is provided.
By suppressing depletion of the lower electrode of the gate electrode, driving power of the transistor can be improved.

The structure according to claim 9 can be easily realized by the method for manufacturing a semiconductor device according to claim 15.

According to the tenth aspect, in the fourth aspect, the second conductor film is composed of a laminated film of the refractory metal film and the barrier conductor film thereunder. Reaction with semiconductor atoms can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first half of a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view illustrating an intermediate portion in a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view showing the latter half of the manufacturing process of the semiconductor device according to the first embodiment;

FIG. 4 is a cross-sectional view for explaining the effect of the structure of the load element in the semiconductor device according to the first embodiment.

FIG. 5 is a cross-sectional view illustrating a first half of a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 6 is a cross-sectional view showing the latter half of the manufacturing process of the semiconductor device according to the second embodiment;

FIG. 7 is a cross-sectional view illustrating a first half of a manufacturing process of a semiconductor device according to a third embodiment.

FIG. 8 is a cross-sectional view showing the latter half of the manufacturing process of the semiconductor device according to the third embodiment.

FIG. 9 is a plan view, a sectional view, and an equivalent circuit diagram of a load element arranged in a step-down power supply circuit according to a fourth embodiment.

FIG. 10 is a cross-sectional view for explaining advantages of the load element according to the fourth embodiment.

FIG. 11 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device on which a load element and a MOS transistor are mounted.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 101 Silicon oxide film 102 Polycrystalline silicon film 102a Resistor 102c Polycrystalline silicon film 102c Lower electrode 103 Groove 104 Silicon oxide film 104a-c Isolation insulating film 105 Etching stopper film 106 Metal film 106a Terminal electrode 106b-d Upper part Electrode 107 etching stopper film 108 photoresist film 110 load element 111 contact 112 metal wiring 120 gate electrode

Claims (18)

[Claims] At least one of a plurality of semiconductor devices formed on a semiconductor substrate is provided.
A semiconductor device provided with three load elements, wherein a groove formed so as to project a linear substrate region on the main surface side of the semiconductor substrate; and a groove formed on the linear substrate region, the same as the substrate region. A semiconductor, comprising: a resistor of the load element formed of a first conductor film formed to have a planar shape; and a separation insulating film that fills a side of the groove and the resistor. apparatus. 2. The semiconductor device according to claim 1, wherein the resistor of the load element is formed in a zigzag shape including a plurality of straight portions and a corner portion connecting the straight portions on a plane. A terminal electrode formed of a second conductor film having a specific resistance smaller than that of the first conductor film and covering a portion of each straight portion of the resistor other than a substantially uniform length and the corner portion; A semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 2, wherein a plurality of load elements having the straight portions having the same length are arranged in parallel to one input terminal, and a voltage input to the input terminal is provided. A semiconductor device, wherein a signal is output through each of the load elements. 4. The semiconductor device according to claim 1, wherein a terminal electrode made of a second conductor film having a lower specific resistance than the first conductor film is provided on a part of the resistor of the load element. An isolation groove formed so as to protrude a substrate region serving as an active region on the main surface side of the semiconductor substrate; and an element isolation formed by filling the isolation groove with the isolation insulating film. And a transistor formed in the active region and having a gate electrode including a lower electrode made of the first conductor film and an upper electrode made of the second conductor film. Semiconductor device. 5. The semiconductor device according to claim 4, wherein the resistor is formed continuously with a lower electrode of the gate electrode, and the terminal electrode is formed continuously with an upper electrode of the gate electrode. A semiconductor device characterized by being performed. 6. The semiconductor device according to claim 5, wherein a gate electrode of said transistor is formed on said active region.
A semiconductor device having a narrow portion functioning as a gate and a wide portion formed at both ends of the narrow portion and not functioning as a gate. 7. The semiconductor device according to claim 4, wherein a source electrode is provided on both sides of said gate electrode in said active region.
A drain region is formed, an interlayer insulating film is formed above the resistor and the transistor, and one of the source / drain regions and the resistor is formed through the interlayer insulating film. A semiconductor device further comprising: a contact hole reaching a terminal electrode; and a connection conductor film embedded in the contact hole. 8. The semiconductor device according to claim 4, wherein said first conductive film is made of polysilicon, and said second conductive film is made of refractory metal. A semiconductor device characterized by being constituted. 9. The semiconductor device according to claim 8, wherein a portion of the first conductor film which is to be a lower electrode of the gate electrode is doped with a high-concentration impurity to be a resistor of the load element. A semiconductor device having a lower specific resistance than a portion. 10. The semiconductor device according to claim 4, wherein said second conductor film is a laminated film of a refractory metal film and a barrier conductor film thereunder. Characteristic semiconductor device. 11. A first step of forming a first conductor film on a semiconductor substrate having a load element formation region and a transistor formation region, and from a surface of the first conductor film and the semiconductor substrate to a predetermined depth. Is selectively removed to leave a linear substrate region and a resistor made of the first conductive film in the load element formation region, and a substrate region to be an active region in the transistor formation region and the same. A second step of forming a groove that leaves the first conductive film above, a third step of filling the groove with an insulating film for isolation, and a fourth step of depositing a second conductive film on the substrate A fifth step of patterning the second conductor film in the load element formation region to form a terminal electrode connected to the resistor; and a first and second conductor in the transistor formation region Putter membrane And ring method of manufacturing a semiconductor device characterized by and a sixth step of forming a gate electrode and the first conductor film as the lower electrode and the second conductive film top electrode. 12. The method for manufacturing a semiconductor device according to claim 11, wherein before the fourth step, an insulating film for an etching stopper is formed to cover a region of the resistor other than a region in contact with the terminal electrode. A manufacturing method of a semiconductor device, wherein the fifth and sixth steps are performed continuously using a common etching mask. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the step of forming the etching stopper insulating film is performed after the first step and before the second step. Semiconductor device manufacturing method. 14. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming the etching stopper insulating film is performed after the third step and before the fourth step. Semiconductor device manufacturing method. 15. The method of manufacturing a semiconductor device according to claim 12, wherein in the first step, a polycrystalline silicon film is deposited as the first conductor film, and the etching is performed before the fourth step. A method for manufacturing a semiconductor device, further comprising a step of introducing an impurity into the first conductive film using the stopper film as a mask. 16. The method of manufacturing a semiconductor device according to claim 11, wherein the load element formation region and the transistor formation region are adjacent to each other, and in the second step, The first conductor film is integrally left over the load element formation region and the transistor formation region. In the fifth and sixth steps, the terminal electrode of the load element and the upper electrode of the gate electrode are integrated. A method for manufacturing a semiconductor device, characterized in that the method is performed in the following manner. 17. The method of manufacturing a semiconductor device according to claim 16, wherein in the fifth and sixth steps, the gate electrode in the transistor formation region has a narrow portion functioning as a gate of a transistor and gates at both ends thereof. A method of manufacturing a semiconductor device, comprising patterning the first and second conductive films so as to have a wide portion that does not function as a semiconductor device. 18. The semiconductor device according to claim 11, wherein the load element formation region and the transistor formation region are adjacent to each other, and after the sixth step, the transistor formation is performed. Forming an impurity diffusion region on both sides of the gate electrode in the region; depositing an interlayer insulating film on the substrate; forming the terminal electrode and the impurity diffusion region in the transistor forming region on the interlayer insulating film. A method for manufacturing a semiconductor device, further comprising: a step of forming a common contact hole to reach; and a step of depositing a conductive material in the contact hole.