JPH1187541A - Semiconductor device having pillar structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controllable conduction device having an erecting pillar structure having a sidewall and a top surface and a side gate structure alongside the sidewall of a pillar structure. SOLUTION: An erecting pillar structure 20 comprising a sidewall 22 and a top surface 21 and a side gate structure 23 alongside the sidewall of a pillar structure is provided. The erecting pillar structure has regions 6 and 7 made of relatively conductive material and non-conductive material. Under a 1st condition, charge carrier flow can occur through the pillar structure. Under a 2nd condition, the regions present a tunnel barrier structure that inhibits the charge carrier flow through the pillar structure. A side gate structure controls charge carrier transport by applying a voltage to the pillar structure through the sidewall. The device can be used as a memory having a memory node 10 beneath the pillar structure. The memory node stores charges which are passed by a control electrode 11 on the top surface 21 of the pillar structure. The device can also be configured as a transistor with a source 5 on the pillar and a drain underneath the pillar.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a controllable conduction device for use in a memory or transistor structure.

[0002]

2. Description of the Related Art Our European patent application EP 96308283.9, filed Nov. 15, 1996 (EPC
54 (3)) describes a memory device having a memory node into which electric charges are written from a control electrode via a tunnel barrier structure. This accumulated charge affects the conductivity of the source / drain path, and data is read out by monitoring the conductivity of this path. This charge barrier configuration is composed of multiple tunnel barriers. The multi-tunnel barrier consists of alternating layers of a 5 nm thick polysilicon layer and a 2 nm thick silicon nitride layer covering a polycrystalline silicon layer, some of which function as memory nodes. Other barrier structures have been described having conductive nanometer-scale conductive islands acting as memory nodes dispersed in an insulating matrix. The advantage of the tunnel barrier structure is that it reduces the leakage current from the memory node without degrading the read / write time of the memory. Different types of memory devices have been described. In the first type, charge carriers from the control electrode pass through the tunnel barrier structure to the memory node according to the voltage applied to the control electrode. In a second type of device, a gate is added to the tunnel barrier structure to control the transfer of charge carriers from the control electrode to the memory node.

The charge barrier structure is described in our European patent application EP 97305399.
As described in No. 4, it can be used for a controlled conduction device such as a transistor.
Using this tunnel barrier structure, a conduction path is provided between the source and the drain. When switched on,
Charge carriers can flow between the source and drain, but when switched off, the barrier structure prevents charge leakage through the path. Therefore, a large on / off current ratio can be obtained.

[0004]

SUMMARY OF THE INVENTION The present invention is directed to various inventive improvements and modifications to the device described above.

[0005] Our European patent application EP9630 mentioned above.
Considering the second type of memory device described in U.S. Pat. No. 8283.9, the tunnel barrier structure is configured as upstanding pillars and control electrodes covering the pillars. The added gate applies an electric field, mainly from top to bottom, via pillar structures to write charge to the memory nodes. The above-mentioned EP 97305399.4
The structure of the gate of the transistor described in the above item is configured to apply an electric field downward to the pillar structure in a similar manner. In this structure, a high electric field is applied between the gate and the memory node in the case of a memory device, and between the gate and the drain in the case of a transistor. This high electric field generates electron-hole pairs, and charges are stored near the gate structure. This shields the confinement potential.

[0006]

SUMMARY OF THE INVENTION To overcome these problems, the present invention, in a first aspect, provides an upright pillar structure having a sidewall and a top surface, and a side wall along the sidewall of the pillar structure. A gated structure. The upright pillar structure has a region of a relatively conductive material and a region of a non-conductive material,
In the state, charge carrier flow can occur through the pillar structure, and in the second state, those regions exhibit a tunnel barrier structure that blocks charge carrier flow through the pillar structure. The side gate structure is configured to control its electrical conductivity by applying an electric field to the pillar structure through the sidewall.

The device according to the invention can be used in a memory with a memory node for receiving charge carriers flowing along a path through a pillar structure. By manipulating the side gate to control the charge carrier flow along the path, the charge stored at the node can be controlled.

[0008] The device can also be operated as a transistor. In the transistor, a source region and a drain region are provided such that a source-drain charge carrier flow path is provided through the pillar structure, and the side gate is operated to control the charge carrier flow in the path.

The side gate structure may be constituted by a Schottky gate or a junction gate.

[0010] One embodiment of the memory device described in the above-mentioned EP 96308283.9 is non-volatile. The barrier structure has a 5 nm thick insulating silicon nitride barrier located between 30 nm thick undoped silicon layers. The resulting energy band profile is as follows: That is, the charge stored in the memory node is held by the barrier structure when no control charge is applied to the memory device.

The present invention provides an improved non-volatile structure. According to another aspect of the present invention, there is provided the following memory device. That is, the memory device has a region of relatively conductive material and a region of non-conductive material, wherein a charge carrier flow can occur through the pillar structure in a first state and a second state. In this state, the region presents a tunnel barrier structure that blocks charge carrier flow in the structure, a memory node that receives charge carriers moving along a path through the structure, and a node that passes through the structure. A control electrode for supplying charge carriers to said path to be stored,
Each has a dimensionally relatively narrow barrier component adjacent to the memory node and the control electrode, and a dimensionally relatively wide barrier component between the narrow barrier components, and this barrier component causes non-volatile charge accumulation at the node. The region of non-conductive material is configured to provide an energy profile configured to provide.

One embodiment of the transistor described in our above EP 97305399.4 has a lateral structure (l
ateral structure). The source and the drain are laterally separated, and a gate is arranged between them.

The present invention in another aspect provides an improved device with this universal lateral structure. According to yet another aspect of the present invention, there is provided a controllable conducting device comprising a substrate, a plurality of control elements laterally spaced on the substrate, and a control device for controlling the same. A channel structure extending between and electrically connected to the elements, and a gate region, the channel structure comprising a region of relatively conductive material and a region of non-conductive material; In the first state, charge carrier flow can occur through the structure, and in the second state, the region presents a tunnel barrier structure that blocks charge carrier flow, and the gate region applies an electric field to the channel structure. And wherein the channel structure is configured to overlap below one of the control elements on the substrate and over the other of the control elements.

The device can be configured as a transistor or a memory device. Therefore, the control element may be a source region and a drain region,
Alternatively, one of them may be in memory mode.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION For better understanding of the present invention, embodiments of the present invention will be illustratively described below with reference to the accompanying drawings.

FIG. 1 illustrates our above EP 9730539.
An example of the transistor device described in No. 9.4 is shown as a cross section thereof. The device has a substrate 1, on which a drain region 2 consists of a layer of n-doped polysilicon, on which a multilayer structure 3 is provided. This multilayer structure 3
Results in a multiple tunnel junction structure. The layer structure 3 consists of alternating layers of relatively conductive and non-conductive materials such as polysilicon and silicon nitride. Gate regions 4a and 4b are provided on the multilayer structure 3, and a source region 5 is arranged between the two gate regions. The source and gate regions 4, 5 can be made of n-doped polysilicon. In use, current flows along the path P from the drain 2 to the source 5 across the plane of the layers of the structure. The voltage applied to the gates 4a, 4b controls the drain / source current.

Referring to the multilayer structure 3, it consists of a conductive polysilicon layer 6 arranged between layers 7 of electrically insulating silicon nitride material. The insulating layer 7 is typically on the order of 3 nm in thickness and provides an energy band diagram as shown in FIG. The insulating layer 7 provides a relatively high barrier 8 with a relatively narrow width dimension w and a height B corresponding to the width of the individual layers 7. In this example, the width dimension w is on the order of 3 nm. The spacing between the individual barriers 8 depends on the thickness of the layer 6 of conductive silicon material. Layer structure 3
Near the top and bottom of the layer 6, the layer 6 has a thickness W1 on the order of 50 nm, and in the central region of the stack, the layer 6 has a thickness W2 on the order of 5 nm.

The layers of the layer structure 3 collectively form a barrier height b
Bring. This barrier height b is the barrier height B of the individual layers.
, But relatively wide in relation to its physical dimensions corresponding to the width WT of the entire multilayer structure 3.

When a source-drain voltage is applied to the device, the energy diagram of the multilayer structure 3 is shown in FIG.
The structure shown in FIG. It can be seen that, while tunneling through the relatively narrow barrier w, the electrons can drop the potential gradient provided by the source-drain voltage and pass from the source 5 to the drain 2.

In the structure shown in FIG. 2A, when the source / drain voltage is 0, the relatively wide but low barrier b provided collectively by the layer structure 3 has a relatively high but narrow height B. In combination with the barrier 8, a barrier structure is provided that prevents charge carrier conduction between the drain 2 and the source 5.
The wide barrier b prevents tunneling of electrons between the source and the drain, and the separate individual barriers 8 provide electron traps that prevent macroscopic quantum tunneling. The fact that the top and bottom barriers of the stack are separated by a spacing W1 that is greater than the spacing W2 of the layers inside the stack contributes to the wide barrier height b.

When a source-drain voltage is applied, conduction occurs from the drain to the source in the manner of a conventional transistor, and a conventional current of ^10-13 powers per second flows. Conduction along the path can be controlled by applying a gate voltage to the gate 4. The gate voltage produces an electric field that "pinches" the width of the source-drain conduction path P by an amount that depends on the gate voltage. However, a problem with this configuration is that a relatively high electric field is applied between the gate 4 and the drain 2. This high electric field creates an electron-hole pair induced by the electric field,
The confinement potential is shielded by the accumulation of carriers near the gate 4.

An embodiment of the memory device corresponding to FIG. 29 of our EP 96308283.9 is described below with reference to FIG. This memory device is shown in cross section and is formed on a silicon substrate 1. This device has a memory node 10 as a 5 nm layer of polysilicon, on which a layer structure 3 is provided, which provides a multi-tunnel barrier structure, much like that shown in FIG. The layer structure 3 is formed by alternating layers of silicon and silicon nitride in the manner described above. 30n of n-type silicon
Charge carriers can be written to the memory node 10 from the control electrode as layer m with a thickness of m via the layer structure 3. The control electrode 11 has an intrinsic (intrinsic) thickness of 30 nm.
ic) formed on the conductive layer 12 of silicon; The control electrode 11 is sealed in the electrically insulating silicon dioxide layers 13 and 14.

The gate electrode 15 of polysilicon material covers the layer structure 3 so as to apply an electric field mainly downward to the layer structure, thereby selectively removing the potential barrier structure provided by the layer 3. Up and down, charges can be selectively written to the memory node 10. Polysilicon gate 15 is electrically insulated from control electrode 11 by silicon dioxides 13 and 14. This gate 15
Is also insulated from the side edges of the layer structure 3 by the thick oxide layer 16. A significant electric field does not enter from the gate 15 through the side edge of the layer structure 3, and an electric field (the condu
The ction controlling field goes down from the top surface of the layer structure.

Memory node 10 has a field effect (fie) for controlling current flow between source 17 and drain 18 implanted in the substrate by conventional doping techniques.
ld effect) acts as a gate. Conduction path 19 extends between source 17 and drain 18, the conductivity of which varies depending on the level of charge stored on memory node 10. Using the multilayer structure 3 to provide a multiple tunnel junction between the control electrode 11 and the memory node 10 significantly reduces leakage current from the node 10. But,
Both gate electrodes 15 do not effectively raise or lower the potential barrier structure below control electrode 11, but increase the electric field in the region between the gate region and memory node 10.

The present invention provides an improved gate that can be used as a transistor according to the principle of FIG. 1 or as a memory device according to the principle of FIG. 3 described below with reference to FIGS. . FIG. 4 (a) shows an improved gate structure for a transistor operating according to the principles described with reference to FIG. 1, and FIG. 4 (b) is applied to a memory device operating according to the memory principle of FIG. 2 shows the same gate structure.

The layer structure 3 shown in FIGS.
It is configured as a pillar 20 upstanding from the substrate 1 and has a top surface 21 and a peripheral sidewall 22 extending around the pillar. According to the present invention, the side gate 23 is
And by selectively raising and lowering the barrier structure, an electric field is generated in the pillar structure through the side wall to control its conductivity. No significant control electric field is applied from the top surface 21 by the side gate 23.

In use, charge carriers flow vertically from the electrodes formed on the top surface 21 through the pillar structure.
In the transistor according to the invention shown in FIG. 4 (a), the top electrode comprises a source 5 operable in the manner described above with reference to FIG. 1, and a drain 2 is provided on the lower surface of the pillar. However, when the device is configured as a memory as shown in FIG. 4B, the top electrode operates as the control electrode 11 described above with reference to FIG. 3, and the memory node 10 is arranged on the lower surface of the pillar structure. . The electric charge stored in the memory node 10 is transferred to the path 19 between the source region 17 and the drain region 18 formed on the substrate 1 by the method described with reference to FIG.
To control the conductivity.

The side gate 23 is formed of, for example, a conductive polysilicon material on the electric insulating layer 24 which can be formed of silicon dioxide. This side gate 23 does not extend into the region occupied by the topmost electrodes 5 and 11,
The gate voltage operates on the barrier structure to reduce the high electric field region.

The layers 6, 7 are typically formed with the thickness and composition described above in FIG. As a result, the top electrode 5,
When no voltage is applied to 11 or the side gate 23, the energy band structure of the device is as shown in FIG. The insulating layer 7 provides a relatively high barrier 8 with a relatively narrow width dimension w corresponding to the width of the individual layers 7.
In this example, the width dimension w is on the order of 3 nm or less, typically on the order of 2 nm.

The spacing between the individual barriers 8 is determined by the thickness of the layer 6 of conductive silicon material. Near the top and bottom of the layer structure 3, the thickness w of the layer 6 is of the order of 50 nm, and the thickness W2 of the layer 6 in the central region of the stack is 10 n
m or less, for example, on the order of 5 nm.

The plurality of layers of the structure 3 are collectively represented as
The overall multilayer structure 3 is lower than the barrier height B of the individual layers.
Resulting in a relatively wide barrier height b associated with its physical dimensions corresponding to a width WT of.

When a voltage is applied to the side gate 23, the entire energy band diagram shown in FIG. When a voltage is applied to the top electrodes 5 and 11, the band diagram is deformed in the manner shown in FIG. 2B, and charge carriers pass downward from the top electrodes 5 and 11 through the pillar structure. Depending on whether it reaches the drain 2 or the memory node 10. When no voltage is applied to the top electrodes 5, 11, the barrier structure prevents charge leakage along the path between the top and bottom of the pillar structure.

When used as a memory as shown in FIG. 4B, this device operates as a high-speed static random access memory. The barrier height b provides a small built-in potential of about 0.2 V, and the threshold voltage required for the gate electrode 23 under the condition that the control electrode 11 and the memory node 10 are zero-biased is −
1.0V. The overall barrier height provided by the pillar structure is controlled by the bias applied to gate 23. When a negative gate bias of about -4.0 V is applied to the gate electrode 23, the accumulated charge is held in the memory node 10. This negative gate bias creates a potential barrier of about 3 eV. This height is sufficient to maintain the stored electrons at the node for a period of about ten years.

To write information, the voltage applied to the gate 23 is maintained at 0, and a bias voltage of 1.0 V is applied to the control electrode 11. At this time, the entire barrier structure of the pillar exhibits a slope inclined downward as shown in FIG. 2B, so that electrons can tunnel to the individual barriers 8 and reach the memory node 10. To read information, a voltage of -3.0 V is applied to the gate electrode 23, and the source / drain current flowing through the channel 19 is monitored by the method described above with reference to FIG.

When this device is used as a transistor as shown in FIG. 4A, that is, when the top electrode 5 constitutes a source and the lower surface region 2 constitutes a drain, the device is a high-speed normally-on transistor. Operate. A more practical example of such a transistor is described below with reference to FIG.

As shown in FIG. 6B, a thermally grown silicon dioxide layer 1 is provided on a silicon wafer 25 functioning as a substrate. Drain 2 is formed of an n ⁺ polysilicon layer formed on silicon oxide layer 1. This drain is sealed by an electrically insulating layer 26 of silicon dioxide.

Layer structure 3 resulting in a multiple tunnel junction structure
Is formed so as to cover the drain 2. Layer structure 3
Is formed as a pillar 20 so as to stand upright from the drain region 2 and is surrounded by an insulating silicon dioxide layer 24. The source 5 has n ⁺ which covers the top surface of the pillar 20.
It consists of a polysilicon layer.

The gate 23 is in contact with the protective insulating layer 24,
Forming a boundary with the side wall 22 of the pillar 20, but with the top surface 2
1 is not coated.

This structure corresponds to the protective insulating layer 2 described in detail below.
7 coated. As can be seen from FIG.
A contact window is formed in oxide layer 27 and source electrode 28 is formed.
The S, drain electrode 28D and gate electrode 28G are provided for connection with the outside.

A method for manufacturing the device shown in FIG. 6 will be described below with reference to FIG.

Referring to FIG. 7 (a), the starting material is a silicon wafer 25, which is thermally oxidized at 1000 ° C. to form a 600 nm layer 1 of SiO ₂ . This layer functions as an insulating substrate. Next, a layer 2 used for forming a drain is formed on the SiO ₂ layer 1. This layer 2 consists of 10 nm thick polysilicon grown in a reactor by low pressure chemical vapor deposition (LPCVD). next,
A 10 nm thick layer of silicon dioxide is grown on the surface of layer 2. Next, by implanting arsenic ions into the layer 2, an n ⁺ -doped conductive layer that can be used as a drain is formed. Arsenic ion is 25K in the oxide layer
It is implanted with an energy of the order of eV and a dose of 3 × 10 ¹⁵ cm ⁻² (not shown). This oxide layer
Next, it is removed by wet etching using a 20: 1 RHF solution.

After that, a multilayer structure 3 is formed on the layer 2.
The multilayer structure 3 is composed of a laminate of a silicon layer 6 and a silicon nitride layer 7. First, a silicon layer 61 with a relatively large thickness W1, then, for the majority of the laminate, the layers 6 ₂
Is formed with a thickness of the order of W2 = 5 nm. further,
On top of the laminate, at least one layer 61 of thickness W1
To form In this example, two layers 61 are formed on top. This can be seen in detail in the enlarged detail of the cross section shown in FIG.

Layers 6 and 7 are formed in an LPCVD reactor. This process is based on M. Moslehi and KC Saraswat, IEEE
Trans.Electron Devices, ED. 32, p 106 (1985).
al nitridation) to form a thin tunnel junction. Here, the nitride barrier thickness is self-limited to about 2-3 nm depending on the growth temperature, and the tunnel barrier height is 2 eV
Of the order.

The layer structure 3 is repeatedly formed as follows. First, 770 ° C. SiH _{4 in} an LPCVD reaction chamber was used.
A silicon layer is grown in the gas to obtain the appropriate thickness of silicon for the relevant layer as shown in FIG. 7 (a). Thereafter, the surface of the grown silicon is directly converted to silicon nitride at 930 ° C. for 20 minutes in a 1 Torr 100% NH ₃ gaseous atmosphere in a reaction chamber. Next, another silicon layer is grown on the silicon nitride in the same chamber, and the above steps are repeated. Thus, pure silicon nitride without any silicon oxide is formed on the sequentially grown layer 7.

Next, a polysilicon layer 5 is grown to a thickness of 10 nm by LPCVD. Next, a silicon dioxide layer having a thickness on the order of 10 nm is grown on the layer 5. At a dose of 5 × 10 ¹⁵ cm ⁻² to this oxide layer,
In addition, arsenic ions are implanted at an energy of 25 KeV (not shown). Thus, the silicon layer 5 is converted into a heavily doped n-type layer. Next, at 800 ° C for 1 minute,
Thermal annealing is performed to activate arsenic ions to form layer 5
Has a large n-doped electrical characteristic. This layer 5
Will be used later as a source for the device. Next, a 100 nm thick silicon oxide layer 3 is formed on the layer 5.
Grow 0.

Referring to FIG. 7B, the silicon oxide layer 30 is then formed in a manner known per se using optical lithography and dry etching in an atmosphere of CHF ₃ and argon gas. Be patterned. Then
Using the photoresist and the pattern layer 30 as a mask, the layers 5 and 3 are patterned in a CF ₄ gas by a conventional dry etching method.

Next, in another patterning step, the layer 2 is etched using conventional optical lithography and dry etching in an atmosphere of CF ₄ gas to form a pattern as shown in FIG. To form In this way, the layer structure 3 is etched in the form of pillars 20 having a top surface 21 and side walls 22 upstanding from the drain region 2.

Next, as shown in FIG. 8A, silicon dioxide layers 24 and 26 are grown by thermal oxidation to cover the etched portions of the n ⁺ polysilicon layers 5 and 2 and the pillar structure 3. The thickness of the oxide layer 24 around the pillar structure is on the order of 10 nm, and the layer 26 covering the source region 5 and the drain region 2 is on the order of 50 nm. The thickness of the silicon dioxide on the heavily doped regions 5, 2 is greater than the thickness of the silicon dioxide on the intrinsic silicon of the pillar 3 by SELOCS.

As shown in FIG. 8B, a polysilicon layer 23 is grown to a thickness of 100 nm by LPCVD. Next, a thin silicon dioxide layer (not shown) having a thickness on the order of 10 nm is grown on the surface of this layer 23. Next, arsenic ions are implanted into the oxide layer with an irradiation dose of 5 × 10 ¹⁵ cm ⁻² and an energy of 25 KeV to convert the polysilicon layer 23 into a heavily doped n-type layer.

Next, thermal annealing is performed at 800 ° C. for 1 minute to activate arsenic ions, so that the layer 23 has a large n-doped electrical characteristic. This layer 23 will later be used as the gate of the device. Next, the layer 23 is patterned using optical lithography and a dry etching method in a CF ₄ gas atmosphere. Then, a 500 nm thick BPSG (boron and phosphoro
A protective layer 27 made of us contained silica deglass) and HGS (spin on glass) having a thickness of 250 nm is formed.

Next, as shown in FIG. 8C, CH ₂ F ₂
The BPSG and HSG layers 27 are etched by a dry etching method in an atmosphere of argon gas and an atmosphere of argon gas to expose the top of the polysilicon layer 23.

As shown in FIG. 9A, the polysilicon layer 2 is formed by dry etching in an atmosphere of WF ₆ gas.
3 is etched to a level intermediate the top and bottom surfaces of n ⁺ polysilicon layer 5. Next, a silicon dioxide layer 31 is grown to a thickness of 1000 nm.

As shown in FIG. 9B, the CMP (chemica
l mechanical polish)
1 is polished to expose the top of the polysilicon layer 5,
Provide access to source parts.

Next, as shown in FIG.
The contact windows 32D are etched in 6, 27 to allow external electrical connection to the drain layer 3. at the same time,
The contact window 32G is opened with respect to the gate 23. These contact windows can be clearly seen in the plan view of the device shown in FIG.

Next, a metal layer 28 is formed by sputtering to make electrical connection to the source, drain and gate of the regions 28S, 28D and 28G.
Layer 28 consists of an initial layer of 100 nm thick titanium produced by conventional sputtering techniques and a 1000 nm thick layer of aluminum / silicon (1%) overlying it.

As shown in FIG. 9C, the individual portions 28
In order to provide D, 28S and 28G, the metal layer 28 is etched to form electrically insulating spaces.

Thus, portion 28S provides a connection to source region 5. Portion 28G includes a pillar structure 20 through window 32G to provide a multi-channel device.
Provides a connection to the layer 23 surrounding the. Layer 23 is insulated from pillar structure 20 by a thin oxide layer 24,
It functions as a side gate extending along the 0 side wall 22.

During and after growth of layers 6 and 7 of multilayer structure 3, the entire wafer is heated to 900-1000 ° C. for several hours. However, to ensure that the resulting device operates satisfactorily, the heavily doped source region 5
And should not from the drain region 2 move the dopant in the silicon layer 6 ₂ of the layer structure 3. In this embodiment, the uppermost and lowermost layers 7 of silicon nitride in the layer structure 3 are layers 2 and
It functions as a barrier to n ⁺ dopants in 5 and prevents them from diffusing into the central region of the multilayer structure 3 during the heat treatment.

FIG. 6A shows the active area of the transistor as X × Y. Typically X = Y = 150n
m. The pillar dimensions for X = Y <20 nm are HI Li
e, DK Biegelsen, FA Ponse, NM Johnson and RFW Pease, Appl. Phys. Lett. vol. 64, p 138
3, 1994, and H. Fukuda, JL Hoyt, MA McCord
And RFW Pease, Appl. Phys. Lett. Vol 70, p
333, 1997. In this process, large compressive stresses on the oxide skin near the silicon core / oxide interface, which can reach as much as 10 Gpa, result in oxidation rate retardation, which is a self-limiting effect. effect).

The space occupied by the transistor structure on the substrate is small, the configuration of the side gate 23 minimizes the high electric field region, and our EP97305399.4.
It will be appreciated that this minimizes spatial conflicts on the substrate that occur in the described embodiments.

It will be understood that a memory cell having a side gate structure can be formed by using the principle of the structure described with reference to FIGS. That is, the above-described memory node 10 can be obtained by replacing the drain region 2 shown in FIG. 6 with, for example, a 30-nm polysilicon layer. Further, the conventional source and drain regions can be formed on the wafer 25 by a method known per se, whereby the regions 17 and 17 shown in FIG. 3 and FIG.
A source region and a drain region corresponding to 18 are provided with a conductive source / drain path interposed therebetween.

Next, various modifications of the pillar structure 20 will be described. These provide different operating characteristics for transistors and memories manufactured according to the present invention.

FIG. 8 shows an example of a pillar structure that can be used to provide a normally-off transistor and a nonvolatile memory. This structure can be considered as a modified example of the configuration shown in FIGS. 4A and 4B, and the same reference numerals are used in FIG. In this pillar structure, a side gate 23 and an insulating region 24 are provided.

The pillar structure 20 has a relatively thick insulating layer 7 ', typically silicon dioxide or silicon nitride. This insulating layer is 3 to 30 n in silicon dioxide.
m is the thickness of the order of, 300 in NH ₃ atmosphere
The thickness of silicon nitride formed by plasma nitridation at a high frequency (RF) power of 500 W is 4 to 30 nm. An insulating layer is interposed between the intrinsic silicon layers 6 'having a thickness of 50 nm. FIG. 11 shows the energy band profile of this pillar structure. This energy band profile has a relatively wide barrier 8 'of height B', whose width dimension corresponds to the thickness of the layer 7 '.

In use, when configured as a memory, the device is a fast non-volatile random access memory (R
AM). This is because there is no need to apply an external gate voltage to the gate 23, and the energy barrier 8 'generated by the insulating layer 7' retains the electrons stored in the memory node 10. The height B 'of this energy barrier is of the order of 2.0 eV for silicon nitride and of the order of 3.0 eV for silicon dioxide.

When a bias voltage is applied to the gate 23, the energy barrier B 'is lowered as shown by a broken line in FIG. By lowering the barrier by using this effect, it is possible to write electric charge to the memory node 10. Further, a voltage is applied to the control electrode 11 to obtain a potential gradient as shown in FIG. 2B (not shown in FIG. 11).

As a result, charge carriers move toward node 10. In the case of the silicon nitride barrier 7 ', the voltage applied to the side gate 23 is on the order of 3V and the voltage applied to the control electrode is on the order of 1V. In this configuration, charge carriers pass through the insulating layer 7 'along the path from the control electrode 11 and
To reach. Thereafter, when the voltage is removed from the electrodes 11 and 23, the charge is held at the gate voltage by the barrier B ',
The retention time can be on the order of 10 years. Therefore, this device operates as a high-speed nonvolatile RAM.

When the pillar structure of FIG. 11 is used in a transistor configuration having a source 5 and a drain 2, this device operates as a normally-off transistor.

The uppermost electrodes 5 and 11 and the lowermost regions 2
FIG. 12 shows a modification in which a relatively thin insulating layer 7 ″ is added in the vicinity of 10, which adds a barrier 8 ″ to the corresponding energy band diagram as shown in FIG. When used as a memory, the layer 7 "prevents a large amount of electrons from being redistributed near the insulating layer 7", the control electrode 11 and the memory node 10, and thereby the node 10 ". The potential gradient in the downward direction when a voltage is applied to the gate 23 and the control electrode 11 so as to write or erase electric charges is improved. The energy band diagram of FIG. 13 shows a case where a write voltage is applied to the control electrode 11 and the gate 23 (their values are described above with reference to FIG. 10). The effect of applying a voltage to the control electrode 11 is that the band diagram is tilted downward from the control electrode 11 to the memory node 10 so that electrons can tunnel the barrier B and descend this tilt toward the memory node. It is. The effect of the gate voltage 23 is to lower the height of the barrier B.

The effect of the barrier B 'is as shown in FIG. This barrier is reduced from the level outlined by the dashed outline as a result of the voltage applied to the gate 23. If the pillar structure 20 is formed of the silicon nitride layer 6 and the polysilicon layer 7 as described above, the additional thin layer 7 "is typically 1-2 nm thick and the thickness of the polysilicon layer 6 ' The thickness is on the order of 5 to 30 nm.

FIG. 14 shows a static random access memory (SRAM) or a dynamic random access memory (DRA) that does not require a conventional refresh circuit.
8 shows another modification for producing M). The general-purpose side gate pillar structure is the same as that shown in FIG.
A thin p-type silicon layer 33 is added. This layer is typically 1-2 nm thick and can be formed in a conventional manner in an LPCVD reactor during the formation of layers 6 and 7. The dopant used in layer 33 is boron with a dopant concentration of 10 ¹⁸ cm ^-3 . As a result, a built-in potential barrier on the order of 1.2 V is generated, and as a result, charges can be stored in the memory node 10 for a time on the order of several minutes without applying a bias to the gate electrode 23. Therefore, this memory device does not require the conventional heavy load refresh circuit normally required for a high-speed DRAM. If information needs to be held for a longer time, a negative bias voltage is applied to the gate electrode 23. -1.0V or -0.5V
Can be maintained for 10 years and 1 hour, respectively. To read and write information,
Gate voltages of 0.0 V and 1.0 V are applied to the gate electrode 23. To read information from a node, use source 1
It will be appreciated from the foregoing that applying source-drain voltages to 7 and drain 19 (not shown in FIG. 14) and detecting the resulting source-drain current. This current level depends on the level of the charge stored in memory node 10.

FIG. 16 shows the band gap discontinuity (dis
Another configuration is shown in which some regions 6 are formed of a material having a larger energy band gap to obtain continuity. In the embodiment shown in FIG. 16, thinner layers 6 ₂ 'are metals - are formed in a wide bandgap material, such as semiconductor compounds (e.g. SiC), region 61 is formed of a polysilicon in the manner described above. In forming a layer 6 ₂ 'are used to produce pillars LPCV
It will be appreciated that a suitable dopant can be introduced during the D treatment. The resulting band energy profile is as shown in FIG. It will be appreciated that the band edge has been lifted in the region of layer 6 ₂ ′, which results in a band edge discontinuity ΔEv. In this example, the band edge discontinuity is formed in the valence band, but it is understood that if a suitable material is used and electrons are used as carriers, the discontinuity can also be formed in the conduction band. Like. In this example, the valence band discontinuity is 0.5 eV
It is an order. This is effective for retaining information on the order of one hour without applying a bias to the gate electrode 23. Therefore, the present memory device
There is no need for a high-speed refresh circuit like a conventional DRAM. To retain information for a longer time, a positive bias of 0.5 V can be applied to the gate electrode 23. This achieves a retention time on the order of 10 years. To read and write information, bias voltages of -0.5 V and -1.5 V are applied to the gate electrode 23. Reading and writing at this time are executed by the above-described method.

When used as a transistor, FIG.
Pillar structures usually result in off transistors.

FIG. 18 shows another example of the side gate pillar structure 3. In this structure, a barrier structure is obtained by a group of granular semiconductors or conductive islands 34 formed in the insulating matrix 35. In this example, the matrix 35 is 50n
It is sandwiched between layers of polysilicon material 6 having a thickness of m. Island 3
4 can be composed of metal dots of silicon, germanium, amorphous silicon or gold or aluminum. Various different methods for providing islands on the nanometer scale are described below.

1. Method of Separating Nanometer-Scale Ge Crystallites from Si-Ge-O Mixed Film The Si-Ge-O mixed film is separated by radio frequency magnetron sputtering (RFMS) or ion beam sputtering (IBS). Provided. The sputtering target consisted of a 99.99% pure SiO ₂ glass plate with a diameter of 100 mm, on which several 5 mm square high purity G
e chip was placed. The material sputtered from the target was deposited on a Si substrate with a thickness of 200 nm. The number of Ge chips dispersed on a circular SiO ₂ glass plate was selected to control the amount of Ge sputtered on the target.

In the case of RFMS, 1.25 kW, 13.56 in an argon gas atmosphere at a pressure of 3 mTorr.
Sputtering was performed with a high frequency power of MHz. IB
In the case of S, sputtering was performed in an argon gas atmosphere at a pressure of 0.3 mTorr with a DC power supply of 1 kW.

More specifically, this step was first performed in a growth chamber in which air was discharged to a pressure of 3 × 10 ⁻⁷ Torr by a cryopump. Next, argon gas is introduced,
The power for the above-described sputtering was applied. After 7 minutes, a SiO ₂ glass was formed on the target supersaturated with Ge. The sample was then annealed at 300-800 ° C. for 30 minutes to 4 hours in argon gas. As a result, nanometer-scale crystallites of Ge were separated in the glass. The number of Ge chips, annealing temperature and annealing time were chosen to control the density and size of Ge nanocrystallites formed in the class. The table below is some examples.

Table 1 Sample No. Annealing temperature Annealing time Average diameter 1 300 ° C. 30 minutes 4.2 nm 2 600 ° C. 30 minutes 6.0 nm 3 800 ° C. 30 minutes 6.5 nm 2, hydrogenated by plasma CVD method Preparation of Amorphous Silicon This method used capacitively coupled high frequency plasma chemical vapor deposition (CVD) to prepare extremely thin, hydrogenated amorphous silicon. The growth chamber was first evacuated to a pressure of 10 ^-7 Torr before the introduction of the reaction gas.
The silicon substrate placed on the ground electrode in the reaction chamber
Heated to a temperature of 0 ° C. A mixed gas of SiH ₄ and H ₂ was introduced into the growth chamber by a mass flow controller. The gas flow rates were 10 and 40, respectively.
sccm. 0.2 Ton with automatic pressure controller
A pressure of rr was maintained. By introducing PH ₃ or P ₂ H ₆ during growth, substitutional doping (substitutional doping) is achieved.
doping) to obtain n-type and p-type hydrogenated amorphous silicon, respectively. In this example, 5 sccm or 0.2% PH ₃ diluted in H ₂ was added as an n-type dopant. Forward power (forward
13.56 MHZ for electrodes in the growth chamber by automatic matching to maximize power) and minimize reflections
A high frequency power of z was applied at a level of 10 W, thereby establishing a plasma in the room. The growth rate in this case was 0.08 nm / sec. This growth was performed for 50 seconds to obtain a 4 nm thick layer containing hydrogenated amorphous silicon.

3. Preparation of Microcrystalline Silicon by Plasma CVD Method In order to provide microcrystalline silicon, capacitively coupled high-frequency plasma CVD was used. The main reaction chamber was isolated and connected to a load lock chamber by a shutter that could be easily opened. The sample was loaded and unloaded into the main reaction chamber through the load lock chamber. The pressure in the room was determined by an automatic pressure controller. Before the introduction of the reaction gas, the growth chamber was evacuated with a turbo-molecular pump until the pressure reached 10 ^-7 Torr. The substrate receiving the growth layer is 250 ° C
Was placed on a ground electrode having a diameter of 15 cm heated to a temperature of. The distance between the electrodes was fixed at 3 cm. A mixed gas of SiH ₄ and H ₂ was introduced into the growth chamber by a mass flow controller. The gas flow rates for SiH ₄ and H ₂ were chosen to be 1 and 100 sccm, respectively. During this process, the gas pressure was maintained at 0.15 Torr by an automatic pressure controller. In the same plasma, substitution doping with phosphine or diborane gas was performed during the growth process to produce n-type and p-type amorphous silicon, respectively. In this example, 2sc diluted in hydrogen
Cm or 0.2% phosphine was added as an n-type dopant. The forward power was maximized and the reflected power was minimized by applying 80 W power at 13.56 MHz to the electrodes in the room by AMC.
The growth rate was 0.05 nm / sec. This growth treatment was performed for 80 seconds to obtain a 4 nm-thick microcrystalline silicon layer.

4. Stacked structure of silicon nitride and amorphous or microcrystalline silicon by plasma CVD
g structure) The laminated structure of silicon nitride or microcrystalline silicon
Interspersed silicon nitride layers, which can be realized using the second or third method described above for producing amorphous or microcrystalline silicon
Can be prepared in a similar manner by using a mixed gas of SiH ₄ , NH ₃ , and H ₂ . To prevent contamination between the silicon layer and the silicon nitride layer, individual films are prepared in separate growth chambers joined by a vacuum transfer mechanism.

5. Preparation of Silicon Film by Other Methods Examples of other methods that can be used to prepare amorphous and microcrystalline silicon films are as follows. That is, there are thermal chemical decomposition, photo-chemical vapor decomposition, sputtering, ion beam growth, cluster ion beam growth, and molecular beam growth. These methods can be combined with thermal annealing, rapid thermal annealing and laser annealing to obtain a wide range of microcrystalline silicon structures.

In one specific example, silicon particles are formed with insulating particle boundaries and have a diameter of 3 to 10 nm.
, Preferably 5 nm or less. In the result structure schematically shown in FIG. 18, a current threshold of about 0.5 V is formed. As a result, information can be stored in the memory node 10 for several minutes without applying a bias to the gate electrode 23. To retain information for a longer time, by applying a bias voltage of -1.0 V to -0.5 V to the gate electrode 23,
Retention times of 10 years and 1 hour respectively can be achieved.
To read and write stored information, 0V and 1V respectively
Is applied to the gate electrode 23.

When used as a transistor, FIG.
The eight pillar structure 20 results in a normally off transistor device.

It will be understood that the grain size of the intrinsic polysilicon layer 6 in the above structure can be formed as small as about 3 to 10 nm. During the thermal nitridation process, the grain boundaries are also converted to silicon nitride so that the grains are also surrounded by a 2-3 nm thick insulation. Further, the structure of the combined conductive and insulating layer in FIG. 18 can be used together with any of the pillar structures described above. Small particle size
The energy barrier effect is improved by the charge energy and the quantum size effect, and the electron localization is promoted. This is because the resistance of each tunnel junction can be increased as the junction area decreases. Also,
Leakage current due to the generation of electron-hole pairs can be reduced because the generated electron-hole pairs recombine inside the grain region. This is because separation outside the particles is energetically unfavorable because the charged energy increases.

In FIG. 18, the device is a node 10
And a layer 6. However, node 10 and layer 6 can be eliminated. This is because the particles 34 can be used as nodes. Referring now to FIG. 19, this shows a modification of the side gate structure. This can be considered as a modification of the structure shown in FIG. In this device, a junction gate is formed by replacing the insulating oxide layer 22 of FIG. In the example shown in FIG. 20, the region 36 is made of p-type silicon. As described above with reference to FIG.
Conductive polysilicon layer 6 and insulating silicon nitride layer 7
And The side gate 23 is formed of polysilicon as described above.

The effect of the p-type region 36 is to generate a built-in potential b of 1.0 V in the energy band profile as shown in FIG. As a result, the current threshold voltage of this device is -0.1V
It is an order. Therefore, when used as a memory device, the frequency of the refresh operation can be reduced as compared with the conventional DRAM, so that a low-voltage operation can be realized. -1.6 V and-with respect to the gate electrode 23
When a negative bias voltage of 1.1 V is applied, 1
Retention times for nodes 10 are obtained on the order of 0 years and 1 hour. To read / write information from / to node 10, -0.8 V and 0.4 V are applied to gate electrode 23, respectively.
A gate bias voltage of V is applied.

When used as a transistor, FIG.
The nine pillar structure 20 results in a normally off transistor device.

FIG. 21 shows a pillar structure having an associated Schottky side gate structure. This can be considered as a modification of the structure of FIG. In the embodiment of FIG. 21, the insulating layer 22 is omitted, and a metal side gate 37 is directly added to the side wall 22 of the pillar structure 3, thereby forming a Schottky gate.

The side Schottky gate 37 generates a built-in potential b reaching 0.4 V in the pillar structure 20. The resulting current threshold voltage is 0.3 V
It is an order. Therefore, when used as a memory device, low-voltage operation can be realized, and refresh operation can be performed less frequently than a conventional DRAM. When negative bias voltages of -1.8 V and -1.3 V are applied to the gate electrode 37, retention times of 10 years and 1 hour are obtained, respectively. To read / write information from / to the memory node 10, gate bias voltages of −1.0 V and 0.2 V are applied to the gate electrode 37. In a typical example, Schottky metal gate 37 is formed of WSi or aluminum. It will be appreciated that the Schottky gate of the appropriate material can be formed by appropriately modifying the processing steps described in FIGS.

The pillar structure shown in FIG. 22 can be used for a transistor structure. That is, a normally-on transistor is obtained.

It will be appreciated that the junction gate of FIG. 19 and the Schottky gate of FIG. 21 can be used with any of the pillar structures described above (not just the pillar structure of FIG. 4).

Referring to FIG. 23, another method of manufacturing a transistor device according to the present invention will be described below. The starting materials are the same as those used in the method described above in FIGS. That is, referring to FIG. 23A, a silicon wafer 25 is thermally oxidized at 1000 ° C. to form a silicon dioxide layer 1 having a thickness of 600 nm.
This layer 1 functions as an insulating substrate. Next, a layer 2 used to form a drain is formed on the silicon dioxide layer 1. This layer 2 is LPC in the reaction chamber.
It consists of 100 nm thick polysilicon grown by VD. On the surface of this layer 2, a thin silicon dioxide layer (not shown) of the order of 10 nm is grown. Next, by implanting arsenic ions into layer 2, n
⁺ Form a doped conductive layer. This layer can be used as a drain. Arsenic ions have an energy of the order of 25 KeV for the oxide layer and 3 × 10
^{Driving is performed at} a dose of ¹⁵ cm ^-2 . Next, this oxide layer
It is removed by wet etching using a 20: 1 BHF solution. Thereafter, a multilayer structure 3 providing a multilayer tunnel junction is formed by growing a stacked body of the silicon layer 6 and the silicon nitride layer 7. First, a silicon layer 61 to a relatively large thickness W1 = 50 nm, then, to form a W2 = 5 nm layer 6 ₂ thickness on the order of for most of the laminate. At least one further layer 61 of thickness W1 is formed on the top of the laminate. In this example, further, a silicon layer 6 ₃ of a thickness of 30 nm.

The layers 6 and 7 are formed in an LPCVD reaction chamber. This includes thermal nitridation of silicon as described in Moslehi and Saraswat above.

As described above with reference to FIGS. 7 to 9, the layer structure is as follows.
It is assembled sequentially as follows. First, LPCVD
Growing the silicon layer in SiH ₄ gas at 770 ° C. in the reaction chamber results in silicon of appropriate thickness for the relevant layers shown in the inset to FIG.
Then, the surface of the grown silicon is directly placed in a 1 Torr 100% NH ₃ gaseous atmosphere in a reaction chamber.
Minutes at 930 ° C. to silicon nitride. Next, another silicon layer is grown on the silicon nitride in the same chamber. As a result, pure silicon nitride containing no silicon dioxide is formed between the sequentially grown silicon layers.

In FIG. 23B, on the layer structure 3,
A 10 nm thick silicon dioxide layer 38 is formed by thermal oxidation, and a 160 nm thick silicon nitride layer 39 is deposited at 740 °.
Grow at a temperature of C.

Next, in FIG. 23C, the layers 38 and 39 are patterned using optical lithography and dry etching in an atmosphere of CHF ₃ and argon gas in a manner known per se. . The resulting structure has a lateral width dimension AA and a dimension Y shown in FIG.

Next, as shown in FIG. 23D, the multilayer structure 3 is dry-etched using the patterned layers 38 and 39 as a mask to obtain a dimension A.
Most of the layers 6, 7 outside of A are removed, leaving about 30 nm thickness of structure 3 outside the mask pattern. Next, the remaining portion of the region 3 is converted into silicon dioxide by thermal oxidation to form a region 40, which is insulated from an adjacent transistor (not shown) formed on the same substrate 1 by the method of the present invention. I do. This electrically insulating region 40 is shown in FIG.
Shown in

In FIG. 24 (a), next, at 160 ° C.
The silicon nitride layer 38 and the silicon dioxide layer 39 are removed by using orthophosphoric acid and a 20: 1 BHF solution. Next, a polysilicon layer 5 having a thickness of 100 nm is grown by LPCVD. On the surface of this layer 5, 10
Grow a thin silicon dioxide layer (not shown) on the order of nm. 5 × 10 ¹⁵ c
By implanting arsenic ions with an irradiation dose of m ⁻² and an energy of 25 KeV, the silicon layer 5 is converted into a heavily doped n-type layer for use as a source of a transistor. Next, thermal annealing at 800 ° C. for 1 minute activates arsenic ions and obtains electrical properties that are heavily doped in layer 5. Next, on layer 5
A 00 nm thick silicon dioxide layer 41 is grown.

Referring to FIG. 24B, the silicon dioxide layer 41 is patterned by using electron beam lithography and dry etching to form a narrow region having a width X. This region is used to define a mask that defines the source of the transistor.

In FIG. 24C, the polysilicon layer 5 and the multilayer structure 3 are CF-exposed except for the part of the layer 41 which has been etched, except for the thickness of the layer structure 3 of about 30 nm.
Etching in ₄ gas.

As shown in FIG. 24D, the silicon dioxide layer regions 24 and 26 having a thickness of about 10 nm and 50 nm, respectively, are oxidized by thermal oxidation, whereby the etched portion of the multilayer structure 3 and the n-type To cover the exposed portions of the source and drain regions 5 and 2. The thickness of the silicon dioxide 26 over the heavily doped regions 5, 2 is SE
Due to the LOCS process, the thickness of the oxide 24 on the intrinsic silicon of the layer structure 3 is larger.

As shown in FIG. 24E, a 10 nm-thick polysilicon layer 23 'is grown by LPCVD. On the surface of this layer 23 ', a thin silicon dioxide layer (not shown) of the order of 10 nm is grown.
By implanting arsenic ions into this oxide layer at a dose of 5 × 10 ¹⁵ cm ⁻² and an energy of 25 KeV, the polysilicon layer 23 ′ is converted into a heavily doped n-type layer. Next, by performing thermal annealing at 800 ° C. for 1 minute, arsenic ions are activated and the layer 2 is heated.
Highly doped n-type electrical characteristics are obtained in 3 '. This layer 23 '
Will be used later to form the gate of the device. Next, this layer 23 'is patterned using optical lithography and a dry etching method in a CF ₄ gas atmosphere. Next, as shown in FIG. 25A, a silicon dioxide layer 42 having a thickness of 1000 nm is grown on the device, and a contact window 32D is formed in the oxide layers 42 and 26 by etching. Enables electrical connection. The contact window 32D is formed by optical lithography and wet etching using a 20: 1 BHF solution. As part of this process,
A contact window 32G is formed for the gate 23 '.

As shown in FIG. 25B, a metal layer 28 is formed by sputtering, and electrical connection to the gate and drain is made. This layer 28 comprises an initial layer of 100 nm thick titanium and a 1000 nm layer of aluminum / silicon (1%) produced by conventional sputtering techniques. As shown in FIG. 25B, the first and second contact portions 28D and 28G are provided by etching the electrically insulating space 43 in the layer 28.
These provide connections to the gate and drain regions via contact windows 32D and 32G, respectively.

FIG. 26 shows a schematic plan view of the completed device. 26, the contact windows 32D and 32G are shown.
The process step described with reference to FIG. 25A can also be used to form the contact window 32S in the silicon dioxide coating layer 41, and thereby, the external electric current to the heavily doped n-type region 5 constituting the source can be used. Connection can be made. Further, when forming the insulating gap 43, the insulating gap 44 shown in FIG. 4 is also formed to define the portion 28S of the sputtered metal contact layer 28. As a result, electrical connection to the source 5 can be made via the contact window 32S.

During and after the growth of the layers 6 and 7 of the multilayer structure 3, the whole wafer is heated to 900 to 100 ° C. for several hours. However, in order to ensure that the device of the finished works successfully, must move the dopant in the silicon layer 6 ₂ of the layer structure 3 from a large doped source and drain regions 5 and 2. In this embodiment,
The top and bottom layers 7 of silicon nitride are the n ⁺
Acts as a barrier to dopants, during heat treatment,
They are prevented from diffusing into the central region of the multilayer structure 3. FIG. 4 shows the active area of the transistor as X × Y. Typically, X = 50 nm and Y = 200 nm.

Referring again to FIG. 25B, it can be seen that the etched multilayer structure 3 forms a pillar 20 standing upright from the drain region 2. The region 23 'functions as a side gate extending along the side wall 21 of the pillar 20. When a gate voltage is applied to the contact region 28G, a control electric field is applied from the side gate to the side wall 22G.
To the layer structure 3, whereby the tunnel barrier structure is controlled in the manner described above. This control electric field is applied substantially only via the side walls 22 and no significant electric field is applied from the top surface 21 of the pillar structure.
The region 23 'straddles the pillar, but this region is separated from the pillar top surface 21 by the thickness of the source region 5 and the insulating layer 41 covering the source region 5, so that a significant electric field cannot be applied from the top surface. Not done. This described structure has the following advantages. That is, since the gate electric field is applied from the sidewall, the high electric field region between the gate and the drain is substantially reduced, thereby improving the source-drain characteristics of the transistor.

The device described with reference to FIGS. 24, 25, and 26 uses another multilayer structure 3 to form a pillar structure 20 by the method described above with reference to FIGS. You may.

Further, it will be understood that the side gate structure described with reference to FIGS. 24 and 25 can be used not only for a transistor but also for a memory device. In a memory device, the drain region 2 is replaced by a polysilicon or similar conductive memory node 10, and source and drain regions corresponding to the regions 17, 18 described above are formed in the device substrate.

In the structure described above, it can be designed that electrons mainly conduct in the surface area of the pillar. In this configuration, the operation is similar to a MOS transistor, and is less affected by the lateral dimensions of the pillar. It is also possible to design the electrons to conduct in both the surface area and the central area of the pillar (in particular,
On pillars with small lateral dimensions).

The above-described structures can be arranged in the horizontal direction as shown in FIG. 27 which is a plan view and FIG. 28 which is a cross-sectional view taken along the line III-III 'of FIG. Gate electrode 1
1G induces an electric field in the multi-tunnel junction, thereby controlling electron transfer between the source and the drain. This gate does not overlap with the source and drain contact regions. In this structure, the gate region can be designed by lateral patterning,
The manufacturing process can be simplified.

The method of manufacturing this device is described below with reference to FIG.
This will be described in detail with reference to FIG. The starting material consists of a silicon wafer 25, which is thermally oxidized at 1000 ° C. to form a 600 nm thick SiO ₂ layer 1.
This functions as an insulating substrate. Next, a layer 2 used for generating a drain is formed on the SiO ₂ layer 1. This layer 2 is made of 100 nm thick polysilicon grown by LPCVD. 10 nm on the surface of this layer
A thin silicon dioxide layer of the order of thickness is grown.
Next, by implanting arsenic ions into layer 2,
An n ⁺ doped conductive layer is formed. This layer can be used as a drain. Arsenic ions are implanted into the oxide layer (not shown) with an energy on the order of 25 KeV and a dose of 3 × 10 ¹⁵ cm ⁻² . 10n
The oxide of m and the silicon layer 2 are patterned by optical lithography and dry etching. Then, a silicon oxide layer 51 having a thickness of 60 nm is grown, and a contact window 55 is formed by etching the oxide layer 51 and the 10 nm oxide, thereby enabling an electrical connection to the drain layer 2. The contact window 55 is formed by optical lithography and wet etching using a 20: 1 BHF solution.

Thereafter, a multilayer structure 3 providing a multi-tunnel junction is formed by growing a laminate of a silicon layer and a silicon nitride layer in the same manner as described above. This multilayer structure 3 is patterned by optical lithography and dry etching.

Next, a 60 nm-thick silicon oxide layer 52 is grown, and a contact window 56 is formed in the oxide layer 52 by etching to enable electrical connection.
The contact window 56 is made by optical lithography and 20: 1B
It is formed by wet etching using an HF solution.

Next, a layer 5 used for providing a source is formed. This layer 5 is a layer 1 grown by LPCVD.
It is made of 00 nm thick polysilicon. On the surface of layer 5,
Grow a thin silicon dioxide layer on the order of 10 nm thick. Next, an n ⁺ -doped conductive layer is formed by implanting arsenic ions into layer 5. This layer can be used as a source. Arsenic ions are implanted into the oxide layer (not shown) with an energy on the order of 25 KeV and a dose of 3 × 10 ¹⁵ cm ⁻² . Next, the 10 nm oxide and silicon layer 5 is patterned by optical lithography and dry etching.

A silicon oxide layer 53 having a thickness of 60 nm is grown, and a gate window 54 is formed in the oxide layers 53 and 52 by etching. This gate window 54 is formed by optical lithography,
It is formed by wet etching using a 20: 1 BHF solution. Then, a 10 nm silicon dioxide layer 54
Is formed by thermal oxidation.

Next, an electrical connection to the drain layer 2 is enabled by etching the contact window 32D in the oxide layers 51, 52, 53. The contact window 32D is formed by optical lithography and wet etching using a 20: 1 BHF solution. At the same time, a contact window 32S is formed for the source 5.

Next, metallization and patterning are performed in the same manner as described with reference to FIG.
7. The structure shown in FIG. 28 is completed.

The device described with reference to FIGS. 27 and 28 may utilize another multilayer structure 3, for example, as described above with reference to FIGS. Further, a memory device may be provided instead of a transistor by replacing the drain 2 with a memory node.

Many other variants within the scope of the present invention
Changes will be apparent to those skilled in the art. For example, in the above embodiment, silicon nitride is used to provide the insulating layer of the multilayer structure 3, but it is also possible to use a film of silicon oxide or another insulating material. Further, the n-type region and the p-type region can be exchanged with each other, and the type of the dopant used can be changed. For example, with a p-type gate,
It is possible to use n-type sources and drains (or memory nodes).

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a conventional transistor structure.

2 (a) and 2 (b) show different bias conditions.
FIG. 2 is an energy diagram of the transistor illustrated in FIG. 1.

FIG. 3 is a cross-sectional view of a conventional memory device.

4A is a schematic sectional view of a transistor device according to the present invention, and FIG. 4B is a schematic sectional view of a memory device according to the present invention.

FIG. 5 is an energy band diagram of the device shown in FIGS. 4 (a) and 4 (b).

FIG. 6 (a) is a schematic plan view of a transistor device according to the present invention, and FIG. 6 (b) is a schematic cross-sectional view of the transistor device of FIG.

FIGS. 7 (a) and 7 (b) are views showing a manufacturing process for manufacturing the transistor device shown in FIG. 6;

FIGS. 8A to 8C are diagrams showing a manufacturing process following the manufacturing process shown in FIG.

FIGS. 9A to 9C are views showing a manufacturing process following the manufacturing process shown in FIG. 8;

FIG. 10 used in a device according to the invention;
It is a figure which shows the pillar structure which was deformed.

11 is an energy band diagram of the device shown in FIG.

FIG. 12 illustrates another pillar structure for use in a device according to the present invention.

FIG. 13 is an energy band diagram of the device shown in FIG.

FIG. 14 illustrates another pillar structure for use in a device according to the present invention.

15 is an energy band diagram of the device shown in FIG.

FIG. 16 illustrates another embodiment of a pillar for use in a device according to the present invention.

17 is an energy band diagram of the device shown in FIG.

FIG. 18 illustrates another pillar structure for use in a device according to the present invention.

FIG. 19 shows yet another embodiment of a pillar structure incorporating a junction diode side gate for use in a device according to the present invention.

20 is an energy band diagram of the device shown in FIG.

FIG. 21 is an explanatory diagram of a side gate structure using a Schottky gate.

FIG. 22 is an energy band diagram of the device of FIG. 21.

FIG. 23 is a process chart for manufacturing another embodiment of the transistor device according to the present invention.

FIG. 24 is a processing step diagram following FIG. 23;

FIG. 25 is a processing step diagram following FIG. 24;

FIG. 26 is a plan view of the transistor device manufactured according to FIGS. 23 to 25 (FIG. 25 (b) is a line II-
II 'is a sectional view).

FIG. 27 is a plan view of a lateral transistor structure according to the present invention.

FIG. 28 shows a line III-III ′ of the transistor in FIG.
FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Drain region, 3 ... Layer structure, 4 ... Source region, 5 ... Drain region, 6 ... Polysilicon layer, 7 ... Insulating layer, 8 ... Barrier, 10 ... Memory node, 11 ... Control electrode, 20 ... pillar structure, 23 ... side gate, 21 ... top surface, 22 ... side wall.

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 5, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

The device can be configured as a transistor or a memory device. Therefore, the control element may be a source region and a drain region,
Alternatively, one of them may be a memory node .

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

Memory node 10 has a field effect (fie) for controlling current flow between source 17 and drain 18 implanted in the substrate by conventional doping techniques.
ld effect) acts as a gate. Conduction path 19 extends between source 17 and drain 18, the conductivity of which varies depending on the level of charge stored on memory node 10. Using the multilayer structure 3 to provide a multiple tunnel junction between the control electrode 11 and the memory node 10 significantly reduces leakage current from the node 10. But,
The gate electrode 15 does not effectively raise or lower the potential barrier structure below the control electrode 11, but increases the electric field in the region between the gate region and the memory node 10.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0077

[Correction method] Change

[Correction contents]

More specifically, this step was first performed in a growth chamber in which air was discharged to a pressure of 3 × 10 ⁻⁷ Torr by a cryopump. Next, argon gas is introduced,
The power for the above-described sputtering was applied. After 7 minutes, a SiO ₂ glass was formed on the target supersaturated with Ge. The sample was then annealed at 300-800 ° C. for 30 minutes to 4 hours in argon gas. As a result, nanometer-scale crystallites of Ge were separated in the glass. The number of Ge chips, annealing temperature and annealing time were selected to control the density and size of Ge nanocrystallites formed in the glass . The table below is some examples.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0090

[Correction method] Change

[Correction contents]

The pillar structure shown in FIG . 21 can also be used for a transistor structure. That is, a normally-on transistor is obtained.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0104

[Correction method] Change

[Correction contents]

FIG. 26 shows a schematic plan view of the completed device. 26, the contact windows 32D and 32G are shown.
The process step described with reference to FIG. 25A can also be used to form the contact window 32S in the silicon dioxide coating layer 41, and thereby, the external electric current to the heavily doped n-type region 5 constituting the source can be used. Connection can be made. Further, when forming the insulating gap 43, the insulating gap 44 shown in FIG. 26 is also formed to define the portion 28S of the sputtered metal contact layer 28. As a result, electrical connection to the source 5 can be made via the contact window 32S.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0110

[Correction method] Change

[Correction contents]

The above-described structures can be arranged in the horizontal direction as shown in FIG. 27 which is a plan view and FIG. 28 which is a cross-sectional view taken along the line III-III 'of FIG. Gate electrode 2
8G induces an electric field in the multiple tunnel junction, thereby controlling electron transfer between source and drain. This gate does not overlap with the source and drain contact regions. In this structure, the gate region can be designed by lateral patterning,
The manufacturing process can be simplified.

[Procedure amendment 7]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 25 ────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 6, 1998

[Procedure amendment 7]

[Document name to be amended] Drawing

[Correction target item name] Fig. 25

[Correction method] Change

[Correction contents]

FIG. 25

Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/786 H01L 29/78 622 21/336 29/80 V 29/80 (72) Inventor Hiroshi Mizuta Cambridge CB3, UK 0 H.E., Madingley Road (No address) Cavendish Laboratory, Hitachi Cambridge Laboratory, Hitachi Europe Limited (72) Inventor Juichi Shimada 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. 72) Inventor Hideo Sunami 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Kiyoo Ito 1-1280 Higashi Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Tatsuya Teshima 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Toshiyuki Mine Higashi Koike, Kokubunji City, Tokyo 1-280 Kubo, Central Research Laboratory, Hitachi, Ltd.

Claims (28)

[Claims] An upright pillar structure having sidewalls and a top surface, and a side gate structure along a sidewall of the pillar structure, wherein the upright pillar structure has a region of relatively conductive material and a non-conductive material. In a first state, charge carrier flow can occur through the pillar structure, and in a second state, the areas can be tunnel barriers that block charge carrier flow through the pillar structure. A controllable conductive device, wherein the device has a structure, wherein the side gate structure is configured to control its electrical conductivity by applying an electric field through a sidewall to the pillar structure. 2. An energy band comprising a relatively dimensionally wide barrier component having a relatively low barrier height and at least one relatively narrow barrier component having a relatively high barrier height. The device of claim 1 that results in a profile. 3. The device according to claim 2, wherein the component of the energy band profile with a relatively high barrier height is obtained by an element of 3 nm or less. 4. The device according to claim 2, wherein the energy band profile of the tunnel barrier structure has a plurality of the relatively high barrier height components. 5. The structure comprises alternating layers of relatively conductive and insulating materials, which collectively provide the relatively low barrier height component of the energy band profile; 5. The device of claim 2, 3 or 4, wherein individual insulating layers provide said relatively high barrier component. 6. The device of claim 5, wherein said alternating layers are each polysilicon and silicon nitride or silicon oxide. 7. The device of claim 6, including a heavily doped barrier layer in said alternating layers. 8. The device of claim 5, wherein the conductive layers are each less than 10 nm thick and the insulating layers are on the order of 1 nm. 9. The device of claim 5, wherein said structure comprises alternating layers of conductive and semiconductor materials. 10. The device according to claim 1, wherein said pillar structure has a plurality of conductive islands. 11. The device of claim 10, wherein said islands are dispersed in an insulating matrix. 12. The device according to claim 10, wherein the island has a diameter of 3 to 10 nm. 13. The device according to claim 10, wherein the islands comprise nanocrystals of a semiconductor material. 14. An island according to claim 1, wherein said island is made of metal.
The device according to any one of 0 to 12. 15. The device of any preceding claim, operative as a transistor, comprising a source region and a drain region for providing a source-drain charge carrier flow path through said pillar structure. A device wherein a side gate is operable to control charge carrier flow along said source / drain charge carrier flow path. 16. The memory according to claim 1, wherein said memory is operable as a memory.
Device according to any one of the preceding claims, comprising a memory node for receiving charge carriers passing along a path through the pillar structure, wherein the gate controls the charge stored at the node. Operable to control the flow of charge carriers along said path. 17. The device of claim 16, comprising a source / drain path having a conductivity dependent on the level of charge stored at said node. 18. A device according to any preceding claim, wherein said side gate structure comprises a Schottky gate. 19. The device according to claim 1, wherein said side gate comprises a junction gate. 20. A device according to any preceding claim, wherein the side gate is disposed along the sidewall, but does not cover the top surface. 21. The side gate is constituted by a region arranged along the side wall and forming a bridge that is separated from the top surface and straddles the pillar structure.
20. The device according to any one of the preceding claims, whereby no significant control electrostatic field is applied from the bridge into the pillar structure by the region. 22. A device according to any preceding claim, having a control electrode extending over the entire top surface of the pillar structure. 23. A semiconductor device comprising a region of a relatively conductive material and a region of a non-conductive material, wherein a charge carrier flow can be generated through a pillar structure in a first state, and in a second state, A barrier structure in which the regions exhibit a tunnel barrier structure that blocks charge carrier flow through the pillar structure; a memory node for receiving charge carriers passing along a path through the structure; And a control electrode for supplying to the structure and passing through the structure to accumulate at the node, wherein the region of non-conductive material comprises a plurality of dimensionally relatively narrow barrier components adjacent to the memory node and the control electrode, respectively. And an energy band profile having a dimensionally relatively wide barrier component between the narrow barrier components. Memory devices but that is configured to provide non-volatile charge storage in the node. 24. The device according to claim 23, further comprising a side gate for applying an electrostatic field to the pillar structure through a side wall thereof. 25. A substrate (1), control elements (2, 5) laterally spaced on the substrate, and channels electrically connected to and extending between the control elements. A structure (3) and a gate region (28G), wherein the channel structure is composed of a region of a relatively conductive material and a region of a non-conductive material;
Charge carrier flow can occur through the structure, and in a second state, the regions exhibit a tunnel barrier structure that blocks charge carrier flow, and the gate region controls its electrical conductivity within the channel structure. The channel structure (3) configured to apply an electric field;
A controllable conductive device overlying one of said control elements on said substrate and overlying the other of said control elements. 26. The device according to claim 25, wherein the control element comprises source and drain regions (2, 5). 27. The device of claim 25, wherein one of said control elements comprises a memory node. 28. The device of claim 25, wherein said gate region covers said channel structure and is located between said control elements.