JPH1187510A - Wiring structure, forming method thereof, and semiconductor integrated circuit applying thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen a capacitance between wirings so as to enhance a semiconductor integrated circuit in operation speed by a method wherein the base of a second insulating film formed between adjacent wirings is set lower than those of the adjacent wirings by a certain value which is smaller than a space between the adjacent wirings by a specific % or above. SOLUTION: Necessary structures such as transistors, a field oxide film, and others required for the formation of a semiconductor device are formed on the surface of a semiconductor substrate 10. The surface of an underlying insulating film 12 between first wiring layers 18 is etched as deep as d1 , and an interlayer insulating film of fluorinated silicon oxide of low permittivity is formed. The height of the base of the interlayer insulating film formed between the adjacent wiring layers 18 is lower than those of the wiring layers 18 by the film depth d1 . The depth d1 is as large as 20% of a wiring space S1 or above. By this setup, an electrostatic capacity between wirings can be effectively reduced, and a semiconductor device can be enhanced in operation speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor integrated circuit capable of reducing the capacitance between wirings and increasing the operating speed, a method of forming the wiring structure, and application of the wiring structure. And a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, with the advance of fine processing technology, the number of elements that can be integrated in one semiconductor chip has increased and the operation speed of a semiconductor integrated circuit has also increased. This is mainly due to transistor dimensions, eg MOS
In the case of a transistor, this is because the switching speed of each transistor is improved by reducing the gate length. However, when the design rule of the layout of the semiconductor integrated circuit (usually expressed by the minimum gate length of the transistor) becomes smaller than 0.5 μm, the progress of miniaturization does not necessarily lead to the improvement of the operation speed. It has become. This is mainly due to an increase in delay time when a signal is transmitted through a wiring connecting a plurality of circuit blocks in a semiconductor integrated circuit.

That is, even if the gate length of a transistor is reduced, the height of the wiring is kept substantially constant, so that the capacitance per unit wiring length increases as the wiring interval decreases. . In addition, the wiring length between the circuit blocks does not always become shorter, and conversely, it tends to become longer as the functions integrated in one semiconductor chip increase. Therefore, as the miniaturization progresses, the capacitance and the wiring resistance between the wirings between the circuit blocks increase, and the increase in the capacitance and the wiring resistance increases the signal delay caused by the wiring.
Therefore, in order to improve the operation speed of the semiconductor integrated circuit, it is necessary to reduce the capacitance between wirings and the wiring resistance, especially in a semiconductor integrated circuit whose design rule is miniaturized to 0.5 μm or less. It is.

By the way, conventionally, for insulation between wirings in the same wiring layer and for insulation between upper and lower wiring layers,
A silicon oxide film (silicon oxide) formed by a CVD method has been generally used. 3.9 pure silicon oxide
The silicon oxide film formed by the CVD method generally has a dielectric constant of about 4.0 to 4.4. Further, as the wiring, a wiring mainly composed of an Al (aluminum) film or an Al alloy film (hereinafter, referred to as “Al-based wiring”) was generally used. On the other hand, in order to reduce the capacitance between wirings, use of an insulating material having a lower dielectric constant than a silicon oxide film has been studied. On the other hand, in order to reduce the wiring resistance, a low-resistance wiring mainly composed of gold, silver and copper having a lower resistance than Al has been studied. For example, the use of a wiring mainly composed of a Cu (copper) film or a Cu alloy film (hereinafter referred to as “Cu-based wiring”) is being studied.

In order to form an Al-based wiring, a method of forming a metal film over the entire surface of an insulating layer and then removing unnecessary portions (hereinafter referred to as an "etching method") is usually used.
Is used. On the other hand, in order to form Cu-based wiring, a groove for forming wiring is formed in advance on an insulating layer for insulating between wirings, and then a metal film is formed on the surface of the insulating layer including the inside of the groove. A damascene method for forming metal and removing the metal film outside the trench is being studied (MT Bohr, IEEE Internati
onal Electrons Devices Meeting Digest of Technical
Papers (1995) p. 241, J. Paraszczak et al., IEEE
International Electrons Devices Meeting Digest of
Technical Papers (1993) p. 261).

As materials having a lower dielectric constant than a silicon oxide film, for example, the following materials have been proposed.

1) Fluorinated silicon oxide film A technique has been developed for forming a fluorinated silicon oxide film by adding a fluorine compound gas to a conventional gas system for forming a silicon oxide film and performing CVD. The dielectric constant is about 3.0 to 3.7, and can be reduced as the amount of fluorine added increases. However, since the hygroscopicity increases as the amount of added fluorine increases, there is a defect that the dielectric constant can be reduced to only about 3.3 in practice (H. Miyajima et al., Proceedings).
of Symposium on Dry Process, (1994), p. 133, R. Kat
sumata et al., Proceedings of Symposium on Dry Pro
cess (1995), p. 269).

2) Siloxane SOG Materials having a lower dielectric constant include Si-R (R = H,
There is a siloxane SOG (spin-on-glass) formed by applying and curing a solution containing a siloxane oligomer having a bond of CH ₃ , C ₆ H _{5 and the} like. 2.
It has a dielectric constant of about 8 to 3.3. Specific examples include hydrogenated silsesquioxane (BT Ahlburn et al., Procee
dings of the 1st International Dielectrics for ULS
I Multilevel Interconnection Conference (1995) p.
36), methylsiloxane (K. Numata et al., Materia
ls Research Society Symposium Proceedings, Vol. 38
1 (1995) p. 255).

3) Organic materials Materials having a lower dielectric constant include polyimide such as BPDA-PDA, fluorinated polyimide, polyimide-siloxane, cyclic fluororesin / siloxane copolymer, benzocyclobutene, parylene-F, and poly (fluorine). Organic materials such as fluorinated naphthalene), amorphous Teflon (trademark), fluorinated poly (aryl ether), cycloperfluorocarbon polymer, and fluorinated amorphous carbon. Most of these materials are formed into a film by a coating method, and parylene, fluorinated amorphous carbon, and the like are formed by a CVD method (for example,
CHTing et al., Materials Research Society Proc
eedings, Vol. 381 (1995) p.3, C.-I.Lang et al., M
aterials Research Society Proceedings, Vol. 381 (1
995) p. 45, M. Mills et al., 1st International Die
lectrics for ULSI Multilevel Interconnection Confe
rence (1995) p. 269, S.-P. Jeng et al., Materials
Research Society Symposium Proceedings, Vol. 381
(1995) p. 197, BC Auman, 1st International Diele
ctrics for ULSI Multilevel Interconnection Confere
nce (1995) p. 297, NH Hendricks et al., 1st Inte
rnationalDielectrics for ULSI Multilevel Interconn
Section Conference (1995) p. 283, K. Endo et al., J
apanese Journal of Applied Physics, Vol. 35 (1996)
p.L1348).

4) Porous material It is possible to lower the dielectric constant by making the insulator porous. Ultimately, a dielectric constant of 1 can be obtained by insulating the wirings with a vacuum or an inert gas. For example, an organic porous material obtained by making polyimide porous (KR Carter et al., Materials Resear
ch Society Symposium Proceedings, Vol. 381 (1995)
p. 79) and inorganic porous materials such as gel silica (US Pat. No. 5,488,015). Also,
After forming a multilayer wiring structure filled with carbon between wirings, a structure is also proposed in which carbon is removed by heating in oxygen and the wirings are insulated with gas (MB Anand et a).
l. Symposium on VLSI Technology Digest of Technica
l Papers (1996) p. 82).

Among the above materials 1) to 4), the fluorinated silicon oxide film of 1) has a practically obtainable lower limit of the dielectric constant of about 3.3, and has an effect of reducing the capacitance. Has limitations. Therefore, in order to more effectively reduce the capacitance, materials classified into the above 2), 3) and 4) have been energetically studied. Hereinafter, simply "low dielectric constant material"
Is a new material having a lower dielectric constant than a conventional silicon oxide film, such as those classified into 2), 3) and 4) above.

However, these low dielectric constant materials generally have lower heat resistance than conventional silicon oxide films, and are often deteriorated or decomposed during a heat treatment step in a manufacturing process. However, there is a problem that many of them contain moisture or change into a hygroscopic state due to deterioration in the heat treatment step. Such water content or absorbed water is desorbed in a subsequent heat treatment step, and the water released in this manner causes corrosion of the metal wiring. Further, these low dielectric constant materials have another problem that adhesion to metal is poor.

Further, since the above-mentioned low dielectric constant material has a lower mechanical strength than a silicon oxide film, there is a problem that generation of hillocks (projections) on the surface of the metal wiring cannot be prevented.

In order to form a multilayer wiring structure, it is necessary to form a via hole for connecting between wiring layers. In the case of a conventional silicon oxide film, dry etching is performed using a resist as a mask, and thereafter, a fine connection hole is easily formed by a process of removing the resist by ashing (oxidation using oxygen plasma or active oxygen). Was completed. However, the above-mentioned low-k material generally has poor resistance to oxidation, and is modified by ashing to cause an increase in hygroscopicity and an increase in the dielectric constant. There is also a problem that the conventional via hole forming process cannot be applied as it is.

For this reason, a method of forming a via hole using not a resist but an inorganic material such as a silicon oxide film or a silicon nitride film as a mask is often adopted. Such a mask made of an inorganic material is called a hard mask. In addition, the low dielectric constant materials described above generally have low thermal conductivity,
There is also a problem that Joule heat generated by current flowing in the wiring cannot be efficiently diffused.

Further, even if such a material having a low dielectric constant can be used, it is not always possible to effectively reduce the wiring capacitance. That is, the effective permittivity (the permittivity obtained from the actual capacitance value and the wiring dimension) cannot always be reduced to the permittivity of the material. For example, as shown in FIG. 1, wirings 218a, 218a,
Consider a case where a wiring layer 218 including 218b and 218c is formed. In this case, even if the interlayer insulating layer 220 having a low dielectric constant is formed between the wirings and on the wirings, the electric field between the wirings is not confined only in the interlayer insulating layer. That is, the electric field spreads to the inside of the base insulating layer 212 formed immediately below the wiring layer. Therefore, since the base insulating layer 212 is formed of a normal silicon oxide film, the effective dielectric constant between the wirings does not become lower than the dielectric constant of the material forming the interlayer insulating layer 220. Such a phenomenon is described, for example, in JP-A-8-162528.

In order to solve at least some of the various problems described above, the low dielectric constant material includes a silicon oxide film,
It is often used in combination with materials such as a silicon oxynitride film and a silicon nitride film. For example, a silicon oxide film is deposited as a base film by a CVD method on a wiring layer in order to improve adhesion to a lower wiring layer and prevent hillocks on the surface of the lower wiring layer. A common method is to deposit a film of material (JT Wetzel et a
l., Materials Research Society Symposium proceedin
gs Vol. 381 (1995) P. 217, y. Homma et al., Procee
dings of the 12th International Conference on VLSI
Multilevel Interconnection Conference (1995) p. 45
7). Similarly, there is also a method of forming a cap film on a film of a low dielectric constant material in order to improve the adhesion of the upper wiring layer and prevent corrosion of the upper wiring layer due to moisture contained in the low dielectric constant material. .

However, the silicon oxide film is 4.0-4.4.
The silicon oxynitride film or the silicon nitride film has a higher dielectric constant. Therefore,
When such a base film or a cap film is formed, a material having a high dielectric constant exists between wirings. For this reason, there is a problem that the capacitance between the wirings is further increased as compared with the case shown in FIG.

When such a base film is deposited on a vertical surface by an ordinary method, for example, a plasma CVD method, the surface of the deposited film often has an overhang shape. For example, as shown in FIG. 2, when a base film 216 is deposited by a plasma CVD method on a substrate on which a wiring layer including wirings 218a, 218b, and 218c having vertical side walls is formed, the deposited base film 21 is formed.
The surface of 6 overhangs on the side of the wiring. This overhang makes subsequent processes difficult. For example, when the low dielectric constant film 228 is formed on such a base film, voids 229 are formed between wirings. These voids cause cracks in the interlayer insulating layer 220. Further, since the shape of the void is not constant, the capacitance between the wirings varies.

In order to solve the problem that it is difficult to form a via hole, a low dielectric constant material is used only for insulation between wirings in the same layer, and a normal CVD insulating film is used for insulation between wiring layers. Have been proposed (S.-P. Jeng et
al, Materials Research Society Symposium Proceedin
gs, Vol. 337 (1994) p. 25). However, in this case, since the electric field between the wirings spreads in the CVD insulating film, there arises a problem that the capacitance between the wirings is further increased as compared with the case shown in FIG.

In order to solve the problem that Joule heat cannot be diffused efficiently, a material having a higher thermal conductivity than a silicon oxide film, such as a film of silicon nitride or aluminum oxide, is directly contacted with the wiring. Formed between wiring layers (US Pat. No. 5,468,768).
No. 17). However, materials with such high thermal conductivity
It has a higher dielectric constant than a silicon oxide film. Due to the spread of the electric field into the material having such a high dielectric constant, the capacitance between wirings is increased.

Japanese Patent Application Laid-Open No. 8-162528 mentioned above proposes a structure in which the capacitance between wirings is effectively reduced by making the thickness of the low dielectric constant film between the wirings larger than the height of the wirings. I have. However, in this structure, a base film such as a silicon oxide film, a silicon oxynitride film, or a silicon nitride film is used. Therefore, the above-mentioned problems relating to the underlying film have not been solved. On the other hand, regarding the wiring material,
It is sometimes argued that the l-based wiring will eventually be replaced by Cu-based wiring. However, in reality, there are many problems to be solved in order to manufacture a semiconductor integrated circuit product using Cu-based wiring at low cost. Therefore, it is necessary to propose a practical method suitable for industrial reality for applying Cu-based wiring to various semiconductor integrated circuit products.

[0023]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the capacitance between wirings and to increase the operating speed of a semiconductor integrated circuit in view of the above-mentioned problems of the prior art. An object of the present invention is to provide a structure and a method for forming the wiring structure. Another object of the present invention is to
An object of the present invention is to provide a semiconductor integrated circuit to which the above wiring structure is applied, which can further reduce the wiring resistance and further increase the operation speed of the semiconductor integrated circuit.

[0024]

To achieve the above object, the present invention provides a wiring structure applied to a semiconductor integrated circuit, comprising: a first insulating layer formed on a semiconductor substrate;
A wiring layer formed on the first insulating layer and including at least one adjacent wiring; and a low dielectric constant formed between at least adjacent wirings of the wiring layer and having a lower dielectric constant than a silicon oxide film. A second insulating layer including a refractive index film,
The height of the bottom surface of the second insulating layer formed between the adjacent wires is higher than the height of the bottom surface of the adjacent wires.
It is another object of the present invention to provide a wiring structure characterized by being formed at least 20% lower than the distance between the adjacent wirings.

Here, in the above-mentioned wiring structure, the second
The insulating layer further includes a base film formed between the wiring of the wiring layer and the low dielectric constant film, at least on the upper surface and side surfaces of the adjacent wiring, and the base film is It is preferable that the film thickness at the upper end of the side surface of the wiring is formed smaller than the film thickness at the lower end. Further, in the above wiring structure, the low dielectric constant film is formed also on the adjacent wiring, and the second insulating layer further includes a heat conductive film formed on the low dielectric constant film. It is preferable that the thermal conductive insulating film includes an insulating film and has a higher thermal conductivity than the thermal conductivity of the silicon oxide film.

The present invention also relates to a method for forming a wiring structure applied to a semiconductor integrated circuit, comprising forming a first insulating layer on a semiconductor substrate, and forming at least a first insulating layer on the first insulating layer. A wiring layer including one adjacent wiring is formed, and a region having a thickness of 20% or more of a distance between the adjacent wirings on an upper surface of the first insulating layer formed between the adjacent wirings is removed. Forming a second insulating layer including a low dielectric constant film having a dielectric constant lower than that of a silicon oxide film at least between adjacent wirings of the wiring layer. To provide.

Here, in the above-mentioned method for forming a wiring structure, when forming the second insulating layer, before forming the low-dielectric-constant film, the method further includes forming an upper surface and a side surface of the adjacent wiring. A base film is formed such that a film thickness at an upper end portion of a side surface of the adjacent wiring is smaller than a film thickness at a lower end portion, and thereafter, on the base film and at least the wiring adjacent to the wiring layer adjacent to the wiring layer is formed. It is preferable that the low dielectric constant film is formed between them. In the method for forming a wiring structure, the method may further include forming the second insulating layer so that the low dielectric constant film is formed also on the adjacent wiring, and further forming a silicon oxide film. It is preferable to form a thermally conductive insulating film having a higher thermal conductivity than that of the above.

Further, the present invention has at least two or more wiring layers, and at least one of the lower wiring layers has the wiring structure according to any one of claims 1 to 3. An aluminum-based wiring layer mainly made of aluminum or an aluminum alloy, and at least one of the upper wiring layers is a copper-based wiring layer mainly made of copper or a copper alloy; It is an object of the present invention to provide a semiconductor integrated circuit, wherein at least one of a long-distance signal wiring, a clock wiring, and a power supply bus wiring is formed by using a wiring of a wiring layer.

[0029]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a wiring structure according to the present invention; FIG. Will be described.

(Embodiment 1) FIGS. 3 (a), 3 (b) and 3 (c)
FIGS. 4D and 4E are cross-sectional views of the first embodiment showing the steps of forming the wiring structure of the present invention. FIG. 3 (a)
In FIG. 1, a structure (not shown) required for a semiconductor device, such as a transistor or a field oxide film, is formed on the surface of a semiconductor substrate 10. As shown in FIG.
A silicon oxide film or BPSG (borophospho-silicate glass) deposited on the semiconductor substrate 10 by using the CVD method.
s) The base insulating layer 12 is formed using one or a plurality of insulating films such as films. Silicon oxide film and BP
The SG film has a dielectric constant of about 4.0 to 4.4, and its surface is formed by CMP (chemical mechanical polish).
It is preferable to flatten by a method such as ing).

Subsequently, at a necessary position of the base insulating layer 12,
The transistor formed on the surface of the semiconductor substrate 10 is first
A contact hole (not shown) for connecting to the wiring of the wiring layer is formed. In the contact hole, for example, a tungsten plug is formed, and then the wiring of the first wiring layer is formed on such a substrate surface. Depositing a metal film 14 to be formed (hereinafter simply referred to as “substrate” generally means a semiconductor substrate and a semiconductor substrate having various films and structures formed on its surface) . The metal film 14 is, for example, a Ti film having a thickness of 10 to 50 nm and a Ti film having a thickness of 30 to 150 nm.
N film, 300-1000nm Al-0.5wt% Cu
Film, 5-20 nm Ti film, 20-100 nm TiN
The films are formed by stacking in this order. In addition, Al-0.5w
In addition to the t% Cu film, various Al-containing films such as an Al alloy film and a pure Al film can be used.

Subsequently, as shown in FIG. 3B, a resist pattern 16 is formed by a known photolithography technique.
Is formed, and the metal film 14 is patterned by anisotropic plasma etching using a chlorine-based gas (BCl ₃ , Cl _2, etc.) to form the first wiring layer 18 including the wirings 18a, 18b, 18c. Examples of the etching apparatus include an ECR (electro-cyclotron resonance) plasma etching apparatus and a TCP (transformer coupled plasma).
a) Etching equipment, ICP (inductive coupled plasm)
a) An etching apparatus can be suitably used. Preferably, the etching is performed under such a condition that the side walls of the wirings 18a, 18b, 18c are substantially perpendicular to the semiconductor substrate surface. FIG. 3 shows a portion where the wiring of the first wiring layer 18 is densely formed. The height of the wiring in this portion is h1, and the interval between the wirings is s1.

Subsequently, as shown in FIG. 3C, the resist pattern 16 is removed by a known ashing technique, and the wiring of the first wiring layer 18 is formed by an anisotropic plasma etching technique using a fluorine-based gas. The region having the thickness d1 on the surface of the underlying insulating layer 12 is etched. Preferably, the etching is performed under the condition that the TiN film in the uppermost layer of the wiring is not substantially etched. As an etching apparatus, for example, parallel plate type RIE (reactive ion etc.)
hing) apparatus or ICP etching apparatus can be suitably used. Further, if necessary, deposits attached to the substrate surface during dry etching are removed by ashing, wet cleaning, or the like.

Subsequently, as shown in FIG. 4D, a fluorinated silicon oxide film is deposited using, for example, a high-density plasma CVD method, and planarized by, for example, a CMP method to form an interlayer insulating layer 20. As an example of high-density plasma CVD, there is a helicon plasma CVD method using a source gas containing SiH ₄ , SiF ₄ , O ₂ , and Ar. less than,
Examples of typical deposition conditions (Murota et al., Monthly Semiconducto
r World 1996.2, p. 82). SiF ₄ : SiH ₄ = 1: 1 O 2 / (SiF ₄ + SiH ₄ ) = 1 to 2 Ar / (SiF ₄ + SiH ₄ ) = 1 Substrate temperature = 400 ° C. Helicon plasma power (13.56 MHz) = 2.5
kW bias power (400 kHz) = 2 kW

The dielectric constant of the fluorinated silicon oxide film described above is lower than that of a pure silicon oxide film, for example, 3.5.
It has a degree value. Further, under such conditions, deposition by plasma CVD and etching by Ar sputtering are performed at the same time, and fine wiring can be embedded. However, the difference between the height of the surface of the fluorinated silicon oxide film deposited on the wide wiring and the height of the surface of the fluorinated silicon oxide film deposited on the region where no wiring exists, for example, cannot be eliminated. The surface of the silicon oxide film is planarized by, for example, a CMP method. For CMP, for example, a slurry containing silica particles as an abrasive is used.

Perform high-density plasma CVD under appropriate conditions
High film that can be directly contacted by wiring
A quality fluorinated silicon oxide film can be deposited.
In particular, the presence of Si-F bonds in the film makes the film
Become hydrophobic. Therefore, the moisture content in the film is sufficiently low.
It becomes. However, the amount of added fluorine is too large
And Si (-F) in the film_TwoThe amount of coupling increases. this
In some cases, the membrane is hygroscopic. Therefore, fluorinated silicon
The amount of fluorine added to the oxide film depends on the amount of Si (-F) in the film. _TwoBinding amount
Should be limited to a sufficiently small range. That is,
FT-IR (Fourier transformed infrared absorptio
n (Si spectroscopy) method._TwoConclusion
Absorption by combination (980cm^-1Observed near)
Is not performed, or absorption of Si—O bond (1080c
m^-1(Observed in the vicinity) compared to the integrated intensity of Si (−
F)_TwoIntegrated intensity of bond absorption of about 2.0% or less, preferably
Or less than about 0.1%.
Due to this limitation of the amount of added fluorine, fluorinated silicon acid
The lower limit of the dielectric constant of the oxide film is limited. At present
Approximately 3.3 dielectric
It is the lower limit of the rate. However, with the advancement of film deposition technology in the future,
And Si (-F)_TwoWithout increasing the amount of binding
A lower dielectric constant may be obtained.

In the wiring structure of this embodiment, the first wiring layer 18
The region of the thickness d1 on the surface of the base insulating layer 12 between the wirings is etched, and an interlayer insulating layer 20 made of a fluorinated silicon oxide film having a low dielectric constant is formed in this region. That is, the height of the bottom surface of the fluorinated silicon oxide film formed between the adjacent wirings is larger than the height of the bottom surface of the wiring by the thickness d.
It is lower by one. As a result, the spread of the electric field between the wirings is limited within the fluorinated silicon oxide film having a low dielectric constant, and the effective dielectric constant between the wirings decreases to a value close to the dielectric constant of the fluorinated silicon oxide film itself. The capacitance between the wirings can be effectively reduced.

Specifically, the effect is obtained when the thickness d1 is about 20% or more of the wiring interval s1. For example,
The wiring interval s1 is 0.50, 0.35, 0.25, 0.1
In the case of 8 μm, the thickness d1 is about 0.1 and 0.0, respectively.
7, 0.05, 0.036 μm. If it is about 50% or more, the capacitance can be further reduced.
For example, the wiring interval s1 is 0.50, 0.35, 0.2
When the thickness is 5, 0.18 μm, the film thickness d1 is about 0.
25, 0.18, 0.12, 0.09 μm.

3 and 4, the thickness d1 of the surface of the base insulating layer 12 between the wirings of the first wiring layer 18 is schematically shown.
Is shown as completely etched in a rectangular shape, but in reality, it is difficult and not necessary to etch completely in a rectangular shape. For example, the periphery may be etched into a rounded shape. In this case, the film thickness d1 may be a film thickness value near the center between the wirings. Further, depending on the flattening state of the surface of the base insulating layer 12, the heights of the bottom surfaces of the adjacent wirings may not match. In this case, the difference between the height of the bottom surface of the fluorinated silicon oxide film and the height of the bottom surface of the wiring is the average of the height of the bottom surface of the fluorinated silicon oxide film near the center between adjacent wirings and the average of the bottom surface of the adjacent wiring. What is necessary is just to obtain | require it as a difference with height.

Thereafter, if necessary, the same steps are repeated to form the second and subsequent wiring layers and interlayer insulating layers. FIG. 4E is a cross-sectional view showing a state where the second wiring layer 22 including the wirings 22a, 22b, and 22c is formed, and further, the second interlayer insulating layer 24 is formed. In the wiring structure shown in FIG.
8 and the function of insulating the second wiring layer 22 from each other.
The film thickness between the wiring layers 18 and 22 of the interlayer insulating layer 20 is 0.6 to
Make it about 1.5 μm. Although not shown, a via hole for connecting the wiring of the first wiring layer 18 and the wiring of the second wiring layer 22 is formed in a necessary portion of the interlayer insulating layer 20, and for example, a W (tungsten) film is formed. A plug filling the via hole is formed by CVD and etch back. In this embodiment, the high-density plasma C
Since it is formed of a fluorinated silicon oxide film deposited by the VD method, it is possible to form a via hole by anisotropic plasma etching using a normal resist pattern as a mask.

Thereafter, a surface protection film is further formed, and bonding pads are formed, thereby completing the semiconductor integrated circuit wafer manufacturing process. If the second wiring layer 22 is the uppermost wiring layer, a surface protection film is directly formed thereon.

In this embodiment, an example is described in which the surface of the base insulating layer 12 between the wirings of the first wiring layer 18 is etched by anisotropic plasma etching. Is not essential, and isotropic etching may be performed. In this case, the surface of the underlying insulating layer 12 between the wirings of the first wiring layer 18 is etched in a concavely curved shape, and further, the etching progresses under the wiring in the lateral direction. As a result, a fluorinated silicon oxide film of the interlayer insulating layer 20 is formed along the spread of the electric field between the wirings. Thereby, there is an advantage that the effect of restricting the spread of the electric field between the wires of the first wiring layer 18 within the fluorinated silicon oxide film is increased, and the effect of reducing the capacitance between the wires is further enhanced.

In the present embodiment, after the etching of the metal film 14, the resist pattern 16 is removed, and the surface region of the base insulating layer 12 is etched by a gas plasma etching different from the etching of the metal film 14. Etching was performed. However, the present invention is not limited to this. For example, the surface region of the base insulating layer 12 can be etched by lengthening the over-etching time of the etching of the metal film 14. This over-etching is also effective, for example, in the case where the metal film 14 includes an Al alloy film containing Si, to remove an etching residue caused by a precipitate of Si.

In this embodiment, the interlayer insulating layer 20 is
Although formed by a fluorinated silicon oxide film deposited using a helicon plasma CVD method, the present invention is not limited to this, and other high-density plasmas such as ICP C
It is also possible to use VD, ECR CVD, or the like.
Also, an example using a gas system containing SiH ₄ , SiF ₄ , O ₂ and Ar has been described, but Si ₂ F ₆ , SiH ₃ F,
It is also possible to use a gas system containing SiH ₂ F ₂ , SiHF ₃ or the like. It is not essential to use a fluorine compound gas of Si as the fluorine compound gas, and CF ₄ , C
It is also possible to use ₂ F _6, NF ₃ or fluorine compound gas. In this case, it is also possible to use only a fluorine-free compound gas as the Si raw material. Conversely, it is also possible to use only a fluorine compound gas as the Si raw material. Si (OC
It is also possible to use ₂ H ₅₎ organic compounds such as _4. FSi (OC ₂ H ₅ ) ₃ , F ₂ Si (OC ₂ H ₅ )
It is also possible to use fluorinated organosilicon compounds such as ₂ .

The fluorinated silicon oxide film can be formed by a normal plasma CVD method instead of the high-density plasma CVD method. However, in this case, the lower limit of the dielectric constant at which the hygroscopicity can be kept low is higher than when the high-density plasma CVD method is used. further,
The interlayer insulating layer 20 can be formed using a material other than the fluorinated silicon oxide film, or a material having a lower dielectric constant than other silicon oxide films, such as SiBON formed by a plasma CVD method. It is also possible to use Further, if the problems such as adhesion and water release are solved, it is of course possible to use various siloxane SOG, organic materials, and low dielectric constant materials such as porous materials.

In this embodiment, the wiring of the first and second wiring layers 18 and 22 is made of Al mainly composed of an Al-containing film.
Although system wiring was used, the present invention is not limited to this.
Also, one or both of the second wiring layers 18 and 22 can be another wiring, for example, a Cu-based wiring or a wiring mainly composed of a W film (hereinafter referred to as “W-based wiring”). Also,
After forming another wiring layer below the first wiring layer 18,
The first wiring layer 18 and the interlayer insulating layer 20 can be formed by the above method.

Further, in this embodiment, the insulating layer 12 below the first wiring layer 18 is called a “base insulating layer”, and the first wiring layer 1
8 and between the first wiring layer 18 and the second wiring layer 22
The insulating layer 20 between them is referred to as an "interlayer insulating layer", but these terms should not be construed as limiting for the reasons described below. That is, the insulating layer 12 below the first wiring layer 18 functions as a “base insulating layer” for the first wiring layer 18 and, at the same time, the first wiring layer 18 and the semiconductor substrate 1.
It also functions as an "interlayer insulating layer" between the transistor and the transistor formed on the zero surface. Further, when another wiring layer is formed below the first wiring layer 18, between the wirings of the lower wiring layer and between the lower wiring layer and the first wiring layer 18. It also functions as an “interlayer insulating layer”. Similarly, between the wirings of the first wiring layer 18 and the first wiring layer 18
The interlayer insulating layer 20 between the first wiring layer 22 and the second wiring layer 22 also functions as a “base insulating layer” for the second wiring layer 22.

Embodiment 2 FIGS. 5A, 5B and 5C
6 (d), 6 (e) and 6 (f) are cross-sectional views of a second embodiment showing the steps of forming the wiring structure of the present invention. As shown in FIG. 5A, in the same manner as in the first embodiment,
A base insulating layer 12 is formed on a semiconductor substrate 10 on which structures such as a transistor and a field oxide film are formed, and a first wiring layer 18 including wirings 18a, 18b, and 18c is formed thereon. Similarly, the height of the wiring of the first wiring layer 18 is h1, and the interval between the wirings is s1. Then, the first wiring layer 1
The region having the thickness d1 on the surface of the base insulating layer 12 between the wirings 8 is etched.

Next, as shown in FIG. 5B, a fluorinated silicon oxide film is deposited by using, for example, a high-density plasma CVD method. At this time, the deposition time is set shorter than in the case of the first embodiment, and the deposition is completed when the upper and side surfaces of the wiring are covered before the state where the space between the wirings of the first wiring layer 18 is buried. . Here, the thickness of the fluorinated silicon oxide film formed on the surface of the base insulating layer 12 between the dense wirings of the first wiring layer 18 is t1, and the thickness formed on the upper surface of the wiring is t2. When the deposition time is set so as not to fill the space between the wirings of the first wiring layer 18, t1 and t2 are substantially equal to the film thickness deposited on the flat substrate. When depositing a fluorinated silicon oxide film by high-density plasma CVD, a high-frequency power is applied to the substrate side to generate a bias potential, whereby deposition by CVD and sputter etching by Ar and oxygen ions proceed simultaneously. As a result, even when the side wall of the wiring is formed substantially vertically, the surface of the fluorinated silicon oxide film on the side wall is substantially uniform over substantially the entire surface except for the vicinity of the corner at the upper end of the wiring. It has a forward inclination (a forward tapered shape). That is, in the fluorinated silicon oxide film, the film thickness at the upper portion of the sidewall excluding the vicinity of the corner at the upper end of the wiring is smaller than the film thickness at the lower portion. The average thickness of the fluorinated silicon oxide film deposited on the sidewall of the wiring (the thickness on the sidewall of the fluorinated silicon oxide film at the center of the height of the wiring) is larger than t1 and t2. thin. Further, a facet is formed near the corner at the upper end of the wiring. This facet has a constant angle (typically 45 to 60 ° relative to the horizontal) determined by the angular dependence of the sputter etch rate. This fluorinated silicon oxide film becomes a part of the interlayer insulating layer, and becomes the base layer 26 for the low dielectric constant film formed in the next step.

Subsequently, as shown in FIG. 5C, a coating solution containing, for example, a siloxane oligomer is applied to the entire surface of the substrate by spin coating, and cured to form a low dielectric constant film 28 made of siloxane SOG. To form At this time, the base film 26 formed by the high-density plasma CVD method has a forward inclination on the side wall of the wiring of the first wiring layer 18 and the facet is formed at the corner at the upper end of the wiring. Even when the distance between the wirings becomes small, it is possible to satisfactorily bury the portion left after the base film is deposited between the wirings by the siloxane SOG. The curing is realized by evaporating a solvent contained in the coating solution by heating at 80 ° C. and 200 ° C., for example, and then causing a polymerization reaction by heating at 400 ° C. The low dielectric constant film 28 formed by this method has a dielectric constant of about 3.0. At this stage, the surface of the low dielectric constant film 28 has a gentle shape compared to the surface of the base film 26. For example, on a region where wiring is formed at high density,
As shown in the cross-sectional view of FIG. 5C, it has a substantially flat shape. However, for example, the height of the surface of the low dielectric constant film 28 deposited on the region where the wiring is formed at a high density and the height of the surface of the low dielectric constant film 28 formed on the region where the wiring is not formed are different. The difference remains. In order to eliminate this difference in surface height, it is preferable to perform planarization by, for example, a CMP method.

As described above, the side surface of the base film inclined in the forward direction improves the embedding property of the low dielectric constant film between the wirings. This effect is further enhanced when facets are formed at the corners of the upper end of the wiring. In order to obtain a high embedding property improving effect, the angle of inclination of the side surface with respect to the vertical surface of the substrate is about 2 ° or more, preferably about 4 ° or more, and more preferably about 6 ° or more. But the slope is even larger,
For example, it is not preferable that the angle is about 8 ° or more. By reducing the inclination angle, a large portion of the volume between the wirings is buried with a low dielectric constant film, and the capacitance between the wirings can be reduced. This angle can be controlled by the conditions of the high-density plasma CVD, particularly the conditions of the substrate bias.

The effect of improving the burying property by the side surface of the base film inclined in the forward direction is particularly remarkable when a specific method is used for depositing a low dielectric constant film. For example, a low-permittivity material such as fluorinated amorphous carbon can be suitably deposited by using a high-density plasma CVD method using a substrate bias. Due to the similarity in the deposition method between the base film and the low dielectric constant film, the ability to embed the low dielectric constant film between fine wirings is effectively improved. In this case, the base film and the low dielectric constant film can be deposited using the same film forming apparatus. That is, it is possible to deposit a base film and a low dielectric constant film by changing the gas atmosphere in the same deposition tank, or to deposit each film in a separate deposition tank in the same apparatus. Is also possible.

FIG. 6D shows a cross-section of the state where the low dielectric constant film 28 is formed until the low dielectric constant film 28 on the wiring upper surface of the first wiring layer 18 is removed and the low dielectric constant film 28 filling the space between the wirings is formed. The figure is shown. As shown in FIG. 5, when a sufficiently thick low dielectric constant material film 28 is formed at the stage of FIG.
By performing the CMP, the low dielectric constant film 28 on the region where the wiring is formed at a high density and the region where the wiring is not formed is formed.
The difference in surface height can be eliminated, and flattening can be realized. Specifically, the CMP of the portion where the wiring is not formed
The thickness of the previous low dielectric constant film 28 is equal to or more than the sum of the height h1 of the wiring and the thickness d1 obtained by etching the surface of the base insulating layer 12 between the wirings, preferably 1.5 times or more, and Preferably, it is twice or more. For example, by performing CMP using a slurry containing MnO ₂ as an abrasive, the etching rate of the low dielectric constant film 28 can be increased as compared with the etching rate of the base film 12 (Y. Homma et al.).
al., Proceedings of the 12th International Confere
nce on VLSI Multilevel Interconnection Conference
(1995) p. 457). As a result, the underlying film 2 on the upper surface of the wiring
Using the fluorinated silicon oxide film of No. 6 as an etching stopper, the CMP can be completed with high controllability when the low dielectric constant film 28 on the wiring is removed.

Subsequently, as shown in FIG. 6E, a fluorinated silicon oxide film is deposited again by the high-density plasma CVD method, and a cap film 30 is formed. Through the above steps, the interlayer insulating layer 32 including the base film 26, the low dielectric constant film 28 filling the space between the wirings, and the cap film 30 is formed.

In the wiring structure of this embodiment, the first wiring layer 18
A low dielectric constant film 28 made of siloxane SOG, which is a low dielectric constant material, is embedded between the wirings. The height of the lower surface of the low dielectric constant film 28 is higher than the height of the lower surface of the wiring by (d1-
t1), and the height of the upper surface is higher than the height of the upper surface of the wiring by t2. Further, the underlying film 26 on the side wall of the wiring of the first wiring layer 18 and the cap film 30 on the wiring are also formed of a fluorinated silicon oxide film having a lower dielectric constant than a conventional silicon oxide film. Thereby, the capacitance between the wirings can be effectively reduced. The capacitance between the wirings is determined by the dimensions such as s1, h1, t1, and t2, the dielectric constant of the fluorinated silicon oxide film and the siloxane SOG, and the like. Generally, the smaller the thickness of the base film 26, the smaller the capacitance between the wirings. Base film 26
Has a function of improving the adhesion of the low dielectric constant film 28 to the wiring and preventing the water in the low dielectric constant film 28 from diffusing into the wiring or the transistor formed on the surface of the semiconductor substrate 10. In order to improve the adhesion, a sufficient effect can be obtained even if the base film 26 is thinned in a range where a continuous film is formed. On the other hand, in order to prevent the diffusion of moisture, a base film 26 having a certain thickness or more is required. A silicon oxide film deposited by a high-density plasma CVD method has a high moisture diffusion preventing effect as disclosed in US Pat. No. 5,512,513. Therefore, as compared with the case where a film formed by another method is used, a high moisture diffusion preventing effect can be obtained even with a thin film thickness. For example, t1 is 25 nm
The thickness can be reduced to about 10 nm or less depending on the conditions. Therefore, it can be used even when the distance between wirings is reduced due to the progress of miniaturization.

In the conventional wiring structure, a base film made of a silicon oxide film, a silicon oxynitride film, a silicon nitride film or the like has been used. On the other hand, in this embodiment, a fluorinated silicon oxide film is used as the base film 26 for the low dielectric constant film 28. As a result, the wiring capacitance is effectively reduced. It is not obvious to use a fluorinated silicon oxide film as a base film. Heretofore, it has not been confirmed that a fluorinated silicon oxide film has a sufficient effect on improving adhesion and preventing moisture diffusion. On the contrary, it has not been confirmed that the fluorinated silicon oxide film itself has sufficient adhesiveness, and that the amount of water contained in the fluorinated silicon oxide film itself is low enough not to cause a problem such as wiring corrosion. Actually, the effect of improving the adhesion is not significantly deteriorated even by the addition of fluorine. The effect of preventing water diffusion is not significantly deteriorated, and the amount of water in the film is not significantly increased. On the contrary, in fact, S
The inclusion of the i-F bond makes the membrane hydrophobic,
The effect of preventing water diffusion is improved, and the amount of water in the film is also reduced. For this reason, it is possible to make the base film thinner when using the fluorinated silicon oxide film than when using the silicon oxide film.

However, the amount of fluorine added to the fluorinated silicon oxide film needs to be limited to a range in which the film does not contain a significant amount of Si (-F) ₂ bonds. For this reason, the dielectric constant of the base film 26 cannot be reduced below a certain value. However, when used in combination with a low dielectric constant film composed of a material having a dielectric constant lower than that of the fluorinated silicon oxide film, the wiring capacitance can be effectively reduced. Since the wiring is covered with a base film having a high moisture diffusion prevention effect and does not come in contact with low dielectric constant materials,
It is possible to form a low dielectric constant film using various low dielectric constant materials.

In the present embodiment, the thickness (depth) d1 for etching the surface of the base insulating layer 12 is preferably increased by t1 as compared with the first embodiment. However, if d1 is not large enough, or
Even when the surface of the base insulating layer 12 is not etched, both the base film 26 and the low dielectric constant film 28 have a low dielectric constant, so that the wiring capacitance can be reduced to some extent.

Thereafter, if necessary, the same steps are repeated to form the second and subsequent wiring layers and interlayer insulating layers. FIG. 6F shows a second wiring layer 22 including the wirings 22 a, 22 b, and 22 c, a base film 34, a low dielectric constant film 36 buried between the wirings of the second wiring layer 2, and a cap film 38. FIG. 4 shows a cross-sectional view of a state where two interlayer insulating layers 40 are formed. Thereafter, a surface protection film and a bonding pad are formed, and the wafer manufacturing process of the semiconductor integrated circuit is completed.

In this embodiment, a cap film 30 made of a fluorinated silicon oxide film is used for insulation between the wiring layers 18 and 22, and a via hole connecting the wiring layers 18 and 22 is
The cap film 30 is formed. Therefore, it is possible to form a via hole in the same manner as in the case where an interlayer insulating layer is formed using a conventional silicon oxide film. Also, the second wiring layer 22 formed on the surface of the cap film 30
The wiring has the same adhesiveness as before, and there is no problem. In addition, since the fluorinated silicon oxide film has a lower dielectric constant than the conventional silicon oxide film, the capacitance between the wiring layers 18 and 22 can be reduced efficiently. Therefore, the wiring structure according to the present embodiment can maintain the consistency with the conventional manufacturing technique while maintaining the consistency between the wiring and the wiring layers 18 and 22.
The capacitance between them can be effectively reduced.

In this embodiment, siloxane SOG is used to form the low dielectric constant film 28. However, the present invention is not limited to this, and various other low dielectric constant materials may be used. it can. For example, a low dielectric constant material having a dielectric constant of about 3.2 or less, more preferably about 3.0 or about 2.5, and most preferably about 2.0 or less may be used. Further, a low dielectric constant film 28 is formed by using a fluorinated silicon oxide film deposited by a high-density plasma CVD method.
It is also possible to form In this case, the deposition conditions are adjusted to increase the fluorine concentration as compared with the case where the base film 26 and the cap film 30 are formed.
More preferably, the dielectric constant is reduced to about 3.0 or less. Although the film quality of the fluorinated silicon oxide film deteriorates in terms of hygroscopicity and the like as the dielectric constant is lowered, the low dielectric constant film does not directly contact the wiring in the wiring structure of this embodiment, so that the dielectric constant is formed with emphasis on the dielectric constant. It is also possible to use a fluorinated silicon oxide film for which conditions have been set.

In this embodiment, the high-density plasma CV
The fluorinated silicon oxide film deposited by the method D is used as the cap film 3
0, which is used for insulation between the wiring layers 18 and 22. However, the present invention is not limited to this.
It is also possible to use a silicon oxide film or a fluorinated silicon oxide film deposited by the method D. However, in order to reduce the capacitance between the wirings and between the wiring layers 18 and 22, it is preferable that the dielectric constant of the cap film 30 be low. For this purpose, it is preferable to use a fluorinated silicon oxide film deposited by using a high-density plasma CVD method capable of obtaining a low dielectric constant of about 3.5 or less while maintaining high film quality.

In this embodiment, the fluorinated silicon oxide film deposited by the high-density plasma CVD method is used as the base film 26, but the present invention is not limited to this. A forward slope is formed on the side wall of the wiring, and more preferably, a facet is formed at the corner of the upper end of the wiring, and even when the distance between the wirings becomes small, the low dielectric constant film 28 provides good spacing between the wirings. For the purpose of embedding, a silicon oxide film containing no fluorine and formed by, for example, a high-density plasma CVD method using a substrate bias can also be used. A method other than the high-density plasma CVD method can be used as long as it can form a forward slope on the side wall of the wiring, or more preferably, a facet at a corner at the upper end of the wiring. It is not essential to use a film containing fluorine for the purpose of using the low dielectric film 28 as an etching stopper during CMP. However, in order to reduce the capacitance between wirings, it is preferable that the dielectric constant of the base film 26 be low. For this purpose, it is preferable to use a fluorinated silicon oxide film deposited by using a high-density plasma CVD method capable of obtaining a low dielectric constant of about 3.5 or less while maintaining high film quality.

In the present invention, the low dielectric constant film 28
It is also possible to form the low dielectric constant film 30 for burying the space between the wirings by flattening the surface by CMP and then forming the low dielectric constant material film again to form the interlayer insulating layer 32. By forming a film of a low dielectric constant material also between the wiring layers 18 and 22, the capacitance between the wiring layers 18 and 22 and between the wirings can be further reduced. In this case, it is possible to use the same material as the low dielectric constant film 28 used for embedding between the wirings, or to use a different material. In order to form the low dielectric constant film 28 between the wirings, it is necessary to select a material that can fill a minute gap and that can be uniformly formed on a substrate having irregularities. On the other hand, wiring layer 1
Since the low dielectric constant material film between 8 and 22 is formed on a flattened substrate, it is not necessary to have a high embedding property or the possibility of being formed on an uneven substrate, and different materials can be used. . For example, the material can be selected with emphasis on low dielectric constant and ease of forming via holes.

(Embodiment 3) FIGS. 7 (a), (b),
(C), FIGS. 8 (d), (e), (f) and FIG. 9 (g)
FIG. 9 is a cross-sectional view of a third embodiment showing each step of forming a wiring structure according to the present invention. As shown in FIG. 7A, a base insulating layer 12 is formed using a BPSG film or the like on a semiconductor substrate 10 on which structures such as a transistor and a field oxide film are formed, as in the case of the second embodiment. Then, a metal film 14 for forming a first wiring layer is deposited on the substrate. Thereafter, in this embodiment, a silicon oxide film 42 is further formed on the metal film 14 by a plasma CVD method.

Next, as shown in FIG. 7B, a resist pattern is formed, the silicon oxide film 42 is patterned by anisotropic plasma etching using a fluorine-based gas, and the resist pattern is formed by ashing. Remove.
Subsequently, the metal film 14 is patterned using the patterned silicon oxide film 42 as a mask by an anisotropic plasma etching technique using a chlorine-based gas to form the first wiring layer 18 including the wirings 18a, 18b, 18c. Form. Similarly, here, the height of the wiring in the first wiring layer 18 is h1, and the interval between the wirings is s1.

Subsequently, as shown in FIG. 7C, if necessary, the deposits deposited on the side walls of the wiring of the first wiring layer 18 are removed by, for example, ashing, and then a fluorine-based gas is used again. The anisotropic plasma etching is performed to etch the portion of the surface of the base insulating layer 12 between the wirings having the thickness d1. Silicon oxide film 42 on the wiring after this step
Is d2. Since the silicon oxide film 42 on the wiring is also partially etched when etching the surface portion of the base insulating layer 12, the thickness of the silicon oxide film 42 to be deposited is set so that the required film thickness remains. I do.

Next, as shown in FIG. 8D, a fluorinated silicon oxide film is deposited using, for example, a high-density plasma CVD method to form a base film 26. Similarly, here, the base insulating layer 12 between the dense wirings of the first wiring layer 18 is used.
The thickness of the underlying film 26 formed on the wiring is t1, and the thickness of the underlying film 26 formed on the silicon oxide film 42 on the wiring is t2.
And

Next, as shown in FIG. 8E, a low dielectric constant material film made of, for example, siloxane SOG is formed on the entire surface of the substrate, and the low dielectric constant material film on the wiring of the first wiring layer 18 is formed. CMP is performed until it is removed, and a low dielectric constant film 28 filling the space between the wirings is formed. In order to obtain sufficient flatness, it is preferable that the thickness of the low dielectric constant material film 28 before the CMP is increased by d2 as compared with the case of the second embodiment.

Subsequently, as shown in FIG. 8F, a fluorinated silicon oxide film is deposited again by the high-density plasma CVD method, and the cap film 30 is formed. Through the above steps, the interlayer insulating layer 4 including the base film 26, the low dielectric constant film 28 buried between the wirings of the first wiring layer 18, and the cap film 30.
4 is formed.

In the wiring structure of this embodiment, the first wiring layer 18
In addition to the height of the lower surface of the low dielectric constant film 28 buried between the wirings, the height of the upper surface of the low dielectric constant film 28 is lower than the height of the lower surface of the wiring by (d1-t1). It is higher by (t2 + d2) than the height of the upper surface of the wiring. Accordingly, the capacitance between the wirings can be further reduced as compared with the case of the second embodiment. In order to effectively reduce the capacitance between the wirings, the value of (t2 + d2) is preferably about 20% or more, more preferably about 50% or more, of the wiring interval s1.

Thereafter, the same steps are repeated as necessary to form the second and subsequent wiring layers and interlayer insulating layers. FIG. 9G shows the second wiring layer 22 including the wirings 22 a, 22 b, and 22 c, the base film 34, the low dielectric constant film 36 buried between the wirings of the second wiring layer 22, and the cap film 3.
8 shows a cross-sectional shape in a state where a second interlayer insulating layer 48 made of No. 8 is formed. A silicon oxide film 46 is also formed on the second wiring layer 22, and the height of the upper surface of the low dielectric constant film 46 embedded between the wirings of the second wiring layer 22 is higher than the height of the upper surface of the wiring. . Therefore, the capacitance between the wires of the second wiring layer 22 is further reduced as compared with the case of the second embodiment.

Thereafter, a surface protection film and bonding pads are formed, and the wafer manufacturing process of the semiconductor integrated circuit is completed. Although not shown, the interlayer insulating layer 44 includes:
Via holes for connecting the wiring of the first wiring layer 18 and the wiring of the second wiring layer 22 are formed, and a plug made of, for example, W is embedded therein.

In this embodiment, the silicon oxide film is formed on the wiring in order to make the surface of the low dielectric constant film filling the space between the wirings higher than the height of the upper surface of the wiring.
The present invention is not limited to this. For example, by using a fluorinated silicon oxide film having a lower dielectric constant than a silicon oxide film, the capacitance between the wirings and between the wiring layers 18 and 22 can be further reduced. . It is also possible to use a film of a low dielectric constant material having a lower dielectric constant. Further, in this embodiment, the resist pattern is removed after patterning the silicon oxide film on the wiring, but it is also possible to remove the resist pattern after forming the wiring or after etching the surface region of the base insulating layer. .

(Embodiment 4) FIGS. 10 (a), (b),
(C) and FIG. 11 (d) are cross-sectional views of a fourth embodiment showing respective steps of forming a wiring structure of the present invention. FIG.
As shown in (a), in the same process as in Example 2,
On a semiconductor substrate 10, a base insulating layer 12 and a wiring 1
After forming the first wiring layer 18 including 8a, 18b, and 18c, a region having a thickness d1 on the surface of the base insulating layer 12 between the wirings of the first wiring layer 18 is etched. Subsequently, a fluorinated silicon oxide film is deposited using, for example, a high-density plasma CVD method to form a base film 26.

Next, as shown in FIG. 10B, a solution containing, for example, a precursor of a fluorinated polyimide is applied to the entire surface of the substrate and cured to form a low dielectric constant film 28 made of a fluorinated polyimide. To form

Subsequently, as shown in FIG.
The surface of the low dielectric constant film 28 is planarized by the P method. In the case of the present embodiment, unlike the case of the second embodiment, the first wiring layer 1
Instead of continuing the CMP until the low dielectric constant film 28 on the wiring 8 is removed, the CMP is finished when the surface is flattened. At this stage, the thickness of the low dielectric constant film 28 on the wiring is defined as t3. Finally, a fluorinated silicon oxide film is deposited by, for example, a high-density plasma CVD method to form a cap film 30. Through the above steps, the first interlayer insulating layer including the base film 26, the low dielectric constant film 28 having a predetermined thickness on the wiring, and the cap film 30 is buried between the wirings of the first wiring layer 18. 50 are formed. Unlike the case of the second embodiment, the low-dielectric-constant film 28 constituting the interlayer insulating layer 50 is formed not only between the wirings but also on the wirings. For this reason, the capacitance between the wirings and between the wiring layers is further reduced as compared with the case of the second embodiment.

If the thickness t3 of the low dielectric constant film 28 on the wiring after the CMP is insufficient, for example, the thickness of the fluorinated silicon oxide film 30 can be increased. Also,
It is also possible to form another low dielectric constant material film on the surface of the low dielectric constant film 28.

In the present embodiment, unlike the case of the second embodiment, the first wiring layer 18
Since the base film 26 on the wiring is not used as an etching stopper, it is necessary to perform CMP under conditions of high controllability and uniformity. It is also possible to improve the controllability of CMP by selecting the method of forming the low dielectric constant film 28. For example, a high-density plasma C with a substrate bias applied
By forming the low dielectric constant film 28 with fluorinated amorphous carbon deposited by the VD method, the surface after deposition can be made almost flat except that a convex portion is formed on a wide wiring. it can. In this case, as disclosed in, for example, US Pat. No. 5,360,015, the point at which the convex portion on the wide wiring is removed and the entire surface of the low dielectric constant film 28 becomes substantially flat is determined by a change in the motor current of the CMP apparatus. It is possible to detect. Also, JM Neirynck et al.,
Materials Research Society Symposium Proceedings,
As disclosed in Vol. 381 (1995) p. 229, the CMP characteristics of a low-dielectric-constant material also changes depending on the cured state. Depending on the type of low dielectric constant material, after performing a heat treatment for removing the solvent (heating at a temperature of about 150 ° C. or less)
Alternatively, after performing a heat treatment (heating at about 200 to 300 ° C.) for further partial curing, the CMP is performed.
After that, in some cases, it is preferable to perform a heat treatment at a higher temperature (heating at about 350 to 450 ° C.) in order to completely cure.

Subsequently, via holes are formed in the interlayer insulating layer 50, and plugs are formed (not shown). At this time, the cap film 30 can be used as a mask for forming a via hole in the low dielectric constant film 28. That is, a resist pattern corresponding to the via hole is formed on the cap film 30, and an opening corresponding to the via hole is formed by anisotropic plasma etching using a fluorine-based gas.
After that, a via hole is formed in the low dielectric constant film 28 by anisotropic etching using oxygen ions. By this method, it is possible to form a via hole even when the low dielectric constant film 28 is formed of a material having poor resistance to ashing. Many of the organic materials classified as the low dielectric constant materials 3) described in the description of the prior art have poor ashing resistance. Organic porous materials, hydrogenated silsesquioxane SOG, and the like also have poor ashing resistance.

For anisotropic etching using oxygen ions, for example, oxygen gas or N ₂ O, H
Using a gas atmosphere to which ₂ O, CO, etc. are added, a parallel plate type RIE device, ICP plasma etching device, EC
An R plasma etching apparatus, a helicon plasma etching apparatus, or the like can be preferably used. Except for the parallel plate type RIE apparatus, ions are accelerated to an appropriate energy in a direction perpendicular to the substrate by using a substrate bias together. To increase the anisotropy, lower the substrate temperature during etching (100
C. or less, preferably about 50.degree. C. or less, more preferably about 20.degree. C. or less, and most preferably about 0.degree. C. or less. Also, to increase the direction of oxygen ions,
Lower the pressure of the etching atmosphere (about 100 mtorr or less, preferably about 20 mtorr or less, more preferably about 10 mtorr or less, and most preferably about 5 mtorr or less.
mtorr or less). In order to obtain a practical etching rate under such low-temperature and low-pressure conditions, it is preferable to use a high-density plasma etching apparatus such as ICP, ECR, or helicon, which can obtain a high ion density. Further, depending on the material of the low dielectric constant film 28, CF ₄ ,
Adding a fluorine compound gas such as C ₂ F ₆ to the etching atmosphere is also effective to increase the etching rate.

Since the resist is also etched by such anisotropic etching using oxygen ions, the resist can be formed simultaneously with the formation of the via hole in the low dielectric constant film 28 without performing the ashing step for removing the resist pattern. It is possible to remove the pattern. On the other hand, the cap film 30 made of a fluorinated silicon oxide film is hardly etched by anisotropic etching using oxygen ions. Therefore, even if the resist pattern is removed before the formation of the via hole is completed, there is no problem in forming the via hole because the cap film 30 functions as a mask. Conversely, if the removal of the resist pattern has not been completed at the time when the formation of the via hole has been completed, it is necessary to lengthen the overetching time until the resist pattern is removed. Therefore, the etching conditions and the relationship between the resist film thickness and the film thickness of the low dielectric constant film 28 on the wirings 18a, 18b, 18c are appropriately adjusted so that the resist pattern removal is completed before the via hole formation is completed. It is preferable to set.

For the purpose of use as a mask, the material of the cap film is not limited to the fluorinated silicon oxide film, but various inorganic materials can be used.
For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like can be used. Further, the film is not limited to a film deposited by a high-density plasma CVD method.
It is possible to use a film deposited by the VD method, an SOG film, or the like. However, of course, in order to reduce the capacitance between wirings and between wirings, it is preferable to use a fluorinated silicon oxide film having a low dielectric constant.

After the opening corresponding to the via hole is formed in the cap film 30, the resist is removed by ashing, and the via hole is formed in the low dielectric constant film 28 by anisotropic etching using oxygen ions. It is also possible. However, depending on the ashing condition, the low-dielectric-constant film 28 is isotropically etched from the opening of the cap film 30, so that the ashing condition needs to be adjusted. It is also possible to remove the resist by using a solvent that dissolves the resist but does not dissolve the low dielectric constant film 28.

On the other hand, methylsiloxane SOG and inorganic porous materials have relatively high ashing resistance. When these materials are used for the low dielectric constant film 28, via holes can be formed by anisotropic plasma etching using a fluorine-based gas with a resist as a mask. However, even when such a material is used, the surface of the low dielectric constant material exposed on the side wall of the via hole may deteriorate when ashing for removing the resist is performed after etching the via hole. , The hygroscopicity may increase. For this reason, Ito et al., Journal of the Elect
As disclosed in Rochemical Society, Vol. 137 (1990) p. 1212, low temperature (about 100 ° C. or less,
0 ° C. or less, more preferably about 20 ° C. or less), low pressure (about 100 mtorr or less, preferably 20 mto
It is preferable to perform a stabilization treatment using a plasma containing directional oxygen ions (at about rr or less, more preferably about 10 mtorr or less). Thereafter, normal ashing can be performed, or the resist can be removed by extending the oxygen ion processing time. It is also possible to remove the resist using a solvent and omit the ashing by the plasma, or shorten the time.

Further, if necessary, the same steps are repeated to form the second and subsequent wiring layers and interlayer insulating layers. FIG. 11D shows the second wiring layer 22 including the wirings 22a, 22b, and 22c, the base film 34, the low dielectric constant film 36 formed between the wirings of the second wiring layer 22, and on the wiring, and Second interlayer insulating layer 52 composed of cap film 38
FIG. 2 is a cross-sectional view showing a state in which is formed.

The cap film 30 also functions as a film for improving the adhesion of the second wiring layer 22 to the interlayer insulating layer 50. Further, it has a function of preventing moisture released from the low dielectric constant film 28 from diffusing into the second wiring layer 22. Since the fluorinated silicon oxide film deposited by high-density plasma CVD has a high water-dispersion prevention effect and the film thickness required to obtain the necessary diffusion prevention effect is small, the thickness of the cap film 30 is reduced. The capacitance between the wirings of the two wiring layers 22 and the capacitance between the wiring of the first wiring layer 18 and the wiring of the second wiring layer 22 can be reduced. Specifically, the thickness of the fluorinated silicon oxide film deposited by high-density plasma CVD can be reduced to about 25 nm or less, and can be reduced to about 10 nm depending on the conditions. Of course, when the low dielectric constant film 28 is formed using a material capable of forming via holes using a resist as a mask without problems of adhesion and moisture release, the cap film 30 may be omitted. It is possible. In order to improve adhesion and prevent moisture diffusion, a silicon oxide film containing no fluorine, a silicon nitride film, a silicon nitride oxide film, or the like can be used as the cap film 30. When a silicon oxide film is used, it is necessary to use a film having a high moisture diffusion preventing effect deposited using a high-density plasma CVD method, and to reduce the film thickness in order to reduce the capacitance. preferable.

Thereafter, a surface protection film is formed, bonding pads are formed, and the wafer manufacturing process of the semiconductor integrated circuit is completed.

(Embodiment 5) FIGS. 12 (a), (b),
(C) and FIG. 13 (d) are cross-sectional views of a fifth embodiment showing respective steps of forming a wiring structure of the present invention. FIG.
As shown in (a), in the same process as in Example 4,
The first wiring layer 18 including the wirings 18a, 18b, and 18c is formed, and the base film 26, the low dielectric constant film 28 formed between the wirings of the first wiring layer 18 and formed on the wiring, and the interlayer formed of the cap film 30 An insulating layer 50 is formed. Here, the thickness of the cap film 30 is set to t6.

Next, as shown in FIG. 12B, a via hole is formed in the interlayer insulating layer 50, and a plug is formed (not shown). Subsequently, a metal film for forming a wiring of the second wiring layer is formed on the cap film 30. A resist pattern 54 is formed on the metal film, and wirings 22a and 22a are formed by anisotropic plasma etching using a chlorine-based gas.
The second wiring layer 22 including b and 22c is formed. Here, the interval between the wires of the second wiring layer 22 is s11. This etching is completed in a state where the cap film 30 between the wirings of the second wiring layer 22 is not removed.

Next, as shown in FIG. 12C, after removing the resist pattern 54, the second wiring layer 22 is subjected to anisotropic plasma etching using a fluorine-based gas.
After removing the cap film 30 between the wirings, the portion having the thickness d11 on the surface of the low dielectric constant film 28 between the wirings of the second wiring layer 22 is removed by anisotropic plasma etching using oxygen ions.

Further, as shown in FIG.
By repeating the same step as the step of forming the interlayer insulating layer 50, the base film 34, the low dielectric constant film 36 formed between and on the wirings of the second wiring layer 22, and the cap film 3
8 is formed as a second layer interlayer insulating layer 56. Here, the thickness of the underlying film 34 between the wires of the second wiring layer 22 is set to t1.
1. The thickness of the underlying film 34 on the wiring is t12.

In the wiring structure of the present embodiment, unlike the case of the fourth embodiment, the cap film 30 of the first interlayer insulating layer 50 is removed between the wirings of the second wiring layer 22, and the first layer is further removed. Thickness d of the surface of the low dielectric constant film 28 of the interlayer insulating layer 50
Eleven regions have been removed. Therefore, the second wiring layer 2
Between the two wirings, the lower surface of the low dielectric constant film 36 of the second interlayer insulating layer 56 is lower than the lower surface of the wiring of the second wiring layer 22. Therefore, the second wiring layer 22
Since the spread of the electric field between the wirings is limited within the low dielectric constant film 36, the capacitance between the wirings of the second wiring layer 22 is further reduced as compared with the case of the fourth embodiment. In order to effectively reduce the capacitance between the wirings of the second wiring layer 22, the value of (d11 + t6-t11) must be changed to the wiring interval s11.
About 20% or more, more preferably about 50% or more.

Thereafter, if necessary, third and subsequent wiring layers are formed, a surface protective film layer is formed, bonding pads are formed, and the wafer process is completed.

In this embodiment, the wiring of the second wiring layer 22 is formed by anisotropic plasma etching using a chlorine-based gas, the resist is removed, and then anisotropic plasma etching using a fluorine-based gas is performed. The second wiring layer 2
The cap film 30 between the two wirings was removed, and the surface portion of the low dielectric constant film 28 was further removed by anisotropic plasma etching using oxygen ions. However, the present invention is not limited to this. For example, depending on the type of the low dielectric constant film 28, etching can be performed by anisotropic plasma etching using a fluorine-based gas.

In this embodiment, the cap film 30 between the wirings of the second wiring layer 22 is removed and the surface region of the low dielectric constant film 28 between the wirings is removed. By simply removing the cap film 30 between them, the capacitance between the wires of the second wiring layer 22 can be further reduced as compared with the case of the fourth embodiment.

(Embodiment 6) In Embodiments 1 to 5, the first
Although the wiring of the wiring layer 18 and the wiring of the second wiring layer 22 are both formed by the etching method, the present invention is not limited to this. For example, the wiring of the second wiring layer 22 can be formed by the damascene method. is there. FIGS. 14 (a), (b),
(C), FIGS. 15 (d), (e), (f) and FIG.
(G) is sectional drawing of the 6th Example showing each formation process of the wiring structure of this invention. First, as shown in FIG. 14A, the wirings 18a, 18b, 1
An interlayer insulating layer 32 including a first wiring layer 18c including a base film 26, a low-dielectric-constant film 28 buried between the wirings of the first wiring layer 18, and a cap film 30 is formed.

Next, as shown in FIG. 14B, a resist pattern 5 corresponding to a via hole connecting the wiring of the first wiring layer 18 and the wiring of the second wiring layer is formed on the interlayer insulating layer 32.
8 is formed. Using the resist pattern 58 as a mask, anisotropic plasma etching using a fluorine-based gas is performed to form a via hole 60 in the interlayer insulating layer 32.
The via hole 60 is set to such a size that the low dielectric constant film 28 of the first interlayer insulating layer 32 is not exposed on the side wall. In particular, when a film made of a low dielectric constant material having poor resistance to ashing is used as the low dielectric constant film 28, even if a mask misalignment occurs in a photolithography process, for example, the low dielectric constant material allows the via hole 60 to be formed. It is preferable to set the relationship between the size of the wiring of the first wiring layer 18 and the size of the via hole 60 so as not to be exposed on the side wall.

As shown in FIG. 14C, after removing the resist pattern 58, a first interlayer insulating layer 50 is formed.
For example, a low dielectric constant film 62 made of fluorinated polyimide is formed by applying and curing a solution containing a precursor of fluorinated polyimide. At this time, the via hole 60
Are also filled with fluorinated polyimide. Since the surface of the first interlayer insulating layer 50 is flattened, if the thickness of the low dielectric constant film 62 is larger than the dimension (diameter) of the via hole 60, the low dielectric constant film 62 The surface is also almost flat. After coating and curing, CMP may be performed to further improve the flatness. Here, it is assumed that the low dielectric constant film 62 is formed using a low dielectric constant material having poor ashing resistance. Further, for example, a fluorinated silicon oxide film is deposited on the low dielectric constant film 62 to form a cap film 64. The low dielectric constant film 62 and the cap film 64 form an insulating layer 66 between the wirings of the second wiring layer.

Subsequently, as shown in FIG. 15D, a resist pattern 68 corresponding to the groove for forming the wiring of the second wiring layer is formed on the cap film 64, and anisotropically using a fluorine-based gas. Film 6 by reactive plasma etching
4, an opening is formed.

Next, as shown in FIG. 15E, a groove 70 is formed in the low dielectric constant film 62 by anisotropic etching using oxygen ions. At this time, the amount of over-etching is set so that the low dielectric constant film 62 in the via hole 60 is removed. As in the case of forming a via hole in the low dielectric constant film 28 in the fourth embodiment, the resist pattern 68 can be removed in advance, or the low dielectric constant film 62 is etched and the resist pattern 68 is removed. Can be performed simultaneously.

Next, as shown in FIG. 15F, a plug for connecting the wiring of the first wiring layer 18 and the wiring of the second wiring layer and a wiring of the second wiring layer are formed on the entire surface of the substrate. A metal film 72 to be formed is formed. For example, a film thickness of 10 to 1
Ti film of about 00 nm, T of about 20 to 200 nm
An iN film and a Cu film having a thickness of about 0.5 to 2 μm are formed in this order. For the deposition of the Ti film and the TiN film, for example, ionization sputtering (G. Dixit et al., International El
ectron Devices Meeting Digest of Technical Papers
(1996) p. 357), and the CVD method is used to deposit the Cu film. At this time, deposition conditions with high covering properties are selected so that the via holes 60 and the grooves 70 are buried.

Thereafter, as shown in FIG. 16G, the metal film 72 formed on the cap film 64 is removed by, for example, CMP.
Remove by method. As a result, the plug 74 buried in the via hole 60 and connects the wiring of the first wiring layer 18 and the wiring of the second wiring layer, and the second plug buried in the groove 70
The wiring of the wiring layer 22 is formed. Also, if necessary,
For example, K. Ueno et al., Symposium on VLSI Technology
As disclosed in Digest of Technical Papers (1995) p. 27, an oxidation preventing layer is formed on the surface of the wiring of the second wiring layer 22.

In this embodiment, as the wiring of the second wiring layer 22, a Cu-based wiring mainly composed of a Cu film is formed. Although a pure Cu film is used in this embodiment, Cu-Ti, Cu-Z
It is also possible to use various Cu-containing films such as an r alloy. On the other hand, the Ti film improves the adhesiveness of the second wiring layer 22 and the wiring of the first wiring layer 18 and the second wiring layer 22.
Has the function of reducing the contact resistance between the wirings. The TiN film has a function of preventing diffusion of Cu.
It should be noted that a film of a high melting point metal such as Zr, Hf, Ta, or W can be used instead of the Ti film. If there is no problem of adhesion or contact resistance, this film can be omitted. Instead of TiN film, ZrN, HfN, T
aN, WN and other refractory metal nitrides, TiSiN, Ta
It is also possible to use a silicide nitride film of a refractory metal such as SiN or WSiN (these nitrides and silicide nitrides are not limited to substances having a stoichiometric ratio). Of the refractory metals, at least Ta, W, etc. may be used as a single-layer film (for improving adhesion and preventing diffusion).

Thereafter, if necessary, third and subsequent wiring layers are formed, a surface protective film and bonding pads are formed, and the wafer manufacturing process of the semiconductor integrated circuit is completed.

In this embodiment, when forming the groove 70, an opening is formed in the cap film 64 by anisotropic plasma etching using a fluorine-based gas, and thereafter, by anisotropic plasma etching using oxygen ions. The low dielectric constant film 62 is etched. In the anisotropic etching using oxygen ions, the etching rate of the fluorinated silicon oxide film is extremely low. Not etched. Therefore, the depth of the groove 70 is automatically determined by the thickness of the low dielectric constant film 62. Also, as shown in FIG. 15E, the mask for forming the groove 70 is wider than the mask for forming the via hole in a portion overlapping the via hole 60 in consideration of misalignment. When the groove 70 is formed, the via hole 60 does not spread. Further, as schematically shown in FIG. 17, even if the mask for forming the groove 70 is shifted with respect to the via hole 60, the dimension of the via hole 60 is reduced but does not spread. In this sense, the method of the present embodiment has an advantage that a margin for mask misalignment is large.

In this embodiment, after the via hole 60 and the groove 70 are formed, the metal film 72 is formed, and the plug 74 and the wiring of the second wiring layer 22 are simultaneously formed by performing the CMP. The present invention is not limited to this,
At the stage when the via hole 60 is formed, formation of a metal film and CM
It is also possible to form the plug 74 by performing P and then form the groove 70 to form the wiring of the second wiring layer 22. Further, in the present embodiment, the cap film 64 is left as a part of the insulating layer 66 between the wirings of the second wiring layer 22, but the present invention is not limited to this.
It is also possible to remove the cap film 64 by appropriately setting the conditions of the CMP for forming the wiring of FIG.

In this embodiment, Al-based wiring formed by etching is used as the wiring of the first wiring layer 18, and Cu-based wiring formed by the damascene method is used as the wiring of the second wiring layer 22. However, the present invention is not limited to this.

In a conventional semiconductor integrated circuit, Al-based wiring formed by an etching method is generally used. Although it is possible to form Al-based wiring by a damascene method, it is necessary to introduce new equipment such as a CMP apparatus. Therefore, Al-based wiring is generally formed by an etching method following the conventional technology. Is preferred. On the other hand, it is difficult to form a Cu-based wiring by an etching method, and it is preferable to form the Cu-based wiring by a damascene method. Note that the W-based wiring is also preferably formed using a damascene method.

In the wiring structure of the present invention, one or both of the Al-based wiring and the Cu-based wiring can be provided in a plurality of layers. Further, another wiring, for example, a W-based wiring can be provided. The W-based wiring has a high resistance but can be formed finely. For example, a bit line wiring in a DRAM cell array or a local wiring in an SRAM cell (for example, T. Ueda et al., Symposium on VLSI Techno)
logy Digest of Technical Papers (1996) p. 142, K.
Furumochi et al., International Solid-State Circuit
s Conference Digest of Technical Papers (1996) p.
156). Al-based wiring is widely used in conventional LSIs, can be formed at low cost, and has a lower resistance than W-based wiring, so it is generally used for signal wiring and power supply wiring. Can be. Further, since the Cu-based wiring has a lower resistance than the Al-based wiring, if it is used for, for example, a long-distance (1 mm or more) signal wiring, the operating speed of the LSI can be improved, and the clock signal can be improved. If it is used for wiring for distribution, it is possible to improve the operation speed by reducing the shift of the operation timing in the semiconductor chip due to the delay of the clock signal. It is also possible to improve the operation stability by reducing it.

As described above, the performance of the semiconductor integrated circuit can be improved by using the Cu-based wiring. However, at present, the Cu-based wiring has a poor track record in mass production, and there are still issues to be considered in terms of effects on transistor characteristics, productivity, cost, yield, and the like. Even if these problems can be solved technically, it is necessary to introduce a new apparatus for performing a Cu film forming process and a damascene process for mass production. In particular, Cu has the potential to degrade the transistor characteristics, and limits the layout of the device in a clean room in order to prevent cross-contamination. For this reason, it is difficult to mass-produce LSIs having Cu-based wiring by retrofitting existing production plants. In addition, even when constructing a new factory, it requires a process with a poor track record,
Equipment and process development costs are high. Further, the cost of the material is higher than that of the Al-based wiring.

Therefore, at least at present, Cu-based wiring is disadvantageous in cost as compared with Al-based wiring. Therefore, even if there is a demand for a high-performance semiconductor integrated circuit using Cu-based wiring, no more Cu-based wiring is used (only Al-based wiring or Al-based wiring and W
There is a great demand for low-cost semiconductor integrated circuits (using system wiring and the like). Producers of semiconductor integrated circuits are required to respond to such actual demands. In particular, in the ASIC business such as a gate array, a standard cell, and an embedded cell array, it is required to produce a product meeting various customer needs flexibly and at low cost. To meet such demands, C
It is necessary to produce a product that does not use u-based wiring and a product that uses Cu-based wiring in a form that makes use of each other.

In a gate array type ASIC, theoretically, if a basic cell in which a fixed number and shape of transistors are arranged is prepared, a product meeting various customer needs is manufactured using the transistor in the basic cell. can do. However, in reality, if all necessary circuit blocks are developed after receiving an order from an individual customer, the development period becomes longer and the development cost becomes higher. If a sufficient development period cannot be secured, it is difficult to develop a high-performance product. In order to solve such problems, not only basic cells but also adders,
It is necessary to develop circuit blocks for realizing frequently used functions such as multipliers, SRAMs, CPUs, and DSPs in advance and prepare them as macro cells. Upon receiving an order from a customer, select an appropriate macro cell, combine it with a newly designed circuit block using basic cells, and produce a semiconductor integrated circuit with the required functions to shorten delivery time and develop Cost reduction can be realized. In other words, having a macro cell library consisting of a large number of macro cells with high performance and excellent versatility will provide products that satisfy various demands from customers with short delivery time, low development costs, and high competitiveness. Essential to get.

In the gate array, the macro cell is also
It is formed using a transistor in a basic cell. On the other hand, in standard cells and embedded cell arrays, dimensions and sizes are adjusted according to the requirements of each macro cell.
It is formed using a transistor whose shape is determined. For standard cells and embedded cell arrays,
Since the functions required by individual customers are realized on the basis of the macro cell (functional cell), the importance of the macro cell is higher than that of the gate array.

In order to separately develop a large number of macro cells for a product not using Cu-based wiring and for a product using Cu-based wiring, a long development period and a large cost are required. Therefore, it is preferable to use a common macro cell for a product using Cu-based wiring and a product not using the same as much as possible. Actually, the ASIC maker already has a library composed of a large number of macrocells that have been designed on the premise of Al-based wiring and have been checked for operation. Furthermore, in recent years, there has been an increasing movement to share a macro cell among manufacturers as IP (Intellectual Property). An object of the present invention is to increase the interchangeability between manufacturers by sharing a high-performance macro cell required by many users, to improve user convenience, and to reduce the macro cell development burden on individual manufacturers. Therefore, a macro cell designed and confirmed to operate on the premise of Al-based wiring can be used in a product using Cu-based wiring while maintaining IP exchangeability.
It is desired to find a method of using the Cu-based wiring at low cost while utilizing the low resistance and high electromigration resistance of the Cu-based wiring.

Therefore, in the following, what part of the product using the Cu-based wiring is most efficient to use the Cu-based wiring is considered.

In products that can use Cu-based wiring,
The connection in such a macrocell is C
The effect of using the u wiring is small. First, in a macro cell having a small scale, even if the wiring resistance is reduced by replacing the Al-based wiring with the Cu-based wiring, the characteristics are hardly improved. This is because the performance is determined mainly by the performance of the transistor and the wiring capacitance. On the other hand, in a large-scale macrocell, the wiring resistance may affect the characteristics in some cases. In such a macrocell, the characteristics may be improved by replacing the Al-based wiring with the Cu-based wiring. However, as long as the macrocell is designed based on the Al-based wiring, the wiring is simply replaced with the Cu-based wiring. However, it can be said that there is a low possibility that a large improvement in characteristics can be realized.

Further, in order to use a macro cell designed on the premise of Al-based wiring for Cu-based wiring, a test device is manufactured and characteristics are evaluated before the actual use in a product, and necessary characteristics are evaluated. It is necessary to confirm that it is obtained. Even if a remarkable change in the characteristics is not expected from the difference in the wiring resistance between the Al-based wiring and the Cu-based wiring, it is undeniable that a change in the process may cause an unexpected change in the characteristics. The reason is that replacing the Al-based wiring using the etching method with the Cu-based wiring using the damascene method causes a large process change that is not limited to a mere change in material.

It is known that Cu forms a deep level in Si. Therefore, when a Cu-based wiring is used, there is a concern that Cu in the wiring diffuses into the transistor and deteriorates the characteristics of the transistor. Of course, in order to prevent such a phenomenon, Cu
In forming the system wiring, a diffusion preventing layer made of, for example, a TiN film is used. However, care must be taken especially when the lower wiring layer close to the transistor is a Cu-based wiring layer. Even though there is actually no problem of transistor characteristic deterioration due to Cu diffusion, it is essential to evaluate and confirm the influence of Cu-based wiring on transistor characteristics and reliability before actually using Cu-based wiring. Such an evaluation usually requires a period of several months or more. Therefore, if it is not possible to obtain the characteristic improvement justified by the cost of performing such evaluation and confirmation work,
It can be said that the value of replacing the Al-based wiring in the macro cell with the Cu-based wiring is small.

Of course, if the wiring dimensions are reduced on the premise of the low resistance and high electromigration resistance of the Cu-based wiring, the area of the macrocell can be reduced and the characteristics can be improved. However, for this purpose, it is necessary to newly design a mask, manufacture a test element and confirm the operation, and this operation usually requires a period of several months or more. For example, it is necessary to redesign only a limited number of macrocells of high importance on the premise of Cu-based wiring, confirm operation, and prepare as a second macrocell library for products using Cu-based wiring Is possible. However, all of the large number of macrocells in the library
Re-designing for system wiring and confirming operation requires a large cost, which is not practical.

On the other hand, for the following wirings, a great effect can be obtained by replacing the Al-based wiring with the Cu-based wiring.

1) Long-distance signal wiring The wiring in a macrocell or other circuit blocks has a distance of only about 100 μm to several mm at most even if it is long. On the other hand, the wiring connecting between the circuit blocks or between the I / O cell (for exchanging signals with the outside of the semiconductor integrated circuit) and the circuit block may be as short as one line.
Some wirings have a distance of about mm or more and have a distance about the same as the chip size of the semiconductor integrated circuit (for example, 1 cm or more). Since the resistance and capacitance of a wiring are proportional to the length of the wiring, such a long-distance wiring has a large resistance and capacitance. This causes a large signal delay and often limits the operation speed of the entire semiconductor integrated circuit.

On the other hand, for example, a Cu-based wiring having a low resistance is used for such a long-distance wiring to reduce the wiring resistance, or the wiring size is reduced on the assumption that the Cu-based wiring has low resistance. By reducing the capacitance, the signal delay can be reduced and the operation speed of the semiconductor integrated circuit can be improved. For such long-distance signal wiring,
It goes without saying that the use of the wiring structure of the present invention for reducing the capacitance between wirings described in the first to sixth embodiments is effective for further improving the operation speed.

2) Clock Wiring Many circuit blocks in a semiconductor integrated circuit operate in synchronization with a common clock signal. However, the clock wiring for distributing the clock signal in the semiconductor integrated circuit has a distance (about 1 cm or more) which is at least as large as the size of the semiconductor chip.
And has large resistance and capacitance. Therefore,
Due to the delay of the clock signal due to the clock wiring, the timing of the clock signal transmitted to different circuit blocks in the semiconductor integrated circuit shifts (referred to as “skew occurs”), and the synchronization operation becomes abnormal. If the margin of the timing is increased in order to prevent the operation abnormality, the operation speed decreases.

By reducing the resistance by using a Cu-based wiring for such a clock wiring, or reducing the capacitance by reducing the wiring size, circuit blocks arranged at various positions in a semiconductor chip are reduced. The skew of the clock signal between them can be reduced. Thereby, the operation speed of the semiconductor integrated circuit can be improved. It is needless to say that the use of the wiring structure of the present invention for reducing the capacitance between wirings described in the first to sixth embodiments is effective for further improving the operation speed.

3) Power Bus Wiring Needless to say, it is necessary to supply power to all elements in the semiconductor integrated circuit in order to operate the semiconductor integrated circuit. In order to supply power, many wirings are provided in a hierarchy. Among them, a wiring commonly provided to supply power to a large number of elements is generally called a power supply bus. For example, U.S. Pat. No. 4,511,914 describes an example of a power supply bus provided in a grid to supply power to basic cells in a gate array.
No. 4 discloses an example of a power supply bus provided in a grid for supplying power to a memory array.

Such a power supply bus wiring often has a length (1 cm or more) substantially equal to or larger than the size of the semiconductor chip, and a large direct current (more precisely) to supply power to many elements. Means pulsating current). Therefore, there is a high possibility that an electromigration failure occurs. When the resistance is high, a voltage drop occurs when many elements operate at the same time and a large current flows, which causes a malfunction. In order to solve such a problem, resistance is low and electromigration resistance is high,
The effect of using Cu-based wiring is great.

By the way, the current semiconductor integrated circuit has 2
It is customary to use a multi-layer wiring comprising one or more wiring layers. The above-described macro cell is formed by, for example, forming wirings mainly in directions orthogonal to each other on the first and second Al-based wiring layers, and connecting the transistors. In addition, one or more Al-based wiring layers may be further provided thereon.

Therefore, for example, the two Al-based wiring layers used for connection in the macro cell are used as they are, and the Al-based wirings on the upper side are replaced with Cu-based wirings, or one or more layers are formed thereon. A further Cu-based wiring layer is added, and the above-mentioned long-distance signal wiring, clock wiring,
It can be used for power bus wiring and the like. In addition, 2
When a macro cell is formed using an Al-based wiring layer exceeding the number of layers, it is also possible to use those wiring layers as they are and provide a Cu-based wiring layer thereon.
Further, when the upper wiring layer, for example, the third wiring layer is mainly used only for limited applications, for example, only for connection between circuit blocks inside the macro cell, this wiring layer is formed of Cu-based wiring. It is also possible to replace with a layer. If only the upper wiring layer is used, there is little possibility that the transistor characteristics will be adversely affected even if it is replaced with a Cu-based wiring layer.

FIGS. 26A and 26B are cross-sectional views schematically showing examples of the wiring layer configuration of a product not using Cu-based wiring and a product used. FIG. 26 (a) shows C
This is a wiring layer configuration of a product that does not use u-based wiring, and first, second, and third Al-based wiring layers 106, 108, and 110 are formed on a Si substrate 10 in order from the bottom. An interlayer insulating layer is formed between the Si substrate 10 and the first Al-based wiring layer 106 and between the respective wiring layers. It is also possible to provide, for example, one W-based wiring layer below the first Al-based wiring layer 106. For connection in each circuit block, the two Al-based wiring layers 10 are mainly used.
Wirings formed at narrow intervals in the direction perpendicular to each other are used for 6,108. The third Al-based wiring layer 110 is mainly used for forming, for example, long-distance signal wiring between circuit blocks, power supply bus wiring, clock wiring, and the like. It is preferable that these wirings have low wiring resistance and wiring capacitance. Therefore, the first and second layers of Al
Compared to the wiring in the circuit block formed in the system wiring layer,
Increase the wiring width and spacing. Further, in order to reduce the wiring resistance, the height of the wiring (the thickness of the metal film used for forming the wiring) is made larger than that of the first and second Al-based wirings.

On the other hand, a product using Cu-based wiring has a wiring layer structure as shown in FIG. 26B, for example. That is, the first and second A in FIG.
The 1-system wiring layers 106 and 108 are used as they are, the third-layer Al-based wiring layer is replaced with a first-layer Cu-based wiring layer 112, and a second-layer Cu-based wiring layer 114 is further added. The wirings in the individual circuit blocks formed on the first and second Al-based wiring layers are basically used as they are. That is, a common mask pattern is used for products that do not use Cu-based wiring. However, as a matter of course, minor modifications to improve performance are made as necessary. Then, using the first and second Cu-based wiring layers 112 and 114,
Form long-distance signal wiring, power bus wiring, clock wiring, etc. between circuit blocks.

Needless to say, the second Cu-based wiring layer 114 is unnecessary if the wiring formed on the third Al-based wiring layer in FIG. 26A is simply replaced. However, for example, in order to make use of the low resistance of Cu-based wiring for long-distance signal wiring and obtain a high-performance product, two Cu-based wiring layers are provided, and the degree of freedom in forming wiring in directions orthogonal to each other is increased. It is effective to increase. If necessary, three or more Cu-based wiring layers can be provided.
Conversely, in some cases, the use of Cu-based wiring can reduce the number of wiring layers and reduce cost. Specifically, for example, a wiring that requires two wiring layers (for example, third and fourth wiring layers) in a product that does not use Cu-based wiring is replaced with a low-resistance and high electromigration resistance of Cu-based wiring. Assuming that the wiring width is reduced and the wiring density is increased, if the wiring can be formed in one Cu-based wiring layer, the number of wiring layers can be reduced by one.

FIG. 27 schematically shows an example of long-distance signal wiring. A plurality of circuit blocks 118 are arranged in the semiconductor integrated circuit chip 116, and a large number of I / O cells 120 are arranged in a peripheral portion. A long-distance signal wiring 122 is provided for signal transmission between the circuit blocks 118, and a long-distance signal wiring 122 is provided for each circuit block 118 for exchanging signals from outside the semiconductor integrated circuit. 124 are provided. Although each wiring is represented by one line in the figure, for example, 32 wirings are provided to transmit a 32-bit signal.

FIG. 28 schematically shows an example of clock wiring. A plurality of circuit blocks 126 are arranged in the semiconductor integrated circuit chip 116. Further, an oscillation circuit 128 for generating a clock signal is provided at the center of the chip. Clock signals are distributed from the oscillation circuit 128 to the respective circuit blocks 126 via clock wirings 130 provided in a hierarchy. The clock signal is first distributed through a main wiring directly connected to the oscillation circuit, and further distributed to each circuit block through a branch wiring connected to the wiring. In each circuit block, the signal is distributed to individual gate circuits through low-level wiring (not shown). It is particularly effective to use a Cu-based wiring for a high-order portion in such a hierarchical clock wiring. That is, it is a portion that is distributed from an oscillation circuit (or a pad for inputting a clock signal) to a plurality of circuit blocks.

As described above, in the semiconductor integrated circuit of the present invention, the macro cell designed and operation-checked on the premise of the Al-based wiring is used as the Al-based wiring, and the low resistance of the Cu-based wiring is used. By utilizing the high electromigration resistance, a high-performance semiconductor integrated circuit can be realized. Moreover, since the lower wiring layer provided adjacent to the transistor remains the same as the conventional Al-based wiring layer,
It is unlikely that the transistor characteristics will deteriorate due to the diffusion of Cu from the u-based wiring. As a result, the exchangeability of IP can be maintained. That is, for example, the IP developed on the premise of the Al-based wiring can be used for both the product using the Cu-based wiring and the product not using it without making a significant change.

Therefore, as compared with the case where a Cu-based wiring layer is provided in the lower wiring layer, the thickness of the diffusion preventing layer provided for preventing Cu diffusion can be reduced or the diffusion preventing layer can be formed. The process can be simplified.
Further, a test for evaluating the influence of the Cu-based wiring can be simplified. That is, for example, only a test on the effect of Cu diffusion on transistor characteristics may be performed using a limited type of test device in which Cu-based wiring is provided in the third layer. Since the wiring inside the macro cell remains the Al-based wiring, the test on the characteristic change of each macro cell due to the use of the Cu-based wiring can be omitted. In addition, by providing a plurality of Cu-based wiring layers, each of which is mainly used for a specific purpose, the degree of freedom of wiring can be further improved, and the performance of the semiconductor integrated circuit can be improved. In order to form a long-distance signal wiring, it is preferable to provide two layers or an even number of Cu-based wiring layers as a set of two layers in order to mainly form wirings in directions orthogonal to each other.

Of the power supply bus lines, the lower (deep) part of the hierarchy is often formed, for example, also on the lower wiring layer used for connection in a macro cell. It is possible to use the wiring of such a portion as it is, form a wiring substantially parallel to the wiring in a Cu-based wiring layer, and use the wiring electrically electrically. This makes it possible to improve the electromigration resistance, reduce the voltage drop, and stabilize the circuit operation. That is, Cu-based wiring can be used for the purpose of reinforcing Al-based wiring. Further, it is possible to provide a dedicated reinforcing Cu-based wiring for each Al-based wiring, or to provide a common reinforcing Cu-based wiring for a plurality of Al-based wirings. On the other hand, a power bus provided so as to surround a high-level (shallow) portion of a power bus wiring, for example, a peripheral portion of a semiconductor chip for supplying power to all basic cells of a gate array has a particularly long distance.
Since the flowing current is large, the effect of using the Cu-based wiring layer is large. It is also effective to provide separate Cu-based wiring layers for power supply potential (VDD) supply and ground potential (VSS) supply.

FIG. 29 schematically shows an example of power supply bus wiring. FIG. 1 shows three levels of power supply buses provided in a gate array type semiconductor integrated circuit. I / O cells 120 are arranged around the semiconductor integrated circuit chip 116,
Inside, a cell array 132 in which a number of basic cells are arranged vertically and horizontally at regular intervals is provided. The figure shows a power supply bus for supplying power to the cell array. The primary power supply bus 134 is provided so as to surround the entire cell array, and is provided commonly to supply power to a main part of the integrated circuit, that is, all basic cells. It is also possible to provide a separate power bus for other parts of the integrated circuit, for example I / O cells. The tertiary power buses 138 are arranged on the basic cells in the corresponding column, and supply power to the transistors in the basic cells in the column. The secondary power supply buses 136 are provided so as to connect opposite sides of the primary power supply bus, and are connected to the respective tertiary power supply buses. The secondary power bus reduces the impedance between the primary power bus and the tertiary power bus, and serves to reduce the voltage drop when the transistors in a large number of basic cells operate simultaneously.

In a product using Cu-based wiring, of the power supply buses provided in a hierarchical manner as described above, a higher level portion, for example, the primary power supply bus 134 and the secondary power supply bus 13
6 is formed on the Cu-based wiring layer. Alternatively, the power supply bus wiring of the Al-based wiring layer is used as it is, and a reinforcing wiring is formed in the Cu-based wiring layer. On the other hand, a lower part of the hierarchy, for example, the tertiary power supply bus 138 is formed in the Al-based wiring layer. Of course, it is also possible to provide a wiring for reinforcing the tertiary power supply bus 136 in the Cu-based wiring layer. Although only one power supply bus line is shown in FIG.
Two or more power supply buses for supplying a potential and for supplying a VSS potential are provided.

It is also possible to form a required number of layers of Cu-based wiring layers and further form an Al-based wiring layer. For example, as the uppermost wiring, it is preferable to use an Al-based wiring layer that has a proven track record in connection to a package by bonding.

As described above, using the macro cell of the library common to the product not using the Cu-based wiring, the Al-based wiring layer used for the wiring inside the macro cell is used as it is in principle, and 1 Layer or multiple layers of C
By providing a u-based wiring and producing a product using the Cu-based wiring, the following effects can be obtained.

1) It is possible to manufacture a high-performance integrated circuit by using Cu-based wiring in specific portions such as long-distance signal wiring, clock wiring, power supply bus wiring, etc., which can make use of low resistance and high electromigration resistance. it can. 2) The development period and development cost can be reduced by utilizing the properties of the macrocell developed and operation-checked on the premise of Al-based wiring. 3) While maintaining the exchangeability of IP shared with other manufacturers,
In addition, the performance of the entire integrated circuit product can be improved. With the above effects, a high-performance product can be supplied with a short development period and low development cost.

Actually, the type using the Cu-based wiring as described above is prepared as a high-performance grade type to meet the demands of customers who value performance. On the other hand, a type that does not use Cu-based wiring is prepared as a popular grade type to meet the demands of customers who value cost. Then, the macro cell library is shared between the high-performance grade type and the popular grade type. The grades of both grades are made as common as possible except for the Cu-based wiring process (including a groove forming process for the damascene method) and cost reduction is achieved. For example, the process for forming transistors and the layout of basic cells are shared, and the shared process is performed using a common manufacturing line in principle.

When designing a standard grade product,
A required macro cell is selected from the library and placed on a semiconductor integrated circuit chip. A macrocell contains the wiring required for its internal connection. Further, wiring for connection outside the macro cell is formed in the Al-based wiring layer.

Similarly, when designing a high-performance grade product, necessary macro cells are selected from a library and arranged on a chip. Of the interconnections in the macrocell, the portions formed in the interconnection layers below (for example, the first and second layers) are used as they are. That is, the wiring in this portion is formed in one or more Al-based wiring layers. Then, only the portion formed in the upper (for example, third) wiring layer is formed in one or more Cu-based wiring layers.
As a result, the connection in the macro cell is mainly performed by the wiring in the Al-based wiring layer. On the other hand, the connection outside the macro cell is mainly performed by a wiring formed in one or a plurality of Cu-based wiring layers. The wiring outside the macro cell includes a portion where the low resistance and high electromigration resistance of the Cu-based wiring are utilized. For example, long-distance signal wiring between macrocells or between macrocells and I / O cells, power supply bus wiring (particularly, a high-order part of a hierarchically provided power supply bus), clock wiring (particularly, A portion for distributing a clock signal) and the like are formed in the Cu-based wiring layer. As a result, high performance can be achieved despite the use of macrocells selected from a common library with standard grade products. Of course, it is also possible to make some improvements to the macrocell. However, significant changes or redesigns of the macrocell should usually be avoided to reduce development costs.

The above design work is actually performed by CAD (comp
uter aided design) performed on the system. A mask is created based on the design result, and an actual semiconductor integrated circuit is manufactured using the mask.

By using the lower Al-based wiring layer and the upper Cu-based wiring layer in combination as described above, the following effects can be obtained even in a product on the assumption that Cu-based wiring is not used. Can be obtained.

1) The development is performed on the premise of Al-based wiring, and the number of wirings, for example, the number of power supply buses is increased as compared with the estimation at the initial stage, and the number of wirings must be within the predetermined upper limit of the chip size. As a countermeasure in the case where it has been found difficult to use, a Cu-based wiring layer can be used. That is, the wiring layer mainly used for the power supply bus is C
If the wiring width is reduced on the assumption that the Cu-based wiring has low resistance and high electromigration resistance instead of the u-based wiring layer, it may be possible to fit in the intended chip size. Even if the cost of the Cu-based wiring itself is higher than that of the Al-based wiring compared to the case where the package is changed due to the increase in the chip size or the design is re-designed from the beginning to fit in the expected chip size, it is developed. Total costs, including costs, can be reduced.

2) A semiconductor integrated circuit having a certain function is
After development without using Cu-based wiring with emphasis on cost, it is possible to quickly respond when a higher-performance product is required. In other words, the circuit and layout of the first product developed were
A Cu-based wiring layer is added on the system-based wiring layer,
By replacing a higher wiring layer among the system wiring layers with a Cu system wiring layer and forming a wiring having a large influence on characteristics, such as a long-distance signal wiring, in the Cu system wiring layer, it is easy to form the wiring. , The performance can be improved. Of course, if all the Al-based wiring layers are replaced with Cu-based wiring layers and the design is redone on the premise of the use of Cu-based wiring, further improvement in characteristics can be expected. However, this requires a long development period and increases development costs.

As described above, the gate array, the standard cell,
The effect of manufacturing a semiconductor integrated circuit by using a lower Al-based wiring layer and an upper Cu-based wiring layer in combination with an ASIC product such as an embedded cell array has been described. However, it goes without saying that not only ASIC products but also many semiconductor integrated circuits have strong demands for high performance, short development period, and low development cost. Therefore, the combined use of the lower Al-based wiring layer and the upper Cu-based wiring layer is effective in various types of semiconductor integrated circuits.

For example, FPG which is a kind of ASIC product
In an A (field programmable gate array) product, a similar combination of Al-based wiring and Cu-based wiring is effective. The circuit blocks described above can be applied to programmable logic blocks, and long-distance wiring can be applied to programmable wiring between programmable logic blocks and to programmable wiring between programmable logic blocks and I / O cells. That is, the wiring in each programmable logic block is formed mainly using the lower Al-based wiring layer, and the programmable wiring between the programmable logic blocks and between the programmable logic block and the I / O cell is formed on the upper layer. The formation speed using the Cu-based wiring can increase the operation speed of the FPGA in which the distance of such a wiring tends to be long. Similar effects can be obtained by using Cu-based wiring for clock wiring and power supply bus wiring.

FIG. 30 shows a DRAM (Dynamic Radar).
1 schematically shows an example in which a Cu-based wiring is used for a semiconductor integrated circuit in which an ndom access memory and a logic circuit are mounted on the same chip. In the semiconductor integrated circuit chip 116, a DRAM 144 including a memory cell array 140 and a sense amplifier array 142, and a logic circuit block 146 for performing image processing, for example, are arranged. A plurality of data lines 148 are provided for transmitting signals between the DRAM 144 and the logic block 146. In order to perform circuit image processing, a large-capacity memory is required to temporarily record a large amount of data. Further, for example, in order to perform real-time moving image processing, it is necessary to transmit such a large amount of image data between the image processing circuit and the memory in a short time. For such a purpose, it is effective to use a Cu-based wiring having a low resistance.

For cost reduction, the memory cell array 1
40 is desirably manufactured using a common manufacturing process with the memory cell array of a single DRAM product. Normally, at most 2 wires are used for wiring in the memory cell array of a single DRAM.
Uses only one wiring layer. Therefore, by forming the wiring in this portion on the conventional Al-based wiring layer, providing the Cu-based wiring layer thereon, and forming the data wiring 148 on the wiring layer, the common wiring with the manufacturing process of a single DRAM product can be obtained. Can be enhanced. Further, by using an Al-based wiring layer as a low-level wiring layer close to a memory cell that is sensitive to contamination, it is possible to prevent characteristic deterioration due to Cu diffusion. The use of Cu-based wiring for the same data wiring is also effective for transmitting data at high speed between a CPU and a cache memory in a microprocessor, for example.

As described above, products that do not use Cu-based wiring are supplied to customers who require low cost, and products that use Cu-based wiring are supplied only to customers who require high performance. In the case of products using Cu-based wiring, if the Cu-based wiring layer is used only for the upper wiring layer, the production capacity required for the production equipment for forming the Cu-based wiring is based on the use of Cu-based wiring. Small compared to the production capacity required for equipment to produce products. Therefore, for example, a plurality of lines for producing products that do not use Cu-based wiring are prepared, and Cu lines are commonly used for all of them.
It is also possible to provide a production line for forming system wiring. When a new factory is constructed, equipment for forming Al-based wiring and equipment for forming Cu-based wiring are provided.
equipment for forming u-based wiring at the factory, and
It can also be shared with existing factories that do not have facilities for forming Cu-based wiring.

(Embodiment 7) FIGS. 14 (a) to 14 (c), FIG.
In the first-layer interlayer insulating film 32 having the structure shown in FIGS. 5 (d) to (f) and FIG. 16 (g), the low dielectric constant film 28 is formed only in the portion filling the space between the wirings of the first wiring layer 18. Have been.
On the other hand, when the low dielectric constant film is formed not only between the wirings of the first wiring layer 18 but also on the wiring, the second wiring layer 2
The second wiring can be formed by a damascene method. Here, FIG. 18 (a), (b), (c), FIG. 19 (d),
(E), (f), FIGS. 20 (g), (h), (i) and FIG. 21 (j) are cross-sectional views of a seventh embodiment showing respective steps of forming a wiring structure of the present invention. . As shown in FIG. 18A, the first wiring layer 18 is formed in the same manner as in the fourth embodiment, and the low dielectric constant formed between the base film 26, the wiring of the first wiring layer 18 and over the wiring. Film 28 and cap film 3
A first interlayer insulating layer 50 of 0 is formed. Here, the surface of the low dielectric constant film 28 is flattened. Also,
It is assumed that the low dielectric constant film 28 is formed of a material having low resistance to ashing.

Next, as shown in FIG. 18B, a resist pattern 58 corresponding to the via hole is formed, and anisotropic plasma etching using a fluorine-based gas is used to form a resist pattern 58 at a position corresponding to the via hole. The cap film 30 is removed. Subsequently, as shown in FIG. 18C, via holes 60 are formed in the low dielectric constant film 28 by anisotropic etching using oxygen ions. At this time, the cap film 30 functions as a mask.

Next, as shown in FIG. 19D, a low dielectric constant film 62 and a cap film 64 are formed on the entire surface of the substrate in order to form an interwiring insulating layer 66 for insulating between the wirings of the second wiring layer. Are formed in order. For example, a coating method is used to form the low dielectric constant film 62. The low dielectric constant film 62 is also formed in the via hole 60. Since the surface of the first interlayer insulating layer 50 is flattened, the surface of the low dielectric constant film 62 is also almost flattened. Subsequently, as shown in FIG. 19E, a resist pattern 68 corresponding to the groove in which the wiring of the second wiring layer is formed is formed, and the cap is formed by anisotropic plasma etching using a fluorine-based gas. The film 64 is etched.

As shown in FIG. 19F, a groove 70 is formed in the low dielectric constant film 62 by anisotropic etching using oxygen ions. At this time, the over-etching time is set so that the low dielectric constant film 62 formed in the via hole 60 is also removed. The cap film 30 of the first interlayer insulating layer 50 exists at the bottom of the groove 70. Since the fluorinated silicon oxide film forming the cap film 30 is hardly etched by anisotropic etching using oxygen ions, the depth of the groove 70 can be accurately controlled. In addition, since the cap film 30 functions as a mask, it is possible to prevent the via hole from being enlarged when the groove 70 is formed. Further, anisotropic plasma etching using a fluorine-based gas is performed to remove the underlying film 26 of the first interlayer insulating layer 50 exposed at the bottom of the via hole 60, and the wiring of the first wiring layer 18 is removed. Is exposed at the bottom of the via hole 60. At this time, the cap film 30 of the first interlayer insulating layer 50 is formed.
Film 6 of insulating layer 66 between wirings of the second wiring layer
4 is also etched at the same time, so that the film thickness and etching conditions of both are appropriately set. In the figure,
First layer cap film 30 and second layer cap film 64
The example which leaves is shown.

Next, as shown in FIG. 20 (g), via holes 60 are formed in the same steps (damascene method) as in the sixth embodiment.
Then, the plug 74 and the wiring of the second wiring layer 22 are formed in the groove 70.

Thereafter, if necessary, third and subsequent layers of wiring are formed. 20 (h), (i) and FIG.
(J) shows an example of a step of forming a third wiring layer by a damascene method. First, as shown in FIG. 20H, a base film 78 is formed to form an insulating layer (second interlayer insulating layer) 76 for insulating between the second wiring layer 22 and the third wiring layer.
The low dielectric constant film 80 and the cap film 82 are formed in the order of formation. Then, the wiring of the second wiring layer 22 and the wiring of the third wiring layer are connected by the same method as the formation of the via hole 60 for connecting the wiring of the first wiring layer 18 and the wiring of the second wiring layer 22. A via hole 84 for connection is formed.

Subsequently, as shown in FIG.
A low dielectric constant film 88 and a cap film 90 are sequentially formed in order to form an insulating layer 86 that insulates between the wiring layers.
At this time, the low dielectric constant film 88 is also formed in the via hole 84. Then, a groove 92 for forming a third-layer wiring therein is formed in the same manner as the formation of the groove 70 of the second layer. After that, the underlying film 78 of the interlayer insulating layer 76 between the second wiring layer 22 and the third wiring layer, which is exposed at the bottom of the via hole 84, is removed. In the same figure, in the step of removing the underlayer 78,
The example in which the thicknesses of these films and the removal conditions are set such that the cap film 82 at the bottom of the groove 92 and the cap film 90 of the insulating layer 86 between the wires of the third wiring layer remain.

Then, as shown in FIG. 21J, a plug 94 for connecting the wiring of the second wiring layer 22 and the wiring of the third wiring layer 96 to the via hole 84 and the groove 92 by the damascene method. Then, the wiring of the third wiring layer 96 is formed. Thereafter, if necessary, fourth and subsequent wiring layers are formed, a surface protective film and bonding pads are formed, and the wafer manufacturing process of the semiconductor integrated circuit is completed.

In this embodiment, the low dielectric constant films 28, 6
Films of a material having poor resistance to ashing are used as 2, 80, 88, and via holes 60, 84 and grooves 70, 84 are used.
92 is formed by anisotropic etching using oxygen ions using the cap films 30, 64, 82, and 90 as a mask. However, the present invention is not limited to this.
8, 62, 80 and 88 are formed of a material having ashing resistance (for example, siloxane SOG), and via holes 60 and 84 and grooves 70 and 92 are formed by anisotropic plasma etching using a fluorine-based gas with a resist as a mask. It is also possible to form. In this case, the cap films 30, 64,
It is also possible to omit 82 and 90.

In this embodiment, the via holes 60, 84
The grooves 70 and 92 are formed using anisotropic etching using oxygen ions. Since the resist is also etched by the anisotropic etching using oxygen ions, the ashing step for removing the resist pattern is omitted, and the resist pattern is removed in the etching step for forming the via holes 60 and 84 or the grooves 70 and 92. It is also possible to do it at the same time. Thereby, the number of steps can be reduced. For this purpose, the low dielectric constant films 28, 62,
At the time when the etching of 80 and 88 is completed, the removal of the resist is already completed so that the low dielectric constant films 28 and 6 are removed.
It is preferable to set 2,80,88, the thickness of the resist, and the conditions of the plasma etching. Even if the removal of the resist is completed first, the cap films 30, 64, 82, 9
Since 0 exists on the low dielectric constant films 28, 62, 80, and 88 and functions as a mask, the dimensional accuracy of the via holes 60 and 84 and the grooves 70 and 92 does not deteriorate.

In this embodiment, the via holes 6
The surface of the substrate is flattened both when forming 0 and 84 and when forming the grooves 70 and 92. Therefore, even if the film thickness of the resist for forming the resist patterns 58, 68 and the like is reduced, it is possible to apply the resist uniformly. By reducing the resist film thickness, the step of simultaneously etching the via holes 60 and 84 and the grooves 70 and 92 and removing the resist as described above is facilitated, and the resolution can be improved. For example, it is easy to reduce the resist film thickness to about 0.5 μm or less.
It is also possible to reduce the thickness to about 3 μm or less. Since the removal of the resist has already been completed when the etching of the low dielectric constant film is completed, the thickness of the low dielectric constant film to be etched, that is, the via hole 60,
The depth of the via hole when forming 84, and the depth of the groove and the depth of the via hole when forming the grooves 70 and 92, are about the same or less, preferably about 70% or less, and more preferably about 70% or less. It should be about 50% or less, most preferably about 30% or less.

In this embodiment, the via hole 6 is formed in the low dielectric constant film 28 except for the base film 26 of the first interlayer insulating layer 50.
0 is formed, and then, when forming the groove 70 in the insulating layer 66 between the wirings of the second wiring layer 22, the base film 26 at the bottom of the via hole 60 is removed. However, the low dielectric constant film 28 of the first layer
Following formation of the via hole 60, the base film 26 at the bottom of the via hole 60 can be removed by anisotropic plasma etching using a fluorine-based gas.

In the present embodiment, the cap film 64 is left on the surface of the insulating layer 66 between the wirings of the second wiring layer 22. However, the present invention is not limited to this.
Via holes 6 for connecting the wiring of the second wiring layer 22 and the wiring of FIG.
It is also possible to remove the cap film 64 between the wires of the second wiring layer 22 when removing the base film 26 at the bottom of 0. By removing the cap film 64 between the wires of the second wiring layer 22, it is possible to further reduce the capacitance between the wires of the second wiring layer 22. In this case, the second wiring layer 2
The CMP conditions for forming the second wiring are appropriately set,
Care must be taken not to cause scratches on the surface of the low dielectric constant film 62. When the base film 26 at the bottom of the via hole 60 is removed, conditions for setting the cap film 64 between the wirings of the second wiring layer 22 are set, and the wiring of the second wiring layer 22 is formed. After the completion of the CMP, the cap film 64 can be removed by changing the conditions. At least in this case, the cap film 64 may be formed of a material having a low CMP rate, such as silicon nitride. Cap film 6 made of such a material
4 is used as an etching stop layer of CMP for forming the second wiring layer 22, so that a scratch is generated on the surface of the low dielectric constant film 62 even when the amount of over-etching is increased due to variation in process conditions. It is possible to prevent that. Although silicon nitride has a higher dielectric constant than a silicon oxide film, it does not lead to an increase in capacitance between wirings if it is removed by changing the CMP conditions after it is used as an etching stop layer.

Further, in this embodiment, after forming a via hole 60 in the first interlayer insulating layer 50, an insulating layer 66 between the wirings of the second wiring layer 22 is formed, and the insulating layer 66 between the wirings is formed.
However, the present invention is not limited to this. Conversely, for example, the groove
It is also possible to form the via holes 60 in the first interlayer insulating layer 50 after forming 0. FIG. 22 is a cross-sectional view of one embodiment showing each step of forming the wiring structure of the present invention in this case.
(A), (b) and (c) and FIGS. 23 (d) and (e). First, as shown in FIG. 22A, in the same process as that of the fourth embodiment, the first wiring layer 18 and the lower film formed between the wiring of the base film 26 and the first wiring layer 18 and on the wiring are formed. A dielectric film 28 and a first interlayer insulating layer 50 made of a cap film 30 are formed. Thereafter, on this interlayer insulating layer 50, a low dielectric constant film 62 and a cap film 64 constituting an inter-wiring insulating layer 66 for insulating between wirings of the second wiring layer are formed.

Next, as shown in FIG. 22B, a resist pattern corresponding to the groove in which the wiring of the second wiring layer is to be formed is formed, and anisotropic plasma etching using a fluorine-based gas is performed. Thus, an opening is formed in the cap film 64, and a groove 70 is formed in the low dielectric constant film 62 by anisotropic plasma etching using oxygen ions.

Next, as shown in FIG. 22C, a resist pattern 98 corresponding to the via hole is formed, and a portion corresponding to the via hole is formed by anisotropic plasma etching using a fluorine-based gas. The cap film 30 of the one interlayer insulating layer 50 is removed. Subsequently, as shown in FIG. 23D, the low dielectric constant film 28 is etched by anisotropic etching using oxygen ions, and anisotropic plasma etching is performed using a fluorine-based gas to form a base film. 26
Is removed to form a via hole 60.

Then, as shown in FIG. 23E, a via plug 74 for connecting the wiring of the second wiring layer 22 and the wiring of the first wiring layer 18 to the wiring of the second wiring layer 22 is formed by a damascene method. I do. Thereafter, if necessary, a third and subsequent wiring layers are formed, a surface protective film and bonding pads are formed, and the wafer manufacturing process of the semiconductor integrated circuit is completed.

In the embodiment described above, the low dielectric constant film 28 of the first interlayer insulating layer 50 is exposed on the side wall of the via hole 60 and the low dielectric constant
Are exposed on the side walls of the groove 70. Then, a metal film for forming the wiring of the second wiring layer 22 and the plug 74 connecting the first and second wiring layers is deposited in the via hole and the groove. As a result, the plug 74 contacts the low dielectric constant film 28 exposed on the side wall of the via hole 60, and the wiring of the second wiring layer 22 contacts the low dielectric constant film 62 exposed on the side wall of the groove 70. Similarly, the plug 94 connecting the second and third wiring layers contacts the low dielectric constant film 80 of the second interlayer insulating layer on the side wall of the via hole 84, and the wiring of the third wiring layer is formed on the side wall of the groove 92. At a low dielectric constant film 88 of the third inter-wiring insulating layer. However, depending on the material and the process conditions, the low dielectric constant film may adversely affect the plug and the wiring. For example, the low dielectric constant film may contain a large amount of moisture. In such a case, it is preferable that the plug and the wiring are not brought into direct contact with the low dielectric constant film.

FIGS. 24 (a), 24 (b) and 24 (c) are cross-sectional views showing steps of forming a wiring structure in which the plug and the wiring do not directly contact the low dielectric constant film. First, by a process similar to that of the already described embodiment, the first wiring layer 18, the base film 26, between the wirings, and on the wirings, for example, as shown in FIG. 19 (f) or FIG. 23 (d). Low dielectric constant film 2
8 and a first interlayer insulating layer 50 including a cap film 30;
A structure having a second inter-wiring insulating layer 66 composed of a low dielectric constant film 62 and a cap film 64, a via hole 60 formed in the first interlayer insulating layer 50, and a groove 70 formed in the second inter-wiring insulating layer 66. Form. Next, as shown in FIG. 24A, a coating film 71 made of, for example, a fluorinated silicon oxide film is used.
Is deposited on the substrate surface including the sidewalls of the via hole 60 and the groove 70. The coating film 71 is deposited by, for example, a high-density plasma CVD method using a substrate bias.

Subsequently, the via holes 60 are formed by anisotropic plasma etching using a fluorine-based gas atmosphere, for example.
Etchback is performed so that the coating film 71 is removed at the bottom of the groove 70. As a result, as shown in FIG. 24B, a sidewall film 73 is formed on the sidewall of the groove, and a sidewall film 75 is formed on the sidewall of the via hole 60. The side wall film 73 covers the low dielectric constant film 62 exposed on the side wall of the groove 70. The side wall film 75 covers the low dielectric constant film 28 exposed on the side wall of the via hole 60.

Next, as shown in FIG. 24C, a plug 74 is inserted into the via hole 60 by the damascene method, and the groove 70 is formed.
The wiring 22 is formed therein. In this structure, since the side walls of the via hole 60 and the groove 70 are covered with the side wall films 73 and 75, the plug and the wiring do not contact the low dielectric constant films 28 and 62. By repeating such a process, the third layer having the side wall film on the side wall of the via hole and the groove and the subsequent wiring layer can be formed.

In this embodiment, a coating film is deposited by a high-density plasma CVD method using a substrate bias, and an anisotropic etch back is performed to form a sidewall film. Therefore, even when the side walls of the via hole 60 and the groove 70 are formed almost vertically, the surface of the side wall film has a substantially uniform forward direction over almost the entire region excluding the vicinity of the corner at the upper end. It has a slope. Stated another way, the thickness of the sidewall film is smaller at the upper portion of the sidewall than at the lower portion except for the vicinity of the corner at the upper end. By this forward inclination, the embedding property of the metal film in the via hole 60 and the groove 70 is improved, and the metal film can be satisfactorily embedded even when the via hole and the groove become fine. In order to obtain a sufficient burying property improving effect, the high-density plasma CVD and the high-temperature plasma should be inclined so that the forward inclination is about 2 ° or more, preferably about 4 ° or more, more preferably about 6 ° or more with respect to the vertical plane. Set the conditions for anisotropic etchback. However, it is not preferable to make this angle too large. For example, above about 8 °, a significant portion of the via hole or trench becomes occupied by the sidewall film, reducing the volume that can be embedded with the metal film.

Such a forward-inclined side wall film has a particularly remarkable effect of improving the burying property depending on the method of depositing the metal film. On a sidewall film having a forward inclination formed by using a high-density plasma CVD method using such a substrate bias together, for example, by ionization sputtering, titanium /
A diffusion preventing layer such as titanium nitride, titanium nitride, tantalum, tantalum nitride, and tungsten nitride can be deposited thinly and uniformly. This is because both the high-density plasma CVD method and the ionization sputtering method use ions accelerated by the substrate bias. The ionization sputtering method can also be suitably used when depositing a thin copper film on the diffusion preventing layer. This thin copper film can be used as a nucleation layer for depositing a thick copper film for filling via holes and grooves by plating. Similarly, a nucleation layer is required when another low resistance metal film, for example, a gold film is deposited by a plating method.

In this embodiment, the high-density plasma CV
The sidewall film is formed by the coating film deposited by using the D method. The silicon oxide film deposited by the high-density plasma CVD method can be used in another method, for example, a normal plasma CVD method.
It has a higher effect of suppressing moisture diffusion than a film deposited by the method. Further, as described above, when the amount of added fluorine is limited to a range where Si (-F) ₂ bonds are not substantially contained, the effect of suppressing water diffusion is further improved by adding fluorine. Therefore, it is possible to reduce the thickness of the side wall film while keeping the effect of suppressing the diffusion of water from the low dielectric constant film in a necessary range. As a result, the ability to embed the metal film in the fine via holes 60 and the grooves 70 can be enhanced. For example, the thickness of the side wall film above the via hole or the groove (near the upper surface of the low dielectric constant film) can be reduced to about 15 nm or less. Depending on the conditions, it is about 10 nm or less,
It is also possible to make it about 5 nm or less.

In this embodiment, the side wall film is formed of a fluorinated silicon oxide film having a dielectric constant lower than that of the silicon oxide film. For this reason, the capacitance between wirings can be reduced more effectively than when the side wall film is formed of a material having a higher dielectric constant, such as a silicon oxide film or a silicon nitride film. In this embodiment, sidewall films are formed on the sidewalls of the via hole 60 and the groove 70 at the same time. That is, a coating film is deposited on both the via hole and the groove, and anisotropic etchback is performed to form a sidewall film. However, it is also possible to form the sidewall film of the via hole in a step different from that of the trench. In some cases, it is also possible to form a sidewall film on only one of the via hole and the groove.

In this embodiment, after the covering film 71 is formed by the high-density plasma CVD method using the substrate bias, the sidewall films 73 and 75 are etched back.
Is formed. As a result, the following effects can be obtained. 1) By forming the side wall film inclined in the forward direction, the embedding property of the metal film into the via hole and the groove can be improved. 2) The side wall film can be thinned while ensuring a sufficient effect of suppressing moisture diffusion. As a result, the embedding property of the metal film into the via hole and the groove can be improved. 3) A sidewall film having a low dielectric constant can be formed. As a result, the capacitance between the wirings can be effectively reduced.

However, in order to obtain the effects 1) and 2), films made of other various materials can be used. For example, the covering film 71 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. Such a film is preferably deposited by a high-density plasma CVD method using a substrate bias.

(Embodiment 8) FIGS. 25 (a), 25 (b), and
(C) is sectional drawing of 8th Example showing each formation process of the wiring structure of this invention. As shown in FIG. 25 (a), in the same manner as in the fourth embodiment, the first insulating layer 12 including the wirings 18a, 18b and 18c is formed on the underlying insulating layer 12 on the semiconductor substrate 10.
The wiring layer 18 is formed. A portion having a thickness d1 on the surface of the base insulating layer 12 between the wires of the first wiring layer 18 has been removed.
Subsequently, a base film 26 is formed, a solution containing, for example, a fluorinated polyimide precursor is applied, and curing is performed by heating to form a fluorinated polyimide film. Further, flattening is performed to bury the space between the wirings of the first wiring layer 18, and the low dielectric constant film 2 in which the portion of the film thickness t3 is left on the wiring.
8 is formed. The thermal conductivity of the low dielectric constant film 28 made of fluorinated polyimide is about 0.24 W / mK at room temperature, and the thermal conductivity of the silicon oxide film (1.4 at room temperature).
(W / mK). Note that the thickness of the low dielectric constant film 28 on the wiring of the first wiring layer 18 is the same as that of the fourth embodiment.
Thinner than in the case of Further, the distance between the wirings of the first wiring layer 18 is s1, and the thickness of the base film 26 on the upper surface of the wiring is t2.

Next, as shown in FIG. 25B, a silicon nitride film having a thickness of t4 is deposited by, for example, a plasma CVD method to form a heat conductive insulating film 100. The thermal conductivity of silicon nitride at room temperature is about 19 W / mK, which is about 14 times higher than the thermal conductivity of a silicon oxide film. Such a film of an insulating material having a higher thermal conductivity than a silicon oxide film is hereinafter referred to as a “thermally conductive insulating film”. Subsequently, a second low dielectric constant film 102 is formed, and for example, a fluorinated silicon oxide film is deposited to form a cap film 30. The thickness of each of the second low dielectric constant film 102 and the cap film 30 is t.
5, t6. Through the above steps, the interlayer insulating layer 104 including the base film 26, the low dielectric constant film 28, the heat conductive insulating film 100, the second low dielectric constant film 102, and the cap film 30 is formed.

Subsequently, via holes are formed in the interlayer insulating layer 104, and plugs are formed (not shown). Further, if necessary, the same steps are repeated to form the second and subsequent wiring layers and interlayer insulating layers. FIG. 25C is a cross-sectional view showing a state where the second wiring layer 22 is formed. Thereafter, a surface protection film is formed, bonding pads are formed, and the wafer manufacturing process of the semiconductor integrated circuit is completed.

For example, in the wiring structure of the fourth embodiment, most of the interlayer insulating layer 50 is formed of a low-dielectric-constant material film having low thermal conductivity. In such a structure, it has been pointed out that in an electromigration test, the wiring temperature during the test increases due to Joule heat generated in the wiring, and electromigration failure occurs in a short time (for example, K. Banerjee et al., International Elec
tron Devices Meeting, Digest of Technical Papers
(1996) p. 65). On the other hand, in the wiring structure of the present embodiment, a part of the interlayer insulating layer is formed of a heat conductive insulating film made of silicon nitride, and the Joule is diffused by the heat diffusion through the heat conductive insulating film. Since the local rise in the wiring temperature due to heat generation is reduced, the reliability of the wiring is improved.

Here, in order to enhance the effect of reducing the local temperature rise, it is preferable to form the heat conductive insulating film 100 at a position near the wiring of the first wiring layer 18. On the other hand, in order to reduce the capacitance between the wires of the first wiring layer 18, it is preferable to separate the heat conductive insulating film 100 from the wires. This is because the dielectric constant of silicon nitride is high (about 7.5). In reality, the length of the wiring that generates Joule heat is almost of the order of 100 μm or more in most cases, whereas the wiring of the first wiring layer 18 and the heat conductive insulating film 1
00 (that is, the distance from the upper surface of the wiring of the first wiring layer 18 to the lower surface of the thermally conductive insulating film 100 measured in a direction perpendicular to the semiconductor substrate 10 = t2 + t3) is at most on the order of 1 µm. . Therefore, in practice, the importance of the distance between the heat conductive insulating film 100 and the wiring of the first wiring layer 18 is small in the effect of reducing the local temperature rise. Therefore, the distance between the heat conductive insulating film 100 and the wiring of the first wiring layer 18 should be determined with emphasis on the effect on the capacitance between the wirings. Specifically, (t2
+ T3) is about 20% or more of s1, preferably about 5%.
It is better to choose 0% or more. (T5 + t6) is s1
It is good to select about 20% or more, preferably about 50% or more with respect to 1.

In order to reduce the capacitance between the wiring layers, it is preferable that (t3 + t5) is large. Specifically, if (t3 + t5) is made equal to or greater than the larger of s1 and s11, and preferably about twice or more,
The influence of the capacitance between the wiring layers is smaller than the influence of the capacitance between the wirings in the same wiring layer. Further, the thickness of the heat conductive insulating film 100 is preferably large in order to enhance the effect of reducing a local temperature rise. However, if the thickness is too large, the aspect ratio (the ratio between the depth and the opening size) of the via hole connecting the wiring layers increases, and the connection yield decreases. In reality, it is better to be equal to or more than (t2 + t3), preferably about twice or more.

In this embodiment, the heat conductive insulating film 10
Although a silicon nitride film was used as 0, the present invention is not limited to this. For example, an aluminum oxide (alumina) film can be used. Alumina is 21W / mK at room temperature
And about 15 times the thermal conductivity of the silicon oxide film. In addition, use a film of a material having a higher thermal conductivity than a silicon oxide film, preferably a film of a material having a thermal conductivity of about 3 times or more, preferably about 5 times or more as compared with a silicon oxide film. Good to do. Further, a remarkable effect can be obtained when the thermally conductive insulating film 100 is formed using a material having a thermal conductivity that is about 10 times or more that of a silicon oxide film.

In this embodiment, the example in which the low dielectric constant film 28 is formed of fluorinated polyimide is shown, but the present invention is not limited to this, and various other low dielectric constant materials can be used. It is. The thermal conductivity of these materials differs depending on the material, but is often lower than that of the silicon oxide film. The effect of the present invention is that a low dielectric constant film 2 is formed by using a material having a thermal conductivity of about 1/3 or less as compared with a silicon oxide film.
This is remarkable when 8,102 are formed. 1/5 more
Particularly remarkable effects can be obtained when a material having a thermal conductivity of the order of magnitude or less is used.

As described above, the wiring structure of the present invention, the method of forming the wiring structure, and the semiconductor integrated circuit to which the wiring structure is applied have been described in detail. However, the present invention is not limited to the above-described embodiment. Of course, various improvements and changes may be made without departing from the spirit of the invention.

[0191]

As described in detail above, the wiring structure and the method of forming the wiring structure of the present invention basically determine the height of the upper surface of the first insulating layer between the wirings of the wiring layer. And a second insulating layer including a low dielectric constant film is formed between the lower region of the first insulating layer and the wiring of the wiring layer. Therefore, according to the wiring structure and the method of forming the wiring structure of the present invention, the spread of the electric field between the wirings is limited in the low dielectric constant second insulating layer, and the effective dielectric constant between the wirings is reduced by the second insulating layer. Since the value can be reduced to a value close to the dielectric constant, the capacitance between wirings can be effectively reduced, and the semiconductor device can operate at high speed. According to the wiring structure and the method of forming the wiring structure of the present invention, the thickness of the base film between the wiring of the wiring layer and the low dielectric constant film is larger at the upper end of the side surface of the wiring than at the lower end. Even if the space between the wirings becomes fine by forming the wiring thinner, the space between the wirings can be satisfactorily buried with a low dielectric constant film. The capacitance between the wiring layers and between the wiring layers can be more effectively reduced. Furthermore, according to the wiring structure and the method of forming the wiring structure of the present invention,
By forming a thermally conductive insulating film on the low dielectric constant film, it is possible to reduce a local rise in the wiring temperature due to the generation of Joule heat and to prevent the occurrence of defects such as electromigration. Can be improved in reliability. Further, the semiconductor integrated circuit of the present invention to which the wiring structure of the present invention is applied has at least two or more wiring layers, and at least one of the lower wiring layers has A
Apply l-system wiring, and select at least one of the upper wiring layers.
One wiring layer is a copper-based wiring layer. Therefore, according to the semiconductor integrated circuit to which the wiring structure of the present invention is applied, A
A semiconductor integrated circuit capable of high-speed operation can be realized with a short development period and low development cost by making use of assets such as a macro cell developed by using l-system wiring and reducing the wiring resistance by copper-based wiring. There is an effect that it can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a conventional wiring structure.

FIG. 2 is a cross-sectional view illustrating another example of a conventional wiring structure.

FIGS. 3A, 3B and 3C are cross-sectional views of a first embodiment showing respective steps of forming a wiring structure of the present invention.

FIGS. 4D and 4E are cross-sectional views of a first embodiment showing respective steps of forming a wiring structure according to the present invention.

FIGS. 5A, 5B, and 5C are cross-sectional views of a second embodiment showing respective steps of forming a wiring structure according to the present invention.

FIGS. 6 (d), (e) and (f) are cross-sectional views of a second embodiment showing respective steps of forming a wiring structure of the present invention.

FIGS. 7A, 7B and 7C are cross-sectional views of a third embodiment showing respective steps of forming a wiring structure according to the present invention.

FIGS. 8 (d), (e) and (f) are cross-sectional views of a third embodiment showing respective steps of forming a wiring structure of the present invention.

FIG. 9 (g) is a cross-sectional view of a third embodiment illustrating each step of forming a wiring structure according to the present invention.

FIGS. 10A, 10B, and 10C are cross-sectional views of a fourth embodiment showing respective steps of forming a wiring structure of the present invention.

FIG. 11D is a cross-sectional view of the fourth embodiment illustrating each step of forming the wiring structure of the present invention.

FIGS. 12A, 12B, and 12C are cross-sectional views of a fifth embodiment showing respective steps of forming a wiring structure according to the present invention.

FIG. 13D is a cross-sectional view of the fifth embodiment illustrating each step of forming the wiring structure of the present invention.

FIGS. 14A, 14B, and 14C are cross-sectional views of a sixth embodiment illustrating respective steps of forming a wiring structure of the present invention.

FIGS. 15 (d), (e) and (f) are cross-sectional views of a sixth embodiment showing the steps of forming a wiring structure according to the present invention.

FIG. 16 (g) is a cross-sectional view of a sixth embodiment illustrating each step of forming the wiring structure of the present invention.

FIG. 17 is a cross-sectional view of one embodiment illustrating a step of forming a wiring structure according to the present invention.

FIGS. 18 (a), (b) and (c) are cross-sectional views of a seventh embodiment showing steps of forming a wiring structure according to the present invention.

FIGS. 19 (d), (e) and (f) are cross-sectional views of a seventh embodiment showing respective steps of forming a wiring structure of the present invention.

FIGS. 20 (g), (h), and (i) are cross-sectional views of a seventh embodiment showing respective steps of forming a wiring structure of the present invention.

FIG. 21J is a cross-sectional view of the seventh embodiment illustrating each step of forming the wiring structure of the present invention.

FIGS. 22 (a), (b), and (c) are cross-sectional views of another embodiment showing respective steps of forming a wiring structure of the present invention.

FIGS. 23 (d) and (e) are cross-sectional views of another embodiment showing respective steps of forming a wiring structure of the present invention.

24 (a), (b), and (c) are cross-sectional views of still another embodiment illustrating respective steps of forming a wiring structure of the present invention.

FIGS. 25 (a), (b) and (c) are cross-sectional views of an eighth embodiment showing respective steps of forming a wiring structure according to the present invention.

FIGS. 26A and 26B are cross-sectional views schematically showing examples of a wiring layer configuration of a product that does not use Cu-based wiring and a product that uses Cu-based wiring, respectively.

FIG. 27 is a schematic diagram illustrating an example of a long-distance signal wiring.

FIG. 28 is a schematic diagram illustrating an example of a clock wiring.

FIG. 29 is a schematic diagram illustrating an example of a power supply bus wiring.

FIG. 30 is a schematic diagram showing an example in which Cu-based wiring is used for a semiconductor integrated circuit in which a DRAM and a logic circuit are mounted on the same chip.

[Explanation of symbols]

10, 210 Semiconductor substrate 12, 212 Base insulating layer 14, 72 Metal film 16, 54, 58, 68, 98 Resist pattern 18, 22, 96, 218 Wiring layer 18a, 18b, 18c, 22a, 22b, 22c, 2
18a, 218b, 218c Wiring 20, 24, 32, 40, 44, 48, 50, 52, 5
6, 76, 104, 220 Interlayer insulating layer 26, 34, 78, 216 Underlayer 28, 36, 62, 80, 88, 102, 228 Low dielectric constant film 30, 38, 64, 82, 90 Cap film 42, 46 Silicon oxide film 60, 84 Via hole 66, 86 Insulating layer 70, 92 Groove 71 Covering film 73, 75 Side wall film 74, 94 Plug 100 Thermal conductive insulating film 106, 108, 110 Al-based wiring layer 112, 114 Cu-based Wiring layer 116 Semiconductor integrated circuit chip 118, 126 Circuit block 120 I / O cell 122, 124 Long distance signal wiring 128 Oscillation circuit 130 Clock wiring 132 Cell array 134, 136, 138 Power supply bus 140 Memory cell array 142 Sense amplifier array 144 DRAM 146 Logic Circuit block 148 Data wiring 229 void

Claims (7)

[Claims] 1. A wiring structure applied to a semiconductor integrated circuit, comprising: a first insulating layer formed on a semiconductor substrate;
A wiring layer including at least one adjacent wiring, and a low dielectric constant film formed between at least one adjacent wiring of the wiring layers and having a lower dielectric constant than a silicon oxide film. A height of a bottom surface of the second insulating layer formed between the adjacent wirings is higher than a height of a bottom surface of the adjacent wirings.
A wiring structure characterized by being formed at least 20% lower than the interval between adjacent wirings. 2. The wiring structure according to claim 1, wherein the second insulating layer is provided between a wiring of the wiring layer and the low dielectric constant film, and at least an upper surface of the adjacent wiring. And a base film formed on the side surface, wherein the base film is formed such that a film thickness at an upper end portion of a side surface of the adjacent wiring is smaller than a film thickness at a lower end portion. 3. The wiring structure according to claim 1, wherein said low dielectric constant film is also formed on said adjacent wiring, and said second insulating layer further comprises said low dielectric constant film. A wiring structure, comprising: a heat conductive insulating film formed on the film; wherein the heat conductive insulating film has a higher thermal conductivity than a silicon oxide film. 4. A method for forming a wiring structure applied to a semiconductor integrated circuit, comprising: forming a first insulating layer on a semiconductor substrate; and forming at least one adjacent layer on the first insulating layer. Forming a wiring layer including wiring, and forming 20% of the distance between the adjacent wirings on the upper surface of the first insulating layer formed between the adjacent wirings;
After removing the region having the above thickness, a second insulating layer including a low dielectric constant film having a dielectric constant lower than that of a silicon oxide film is formed at least between wirings adjacent to the wiring layer. Method for forming a wiring structure. 5. The method for forming a wiring structure according to claim 4, wherein, when forming the second insulating layer, before forming the low dielectric constant film, further, an upper surface of the adjacent wiring. And forming a base film on the side surface such that the film thickness at the upper end portion of the side surface of the adjacent wiring is smaller than the film thickness at the lower end portion, and thereafter, on the base film and at least the wiring layer Forming the low dielectric constant film between adjacent wirings. 6. The method for forming a wiring structure according to claim 4, wherein said low dielectric constant film is formed also on said adjacent wiring when said second insulating layer is formed. Forming a heat conductive insulating film having a higher thermal conductivity than that of the silicon oxide film. 7. At least two wiring layers, wherein at least one of the lower wiring layers is aluminum or aluminum to which the wiring structure according to claim 1 is applied. An aluminum-based wiring layer mainly composed of an alloy; at least one of the upper wiring layers is a copper-based wiring layer mainly composed of copper or a copper alloy; Wherein at least one of a long-distance signal wiring, a clock wiring, and a power supply bus wiring is formed using the semiconductor integrated circuit.