JPH1185824A - Hierarchy description method for control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To describe higher-order blocks in a simple and easy-to-see state. SOLUTION: At the time of describing hierarchical macros 112a and 112b with a same function in higher-order block graphics 11b and 11c, the same input signal 23 and output signal 24 are described as a name in the input/output terminal of each macro. When the macros 112a and 112b use the medium-order block graphic 12b in common, the same signals 23 and 24 as the macros 112a and 112b in the graphic 12b. When large macros 111a and 111b belonging to the graphic 12b are provided with the same function and both of the use a low-order bloc graphic 13b, the names of the same input and output signals 25 and 26 as the macros 111a and 111b in the graphic 13b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of describing a hierarchy of a control circuit, and more particularly to a control circuit suitable for describing the components of the control circuit described in order to create a control device program in a hierarchical manner. The hierarchical description method.

[0002]

2. Description of the Related Art The functions of a program of a control device are expressed in the form of a control circuit diagram (hereinafter, referred to as a block diagram) described using various means. The description method of this block diagram is described in, for example,
As described in Japanese Patent Application Laid-Open No. 271840 and Japanese Patent Application Laid-Open No. 8-76819, a high-order symbol expressed by a symbol (hereinafter, referred to as a macro) collectively characterizing a group of control functions constituting a control circuit. There is known a hierarchical description method including a block diagram and a lower block diagram in which a detailed circuit of a macro is described. Also, a technique has been realized in which a macro and a lower-order block diagram are made into parts and registered, and these are reused. Hierarchical description methods have been widely used mainly in the field of control that mainly performs process processing. For example, various processes and their conditions are organized in a tree structure such as a large process-middle process-small process. Thus, it is possible to provide a form that is easy for a designer or a user to approach in creating a drawing or understanding the functions of elements created in the drawing.

[0003]

However, in the conventional hierarchical description method, the macro and the lower block diagram are in one-to-one correspondence.
And a description method in which there are as many lower-level block diagrams as there are macros, or a description method in which the lower-level block diagrams are used in common, is adopted. And the output point information are made to correspond with each other, so that the correspondence between the layers is performed. Therefore, even if the input / output point information differs even at one point depending on the purpose of the application circuit even if the control functions are similar, Macros and lower-level block diagrams must be created separately.

As a result, in the conventional hierarchical description method, the type and number of drawings are increased, input / output point information in the lower block diagram is entirely described in the upper macro, and the upper block diagram is complicated and the upper block is complicated. There is a problem that the functions of the elements shown in the figure are difficult to understand.

An object of the present invention is to provide a hierarchical description method of a control circuit capable of expressing a block diagram simply and easily.

[0006]

In order to achieve the above object, the present invention divides the components of the control circuit into a plurality of layers by their functions, and associates the functions of the elements of each layer with each layer. The symbolized mark is set for each element, and the marks of the elements belonging to the highest level are described in the highest level block diagram corresponding to the highest level, and the functions belonging to the levels lower than the highest level are functioned. In each case, the minimum mark is described in the lower block diagram corresponding to each layer, and the name of each function is described in the mark of the element belonging to the highest layer,
In addition, the same mark describes the same name for each function, and the mark of the element belonging to the hierarchy lower than the highest level is the mark of the element whose function is mutually related among the elements belonging to the highest level. Hierarchical description method of control circuit that describes the names of mutually related names or the names of mutually related elements that are related to each other or the elements that belong to layers higher than their own layer. It is.

Further, the present invention includes a control logic for actually operating the contents described in the block diagram, and divides the components of the control circuit into a plurality of layers by their functions, and Mark each element with a mark that symbolizes the function of the element in each level, and mark the marks of the elements belonging to the highest level in the top-level block diagram corresponding to the highest level. For the elements belonging to the lower layer, the minimum mark for each function is described in the lower block diagram corresponding to each layer, the name of the element belonging to the highest layer is described for each function, and the same mark is written. The mark of the same name is described for each function in the mark, and the mark of the element belonging to the hierarchy lower than the highest level is mutually different from the mark of the element whose function is related among the elements belonging to the highest level. Related names Or, for each function, a mark of an element whose function is related to each other among elements belonging to a layer higher than the own layer is described for each function, and a plurality of the same mark exists in the same layer. When a plurality of elements on the upper side share the elements belonging to a layer lower than this layer, a plurality of elements on the upper side set a control logic that switches and uses the common element on the lower side according to the name. The description method is adopted.

In adopting the hierarchical description method of each control circuit, the following elements can be added.

(1) Marks of elements belonging to the highest hierarchy are described in the top block diagram together with signal terminal groups and signal line groups, and marks of elements belonging to the lower hierarchy from the top are shown in the lower block diagram. It is described together with the signal terminal group and the signal line group.

(2) The mark of the element belonging to the highest hierarchy is described in the top block diagram together with the input / output terminal group and the signal line group, and the mark of the element belonging to the lower hierarchy from the top is shown in the lower block diagram. Are described together with the input / output terminal group and the signal line group.

(3) The mark of the element belonging to the highest hierarchy is described in the top block diagram together with the specific signal terminal and the specific signal line, and the mark of the element belonging to the hierarchy lower than the top is described in the lower block diagram. A mark is described together with a signal terminal group and a signal line group, a name is described in a specific mark among elements belonging to the highest hierarchy, and the same name is described in the same mark among the specific marks.

(4) When describing a name on a mark,
Describe the terminal name or signal name in the input / output terminal of the mark.

(5) When describing a name on a mark,
The terminal name or signal name is described in the signal terminal of the mark.

(6) When describing a name on a mark,
A terminal name or a signal name is described in a signal terminal or an input / output terminal of a specific mark.

(7) Instead of the upper plurality of elements switching among the lower common elements according to their names, the upper plurality of elements replace the lower common elements with the terminal names or signal names. Set the control logic to switch to each other.

(8) In the lower block diagram, in place of a specific signal terminal and a signal terminal and a signal line deviating from a specific signal line, a mark of an element belonging only to the lower hierarchy from the highest level is marked with another element. Describe in association with the mark.

(9) In the lower block diagram, in place of a specific input / output terminal or a signal terminal or a signal line deviating from a specific signal line, a mark of an element belonging only to the lower hierarchy from the highest level is added to another mark. Describe in association with the element mark.

(10) In the vicinity of a mark of an element belonging to the highest hierarchy, a mark and an identification name are described as a signal output destination terminal indicating a signal output destination, and a signal input source terminal indicating a signal input source is provided. Describe the mark and identification name, describe the signal output destination identification name and the signal input source identification name indicating the input source of the signal, and, near the mark of the element belonging to the hierarchy lower than the highest level, A signal output destination terminal described in the vicinity of a mark of an element belonging to the hierarchy and its mark and identification name are described as lower signal input source terminals correlated with each other, and a vicinity of the mark of an element belonging to the highest hierarchy. The mark and the identification name are described as the lower signal output destination terminals correlated with the signal input source terminal described in (1).

(11) A plurality of identical signal output destination terminals and signal input source terminals exist near a plurality of marks belonging to the same hierarchy, and the plurality of signal output destination terminals and signal input source terminals are lower than this hierarchy. The logic that shares the lower signal input source terminal and the lower signal output destination terminal described near the mark of the element belonging to the upper hierarchy is such that the upper multiple signal output destination terminals and the signal input source terminal are lower The control logic used by mutually switching the common lower signal input source terminal and lower signal output destination terminal according to the identification name of the terminal is set.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which a configuration of a block diagram created by a hierarchical description method of a control circuit and information on the block diagram are inputted and a processing result is displayed. FIG. 2 is a configuration diagram showing a relationship with a programming tool.

In FIG. 1, when a program for the control device is generated, information relating to a control circuit constituting the control device is input to the input device 2. When inputting information to the input device 2, the components of the control circuit are divided into a plurality of layers, for example, upper, middle, and lower three layers by their functions, and the functions of the elements belonging to each layer are divided into the respective layers. Marks associated with each other and symbolized are set for each element, and marks of elements belonging to each layer are marked with the upper block diagram 11, the middle block diagram 12, and the lower block diagram 1, respectively.
3 is described. Each block diagram 11-1
Reference numeral 3 denotes a plurality of sheets, each of which includes a plurality of marks which symbolize the components of the control circuit. For example, in the upper block diagram 11a, a macro 111 (hereinafter, referred to as a large macro) is set as a mark regarding an element. In the present embodiment, the macro 111 is defined as a large macro since specific components of the macro 111 are configured by the operators 121 in the lower block diagram 13a. On the other hand, block diagram 11
In b, a macro 112 (hereinafter, referred to as a hierarchical macro) is set as a mark. This macro 112
In this embodiment, since the specific configuration of the macro 112 is shown by the arithmetic element 121 shown in the middle block diagram 12a, it is defined as a hierarchical macro. Also, a macro 112 (hierarchical macro) is set in the upper block diagram 11c, and a large macro 1 is marked in the middle block diagram 12b as a mark of an element mutually related to the macro 112.
11 is set. Further, as a mark of an element related to the element in the middle block diagram 12b, the large macro 1
Marks of the operation elements 121 are set in a lower block diagram 13b showing a specific configuration of the arithmetic element 11.

Upper block diagram 11, middle block diagram 1
2. When describing information about each component of the control circuit in the lower block diagram 13, a mark of each component is described in each block diagram, and a signal terminal group or input / output terminal group and a signal line group of the mark are described. Describe, describe the terminal name or signal name for each function of each signal terminal in each signal terminal (or each input / output terminal) of the mark of the element belonging to the highest hierarchy, and also describe each signal terminal (or The same terminal name and signal name are described for each function of the signal terminal in the input / output terminal, and each signal terminal (or input / output terminal) of the mark of the element belonging to the hierarchy lower than the highest level is described in the highest level. Among the elements belonging to the hierarchy, the signal names (or input / output terminals) of the elements whose functions are related to each other, the terminal names or signal names related to each other, or the functions belonging to the layers higher than the own layer. There has been decided to describe the terminal name or signal names associated with each other with the signal terminal of the mark elements associated with each other (or output terminal) for each function of each signal terminal (or output terminal).

Further, when the upper block diagrams 11a to 11c or the middle block diagrams 12a and 12b have the same elements, the block diagrams on the lower side of the hierarchy to which they belong are shared. There are a plurality of identical marks, and as a logic when the plurality of elements share an element belonging to a hierarchy lower than this hierarchy, a plurality of upper elements name the plurality of lower elements, for example, Control logic to be used by mutually switching is set according to a terminal name or a signal name, and this control logic is input as information.

When information related to each block diagram is input from the input device 2, the input information is processed by the block diagram input / display processing unit 41 of the programming tool 4, and then stored in the block diagram database 42. The processing result is displayed on the display screen of the display device 3. When data relating to the block diagram is stored in the database 42 of the programming tool 4, a control program is generated based on the data stored in the database 42 by the control program generation processing unit 43, and the generated control program is stored in the CPU 5 for the control device. To be forwarded to. The CPU 5 can execute various controls according to the generated control program. Note that the basic arithmetic element 121 is an element having a fixed arithmetic function and a fixed symbol.
1 is stored in the block diagram database 42 in advance.

When inputting data relating to each block diagram, the operator checks the display contents displayed on the display screen of the display device 3 while checking the upper block diagram 11a.
11c, the middle block diagrams 12a and 12b, and the lower block diagrams 13a and 13b are input from the input device 2 using a keyboard, a mouse, or the like. The input procedure at this time describes information on the lower block diagrams 13a and 13b or the middle block 12a including circuit elements whose functions are fixed and commonly used, and these data are stored in the database 42. Next, the lower block diagram 13a,
13b, a block diagram belonging to a higher hierarchy than the middle block diagram 12a, for example, upper block diagrams 11a, 11b,
Large macro 1 as data related to middle block diagram 12b
11. Describe data related to the hierarchical macro 112 and store these contents in the database 42. After the description related to the middle block diagram 12b is completed, information related to the hierarchical macro 112 is described as information related to the upper block diagram 11c.

At this time, the input signal and the output signal of the large macro 111 or the hierarchical macro 112 are
The input and output signals of the block diagrams a and 13b or the middle-level block diagrams 12a and 12b are described so that the signal names and numbers match.
Thereby, the large macro 111 or the hierarchical macro 112 and the lower block diagram 13a, 13b or the middle block diagram 1
2a and 12b, the connection relation of signals between the layers is determined, and every time the operation of the large macro 111 or the hierarchical macro 112 is executed, the input signal necessary for each macro is reduced to the lower block diagram 1
3a or given in the middle block diagrams 12a, 12b,
This calculation result can be extracted as a macro output signal.

Specifically, as shown in FIG. 2, when describing the hierarchical macros 112a and 112b as marks of elements having the same function in the upper block diagrams 11b and 11c, the input / output of each hierarchical macro 112a and 112b is performed. As the names of the terminals (signal terminals), the same signal names, for example, the input signal 23 and the output signal 24 are described in association with the signal terminals (input / output terminals). Then, each hierarchical macro 112a, 1
When the middle block diagram 12b uses the middle block diagram 12b as a common circuit, the same input signals 23 and output signals 24 as the hierarchical macros 112a and 112b are described in the input / output terminals (signal terminals) of the middle block diagram 12b. Further, when the large macros 111a and 111b belonging to the middle block diagram 12b have the same function and each large macro uses the lower block diagram 13b in common, the same input signal 25 is applied to the input / output terminals of the large macros 111a and 111b. , The output signal 26, and the input signal 2 having the same name as the large macros 111a, 111b is connected to the input / output terminal of the lower block diagram 13b.
5. Describe the output signal 26.

Further, the upper block diagrams 11b and 11c set the input switch 211 and the output switch 221 as control logic for commonly using the middle block diagram 12b, and the large macros 111a and 111b of the middle block diagram 12b An input switch 212 and an output switch 222 are set as control logic that commonly uses the lower block diagram 13b.

Here, when performing the operations of the upper block diagrams 11b and 11c, if the upper block diagram 11c is performed after the operation of the upper block diagram 11b, the hierarchical macro 112a is calculated when the upper block diagram 11b is calculated. Of the large macro 111 via the input switch 211
a. The input signal 25 of the large macro 111a is given via the input switch 212 as the input signal 25 of the lower block diagram 13b. When the calculation according to the lower block diagram 13b is performed, the calculation result is given as the output signal 26 to the large macro 111a via the output circuit 222. When the output signal 26 of the large macro 111a is provided as the input signal 25 of the large macro 111b, the input signal 25 to the large macro 111b is provided via the input switch 212 as the input signal 25 of the lower block diagram 13b. When the operation according to the lower block diagram 13b is executed, the operation result is given as the output signal 26 as the output signal 26 of the large macro 111b via the output switch 222. This output signal 26 is
Output switching 2 as a signal indicating the operation result according to 2b
21 and is provided as an output signal 24 of the hierarchical macro 112a.

Thus, the input signal 2 to the common circuit
3, 25 and the switching logic of the output signals 24, 26 are similarly executed when the next higher-level block diagram 11c is calculated. Thus, every time the operation of each macro is executed,
It sequentially calculates the lower block diagram corresponding to each macro,
The input signal used for this operation and the output signal indicating the result of the operation are given as the input signal and the output signal of the macro on the upper side, so that the common and single middle A hierarchical description having a block diagram or a lower block diagram becomes possible.

Next, FIG. 3 shows an embodiment in which signal connection between layers is determined without describing names related to input / output signals at specific input / output terminals of a large macro or a hierarchical macro.
It is explained according to.

In FIG. 3, upper block diagrams 11a, 1
When describing the large macros 111a and 111b as marks having the same function among the elements belonging to 1b, only the specific input / output terminals (input / output terminals) of the large macros 111a and 111b are referred to as input signals 27 as names. ,
The output signal 28 will be described. Furthermore, each large macro 111a,
In the vicinity of 111b, as a signal output destination terminal indicating a signal output destination, its mark and identification name, for example, macro element 3
1a is described, and as a signal input source mark indicating a signal input source, the mark and an identification name, for example, the macro element 32a are described. The macro elements 31a and 31b are described with the same name as signal output destination identification names, and the macro elements 32a and 32b are described with the same name as signal input source identification names. Further, the macro elements 31a, 31b, 32
The input switch 213 and the output switch 223 are set as the logic for sharing the lower block diagram 13 using a and 32b.

Here, when the operation of the upper block diagram 11b is executed after the operation of the upper block diagram 11a, the input signal 27 of the lower block diagram 13 when the upper block diagram 11a is operated is the input signal to the large macro 111a. The other input signal is provided by the macro element 31
The signal input to “a” is input to the macro element 31 via the input switch 213. When the operation according to the lower block diagram 13 is executed, one output signal 28 of the operation result is given as the output signal 28 of the large macro 111a, and the other output signal is output as the output signal of the macro element 32, and the output switching is performed. 223 to the macro element 32a.

Next, when executing the operation of the upper block diagram 11b, the input signal 27 to the large macro 111b is given as the input signal 27 of the lower block diagram 13 and the other input signal is input to the macro element 31b. The signal is supplied to the macro element 31 via the input switch 213. When the operation according to the lower block diagram 13 is executed, one of the output signals based on the operation result is set as the output signal 28 as the output signal 28 of the large macro 111b.
And the other output signal is provided as an output signal of the macro element 32 to the macro element 32 b via the output switch 223.

As described above, in the process of sequentially performing the operation on the lower block diagram corresponding to each macro, the input / output signal of the macro on the upper side or the input / output signal specified by the macro element is used. Therefore, a hierarchical description method that has a common middle block diagram or lower block diagram common to a plurality of upper block diagrams or middle block diagrams becomes possible. In addition, the signals related to common circuits that are not particularly necessary in terms of functional representation are not directly described in large macros or hierarchical macros, but the names related to input / output signals are described in specific input / output terminals. The upper block diagrams 11a and 11b can be described in a concise and easy-to-read manner with a focus on functions.

When using a macro element, FIG.
As shown in (a), the mark of the macro element 41 connected to the signal line, for example, the input signal line 43 is described, and the output destination identification signal name 411 is set as an arbitrary character string, symbol, or It can be described by figures. Further, the mark can be described as the macro element 42 connected to the output signal line 44, and the input source identification signal name 421 can be described as an arbitrary character string, symbol, or figure as the name of the macro element 42.
In this case, using the names of the macro elements 41 and 42 as addresses, data relating to the input signal line 43, the output signal line 44, the output destination signal identification name 411, and the input source identification signal name 421 are stored at these addresses.

In this case, as shown in FIG. 4B, by matching the output destination identification signal name 411 with the input source identification signal name 421, the macro element can be described without using a signal line to describe the connection relationship. By describing 41 and 42, signals can be exchanged. Furthermore, by matching the names of the macro element 41 and the macro element 42 as shown in FIG.
Even if the connection relation between one circuit and n circuits is not described by a signal line, the signals of the circuits for one to n can be exchanged by describing the macro elements 41 and 42.

Next, an embodiment in which the input signal of the middle block diagram serving as a common circuit of the upper block diagram does not need to be described in the large macro of the upper block diagram will be described with reference to FIG.

FIG. 5A shows an example in which all of the input signals 52a and 52b corresponding to the input terminals of the lower block diagram 13 which is a common circuit of the upper block diagram 11 are described. On the other hand, FIG. 5B illustrates only the input signal 52a of the large macro 111 in the lower block diagram 13, which is a common circuit of the upper block diagram 11, and omits the description of the input signal 52b in the large macro 111. In the lower block diagram 13, a mark indicating the initial setting value 54 is described instead of the input signal 52b. The mark relating to the initial setting value 54 is connected to the arithmetic element 121 via a switch. When such a description method is adopted, when the description of a specific input signal and a signal name is omitted in the large macro 111, in the lower block diagram 13, instead of the input signal 52b, a preset initial set value is used. The operation can be performed using. When the input signal for which the initial setting value 54 is not preset in the lower block diagram 13 is omitted on the large macro 111 or the hierarchical macro side, a function of outputting an error message can be provided at the same time. Such a description method can also be applied to a medium-level block diagram.

According to the present embodiment, since only the input signals necessary for the function need to be described in the large macro or the hierarchical macro, only the mark mainly focusing on the function can be described in the upper block diagram. In addition, even if there is a slight difference in individual functions or input points in the upper block diagram or the middle block diagram, it is possible to flexibly cope with them. Even in various circuits having similar functions, it is common to one type of large macro or hierarchical macro. Can be

Next, the output signal of the middle block diagram or the lower block diagram which is a common circuit of the upper block diagram or the middle block diagram is not required to be described in the large macro or the hierarchical macro of the upper block diagram or the middle block diagram. FIG. 6 shows an embodiment in which this is done.

FIG. 6 (a) shows the large macro 111 of the upper block diagram 11 with the input signals 52a,
52b shows an example in which all the output signals 53a and 53b are described. On the other hand, FIG. 6B shows that the large macro 111 of the upper block diagram 11 includes the input signals 52a and 52b and the output signal 53a of the input / output signals of the lower block diagram 13.
Only the case where only the description of the output signal 53b is omitted is shown. Note that such a description method can be used in the relationship between the middle block diagram and the lower block diagram.

According to the present embodiment, only the output signals necessary for the function need to be described in the large macro or the hierarchical macro. Therefore, only the marks and names centering on the functions are described in the upper block diagram or the middle block diagram. Can be described. Further, even when there is a slight difference between the individual functions and the output points of the upper block diagram or the middle block diagram, it is possible to flexibly cope with the problem.
It can be shared by large macros or hierarchical macros.

Next, an embodiment in which a block diagram of three layers is extended to (3 + n) layers will be described with reference to FIG.

In the present embodiment, block diagrams 11, 12, and 13 of three layers include block diagrams 71 including n layers.
... 7n are added. That is, when the block diagram 11 is used as the upper block diagram, the block diagram 12 is used as the middle block diagram, and the block diagram 13 is used as the lower block diagram in the block diagram of the three layers, the upper block diagram of the upper block diagram 11 is used. Block diagrams 71 to 7n are provided as block diagrams belonging to a hierarchy.

In providing the block diagrams 71 to 7n,
As described above, the block diagram 71,... 7n include the hierarchical macro 112 of the upper block diagram 11 and the middle block diagram 1
2, a hierarchical macro 112 is set in the block diagram 71, and a specific configuration of the hierarchical macro 112 is as follows.
The relationship expressed by the upper-level block diagram 11 one layer below is provided. Further, this hierarchical relationship is sequentially expanded, and the hierarchical macro 112 in the block diagram 7n is
It is represented by a block diagram below the hierarchy. In this case, the block diagram 7n is a block diagram belonging to the highest hierarchy, and the block diagrams of the (3 + n) hierarchy can be realized by the block diagrams 7n to 13.

According to the present embodiment, common elements among the elements belonging to the higher hierarchy can be represented by the lower block diagram, so that the number of drawings in the lower block diagram can be reduced. .

In each of the above-described embodiments, the block diagram belonging to the upper hierarchy can be described as the minimum element in the block diagram belonging to the lower hierarchy, and therefore, belongs to the lower hierarchy. The number of drawings in the block diagram can be reduced, and the capacity of data relating to the lower block diagram can be reduced.

In the above embodiment, the description has been given of the embodiment in which each component of the control circuit is described in a block diagram. However, the present invention is also applicable to a method of generating a control program and a method of displaying a block diagram. Can be.

[0051]

As described above, according to the present invention,
Since the same elements belonging to the upper layer are described as the minimum elements in the block diagram belonging to the lower layer, the block diagram belonging to the upper layer can be described simply and easily. It is possible to reduce the number of block diagrams belonging to the lower hierarchical level.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, which is a block diagram configuration created by a hierarchical description method of a control circuit, and programming for inputting information related to the block diagram and displaying a processing result thereof; FIG. 3 is a configuration diagram illustrating a relationship with a tool.

FIG. 2 is a diagram for explaining a configuration when a plurality of upper block diagrams have a middle block diagram and a lower block diagram as common circuits.

FIG. 3 is a diagram for explaining a connection relationship between signals in a plurality of upper block diagrams and lower block diagrams.

FIG. 4 is a diagram for explaining a signal connection relationship when a macro element is used.

FIG. 5 is a diagram for describing a description method when an input signal of a large macro is omitted.

FIG. 6 is a diagram for explaining a description method when an output signal of a large macro is omitted.

FIG. 7 is a diagram for explaining a configuration when the block diagram is set to (3 + n) levels.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Block diagram 2 Input device 3 Display device 4 Programming tool 5 CPU 11a, 11b, 11c Upper block diagram 12a, 12b Middle block diagram 13a, 13b Lower block diagram 111 Large macro 112 Hierarchical macro 121 Operation element

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akio Ito 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Inventor Katsuhito Shimizu 5-chome, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 in Hitachi, Ltd. Omika Plant (72) Inventor Toru Kimura 5-2-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside of Hitachi, Ltd. Omika Plant (72) Inventor Ikuo Koibuchi Hitachi, Ibaraki Prefecture 5-2-1, Omikacho In the Omika Plant of Hitachi, Ltd. (72) Inventor Hideo Otomo 3-2-2, Sachimachi, Hitachi, Ibaraki Prefecture Within Hitachi Engineering Services Co., Ltd.

Claims (14)

[Claims] 1. A component of a control circuit is divided into a plurality of hierarchies by its function, and a mark symbolized by associating the function of the element of each hierarchical level with each hierarchical level is set in each element. The marks of the elements to which they belong are described in the top-level block diagram corresponding to the top layer, and the elements belonging to the layers lower than the top layer are marked with the minimum mark for each function in each lower layer. And the name of each function is described in the mark of the element belonging to the highest level,
In addition, the same mark describes the same name for each function, and the mark of the element belonging to the hierarchy lower than the highest level is the mark of the element whose function is mutually related among the elements belonging to the highest level. A hierarchical description method of a control circuit for describing, for each function, a name related to each other or a name of a mutually related name or a mark of an element whose function is mutually related among elements belonging to a layer higher than its own layer. 2. A component of the control circuit is divided into a plurality of layers by its function, and a mark symbolized by associating the function of the element of each layer with each layer is set in each element. The marks of the elements belonging to the highest level block diagram corresponding to the highest level are described together with the signal terminal group and the signal line group. For the elements belonging to the level lower than the highest level, a minimum mark is provided for each function. Describe in the lower block diagram corresponding to the hierarchy together with the signal terminal group and the signal line group, and describe the terminal name or signal name for each signal terminal function in each signal terminal of the mark of the element belonging to the highest hierarchy, And, for each signal terminal of the same mark, describe the same terminal name or signal name for each function of the signal terminal,
Each signal terminal of the mark of the element belonging to the hierarchy lower than the highest level has a terminal name or a signal name that is mutually related to the signal terminal of the mark of the element whose function is mutually related among the elements belonging to the highest level. Alternatively, a hierarchical description of a control circuit that describes, for each function of each signal terminal, a terminal name or a signal name that is associated with a signal terminal of a mark of an element whose function is mutually associated among elements belonging to a layer higher than its own layer. Method. 3. A component of the control circuit is divided into a plurality of layers by its function, and a mark symbolized by associating the function of the element of each layer with each layer is set in each element. Describe the marks of the elements that belong to them together with the input / output terminal groups and signal line groups in the highest level block diagram corresponding to the highest level, and for the elements belonging to the levels lower than the highest level, a minimum mark for each function Describe the input / output terminal group and signal line group in the lower block diagram corresponding to each hierarchy, and mark the input / output terminals of the elements belonging to the top hierarchy with the terminal name or signal name for each input / output terminal function. And describe the same terminal name or signal name for each input / output terminal function for each input / output terminal of the same mark, and mark each input / output terminal of the element belonging to the hierarchy lower than the highest level. The terminal name or signal name that is related to the input / output terminal of the mark of the element whose function is mutually related among the elements that belong to the highest level A hierarchical description method of a control circuit for describing, for each function of each input / output terminal, a terminal name or a signal name associated with an input / output terminal of a mark of an element associated with each other. 4. A component of the control circuit is divided into a plurality of layers by its function, and a mark symbolized by associating the function of the element of each layer with each layer is set in each element. The marks of the elements to which they belong are described in the top-level block diagram corresponding to the top layer, and the elements belonging to the layers lower than the top layer are marked with the minimum mark for each function in each lower layer. , And the name of each function is described in the mark of the element belonging to the highest hierarchy,
In addition, the same mark describes the same name for each function, and the mark of the element belonging to the hierarchy lower than the highest level is the mark of the element whose function is mutually related among the elements belonging to the highest level. For each function, describe the name of the mutually related name or the mark of the element whose function is mutually related among the elements belonging to the hierarchy higher than the own layer, and the name of the mutually related function. When there are multiple elements and these elements share an element belonging to a layer lower than this level, set the control logic to use the upper multiple elements by switching the lower common elements to each other according to the name. Hierarchical description of control circuit 5. A control circuit element is divided into a plurality of layers by its function, and a mark symbolized by associating the function of each layer element with each layer is set for each element, and the mark is set to the highest layer. The marks of the elements belonging to the highest level block diagram corresponding to the highest level are described together with the signal terminal group and the signal line group. For the elements belonging to the level lower than the highest level, a minimum mark is provided for each function. Describe in the lower block diagram corresponding to the hierarchy together with the signal terminal group and the signal line group, and describe the terminal name or signal name for each signal terminal function in each signal terminal of the mark of the element belonging to the highest hierarchy, And, for each signal terminal of the same mark, describe the same terminal name or signal name for each function of the signal terminal,
Each signal terminal of the mark of the element belonging to the hierarchy lower than the highest level has a terminal name or a signal name that is mutually related to the signal terminal of the mark of the element whose function is mutually related among the elements belonging to the highest level. Alternatively, among the elements belonging to the hierarchy higher than the own hierarchy, describe the terminal name or signal name that is mutually related to the signal terminal of the mark of the element whose function is mutually related for each function of each signal terminal, and put them in the same hierarchy. When there are a plurality of the same marks and these elements share an element belonging to a layer lower than this layer, a plurality of elements on the upper side determine a common element on the lower side according to a terminal name or a signal name. A hierarchical description method of a control circuit for setting control logic to be used by switching between them. 6. A control circuit element is divided into a plurality of hierarchies according to its functions, and a mark symbolized by associating the function of each hierarchical element with each hierarchical element is set in each element. Describe the marks of the elements that belong to them together with the input / output terminal groups and signal line groups in the highest level block diagram corresponding to the highest level, and for the elements belonging to the levels lower than the highest level, a minimum mark for each function Describe the input / output terminal group and signal line group in the lower block diagram corresponding to each hierarchy, and mark the input / output terminals of the elements belonging to the top hierarchy with the terminal name or signal name for each input / output terminal function. And describe the same terminal name or signal name for each input / output terminal function for each input / output terminal of the same mark, and mark each input / output terminal of the element belonging to the hierarchy lower than the highest level. The terminal name or signal name that is related to the input / output terminal of the mark of the element whose function is mutually related among the elements that belong to the highest level Describe the input / output terminal of the mark of the interrelated element and the terminal name or signal name that are associated with each other for each function of the input / output terminal,
When there are a plurality of the same marks in the same layer, and the plurality of elements share an element belonging to a layer lower than this layer, a plurality of elements on an upper side designate a common element on a lower side as a logic. Alternatively, a hierarchical description method of a control circuit for setting a control logic to be used by switching between them according to a signal name. 7. A control circuit element is divided into a plurality of layers by its function, and a mark symbolized by associating the function of each layer element with each layer is set in each element. The mark of the element to which it belongs is described together with the specific signal terminal and the specific signal line in the top block diagram corresponding to the top layer, and the element belonging to the layer lower than the top layer has the minimum mark for each function. Are described in the lower block diagram corresponding to each hierarchy together with the signal terminal group and the signal line group, and a specific signal terminal of a mark of an element belonging to the highest hierarchy is provided with a terminal name or a signal name for each signal terminal function. Describe and describe the same terminal name or signal name for each signal terminal function at a specific signal terminal of the same mark, and mark each signal end of the mark of an element belonging to the hierarchy lower than the highest level. The child has the terminal name or signal name that is related to the signal terminal of the mark of the element whose function is related to the element of the highest level, or the function of the element that belongs to the layer higher than the own layer. A hierarchical description method of a control circuit for describing, for each function of a signal terminal, a terminal name or a signal name associated with a signal terminal of a mark of an interconnected element. 8. A component of the control circuit is divided into a plurality of layers by its function, and a mark symbolized by associating the function of the element of each layer with each layer is set for each element. The mark of the element to which it belongs is described with the specific input / output terminal and the specific signal line in the top block diagram corresponding to the top layer, and the element belonging to the lower layer from the top Marks are described in the lower block diagram corresponding to each layer together with input / output terminal groups and signal line groups, and the specific input / output terminal of the mark of the element belonging to the top layer is a terminal name for each function of the input / output terminal Or, describe the signal name, and write the same terminal name or signal name for each input / output terminal function at the specific input / output terminal of the same mark, and mark the elements belonging to the lower hierarchy from the highest level. Each input / output terminal has a name of the terminal or signal that is associated with the input / output terminal of the mark of the element whose function is mutually related among the elements belonging to the highest level, or a higher level than its own layer. A hierarchical description method of a control circuit for describing, for each function of each input / output terminal, a terminal name or a signal name which is associated with an input / output terminal of a mark of an element whose function is associated with each other. 9. A component of the control circuit is divided into a plurality of layers by its function, and a mark symbolized by associating the function of the element of each layer with each layer is set in each element. The mark of the element to which it belongs is described together with the specific signal terminal and the specific signal line in the top block diagram corresponding to the top layer, and the element belonging to the layer lower than the top layer has the minimum mark for each function. Are described in the lower block diagram corresponding to each hierarchy together with the signal terminal group and the signal line group, and the specific signal terminal of the mark of the element belonging to the highest hierarchy is provided with a terminal name or a signal name for each signal terminal function. Describe and describe the same terminal name or signal name for each signal terminal function at a specific signal terminal of the same mark, and mark each signal end of the mark of an element belonging to the hierarchy lower than the highest level. The child has the terminal name or signal name that is related to the signal terminal of the mark of the element whose function is related to the element of the highest level, or the function of the element that belongs to the layer higher than the own layer. Describe the terminal name or signal name related to the signal terminal of the mark of the interrelated element for each function of each signal terminal, and there are a plurality of the same marks in the same layer, and these elements are Hierarchical description of a control circuit for setting a control logic in which a plurality of higher-level elements mutually switch between lower-level common elements according to terminal names or signal names as logic when sharing elements belonging to lower-level layers Method. 10. A component of a control circuit is divided into a plurality of hierarchies by its function, and a mark symbolized by associating the function of the element of each hierarchical level with each hierarchical level is set in each element. The mark of the element to which it belongs is described with the specific input / output terminal and the specific signal line in the top block diagram corresponding to the top layer, and the element belonging to the lower layer from the top Marks are described in the lower block diagram corresponding to each layer together with input / output terminal groups and signal line groups, and the specific input / output terminal of the mark of the element belonging to the top layer is a terminal name for each function of the input / output terminal Alternatively, describe the signal name, and describe the same terminal name or signal name for each input / output terminal function at a specific input / output terminal of the same mark, and map the elements belonging to the hierarchy lower than the highest level. Each input / output terminal of the network has a terminal name or signal name that is associated with the input / output terminal of the mark of the element whose function is mutually related among the elements belonging to the highest level, or a layer higher than its own layer. Describe the input / output terminals of the marks of the elements whose functions are related to each other and the terminal names or signal names that are related to each other, for each function of each input / output terminal. As a logic when a plurality of elements exist and share an element belonging to a layer lower than this layer, a control in which a plurality of elements on the upper side switch and use a common element on the lower side in accordance with a terminal name or a signal name A hierarchical description method of a control circuit for setting logic. 11. In the lower block diagram, in place of a specific signal terminal and a signal terminal and a signal line deviating from a specific signal line, a mark of an element belonging only to the lower hierarchy from the highest level is marked with another element. 10. The method according to claim 7, wherein the control circuit is described in association with a mark. 12. In the lower block diagram, in place of a specific input / output terminal or a signal terminal or a signal line deviating from a specific signal line, a mark of an element belonging only to the lower hierarchy from the highest level is marked with another element. 11. The method for hierarchically describing a control circuit according to claim 8 or 10, wherein the method is described in association with a mark. 13. A mark and an identification name are described as a signal output destination terminal indicating a signal output destination in the vicinity of a mark of an element belonging to the highest hierarchy, and a signal input source terminal indicating a signal input source is described. Describe the mark and identification name, describe the signal output destination identification name and the signal input source identification name indicating the input source of the signal, and in the vicinity of the mark of the element belonging to the hierarchy lower than the top, the top hierarchy The signal output destination terminal described in the vicinity of the mark of the element belonging to and the mark and the identification name as the lower signal input source terminal correlated with each other are described, and the vicinity of the mark of the element belonging to the highest hierarchy is described. 12. A mark and an identification name are respectively described as lower signal output destination terminals which are mutually related to the described signal input source terminal.
Or the hierarchical description method of a control circuit according to 12. 14. A plurality of identical signal output destination terminals and signal input source terminals are present in the vicinity of a plurality of marks belonging to the same hierarchy, and the plurality of signal output destination terminals and signal input source terminals are lower than this hierarchy. The logic sharing the lower signal input source terminal and the lower signal output destination terminal described near the mark of the element belonging to the hierarchy of a plurality of upper signal output destination terminals and the lower signal output source terminal are common to the lower side. 14. The hierarchical description method of a control circuit according to claim 13, wherein a control logic to be used by switching the lower signal input source terminal and the lower signal output destination terminal of each other according to the terminal identification name is set.