JPH1185674A - Method for transaction communication between pct buses and computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely communicate a transaction between devices respectively connected to primary and secondary PCI buses. SOLUTION: A PCI repeater 116 is interposed between a primary PCI bus 112 and a secondary PCI bus 118. The repeater snoops a configuration cycle communicated by the primary PCI bus 112 and stores the base address of a device contained in this cycle into an address map. Besides, when the transaction generated on the secondary PCI bus 118 has been addressed to the device included in the address map, the repeater transfers it to the primary PCI bus 112. When the transaction is not included in the address map, it is transferred to the secondary PCI bus 118. Since the configuration cycle is executed in initialization or the like without fail, the repeater can confirm the device connected to the primary PCI bus 112 so that communication is surely performed between different PCI buses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus and a method for bridging two PCI buses, and more particularly to a software-transparent PCI / PCI repeater.

[0002]

2. Description of the Related Art The performance of a personal computer (PC) depends on processor speed, memory and input / output (I / O).
Depends on many factors, such as subsystems. 199
In two years, a PCI (Peripheral Component Interconnect) bus was introduced,
The I / O subsystem is now equipped with a high performance bus. Initially, the PCI bus was not intended to replace existing expansion buses such as the ISA (Industrial Standard Architecture) bus or the EISA (Extended Industrial Standard Architecture) bus. However, pressure from the computer industry and bus contention have allowed PCI buses to be used for expansion bus purposes. In this way,
Computer systems can now incorporate PCI devices into motherboards and provide support for add-in boards.

[0003] The PCI bus is called a mezzanine bus or a local bus for the following reasons.
This is because the functionality of the PCI bus exists between a very high performance processor bus and a low performance ISA or EISA bus. The logic that connects one computer bus to another bus allows agents on one bus to access agents on the other bus, and is known as a bridge. In PCI terminology, an agent is any entity or device that runs on a computer bus. The agent is a bus master or a bus slave. A bus master, or initiator, initiates a bus transaction, and a bus slave, or target, responds to a bus transaction initiated by the bus master. In many cases, the initiator is on one bus and the target is on another bus.

A bridge provides a low-latency path through which a PCI device mapped anywhere in a computer system's memory or I / O address space is directly accessed by a processor. The basic function of a bridge is to map the address space of one bus to the address space of another bus. The PCI bus defines three physical address spaces: a memory space, an I / O space, and a configuration space. The decoding of addresses on the PCI bus is distributed, ie, each device coupled to the PCI bus performs the decoding of the address. PC
The I specification defines two styles of address decoding, positive and subtractive. Positive decoding is faster because each PCI device claims access in the address range to which it is assigned. The subtractive decoding can be realized by only one device on the PCI bus. This is because the device performing the subtractive decoding accepts all accesses that have not been positively decoded by any other agent.

[0005] All PCI transfers begin in the address phase. During that phase, the address / data bus (AD [31: 0]) transfers addresses and the command / byte enable (C / BE_ [3: 0]) bus transfers command codes. One or more data phases follow this phase, during which the same address / data bus transfers data and the command / byte enable bus transfers byte enable signals. In a burst cycle, multiple data phases can follow one address phase. In PCI terminology, the requesting PCI device is the initiator and the addressed PCI device.
The device is targeted. All transfers begin with the activation of the frame (FRAME_) signal.

A device select (DEVSEL #) signal is driven by the target to indicate that it is responding to a transaction. If the device has a starting address, it decodes the address / data line and
Assert the VSEL # signal. DEVSEL # can be driven using slow, intermediate, or fast timing. If no agent asserts DEVSEL # with slow timing parameters, then the agent performing the subtractive decoding claims and asserts DEVSEL #. The symbol # or _ means an active low signal. Further details regarding PCI buses and, in particular, PCI addressing, are published by the PCI Special Interest Group, Hillsborough, Oregon, USA, dated June 1, 1995.
It is described in the production version of the CI local bus specification, revision 2.1. This is incorporated by reference in this application.

The target is ready (r) using the active target ready (TRDY_) signal.
eadiness). An active TRDY_ during a write access indicates that the requested data is available on the address / data bus. In addition, the initiator must indicate to the PCI bridge that it is ready via an active initiator ready (IRDY_) signal. An active IRDY_ during a write access indicates that the initiator has sent write data on the address / data bus. For a read access, an active IRDY_ indicates that data from the address / data bus has been accepted. The initiator terminates or suspends the transfer by deactivating the FRAME_ signal. The target is also stopped (ST
The transfer can be stopped by activating the OP_) signal.

[0008]

As defined, the PCI bus is limited to ten loads. The PCI device embedded on the motherboard is essentially one load, and the PCI slot is 2
One load. Thus, a computer system with one processor / PCI bridge, three PCI slots, and one PCI / ISA bridge is limited to two motherboard devices. Since in many cases two motherboard devices are too restrictive, it is desirable to extend this ten load limit. As a method of expanding the number of loads described in the above-mentioned PCI specification, there is a method of using a plurality of PCI buses. The multiple PCI buses are:
Provides support for more devices than can be directly connected to a single PCI bus. There are two ways to organize multiple PCI buses. A method of making them equal to each other and a method of layering. A peer bus requires multiple bridges on the processor bus, which can affect loading. Hierarchical configurations have advantages where the I / O pattern tends to be from one PCI device to another. If most I / O traffic enters and leaves memory, a comparable bus is more meaningful. However, both bus configurations require that the bridge, at startup, respond to accesses on its primary bus only if the address falls within a particular range. Further, the bridge separates the bus into two logical buses, thereby further complicating the configuration.

[0009] Each bridge includes address registers that are programmable through the configuration space so that the bridge only has its address on its primary bus if the address falls within the range specified by these registers. Respond to access. Otherwise, access is solicited by a subtractive decoding agent. Although only one set of address range response registers is required by the PCI specification, where multiple buses are provided, address complexity increases and multiple sets of registers are required. Generally, the address range response register is programmed to correspond to addresses not used by the primary bus, rather than the memory space required by the secondary bus. Thus, the secondary side of the bridge responds to all memory accesses except those in the range specified by the address response range register. Starting on the secondary bus, all transactions outside the programmed range are responded on the primary bus. It is the responsibility of the system software to maintain the bridge's address response range register so that address decoding is performed properly.

[0010] If the device is hot-pluggable (the device can be disconnected without disconnecting power), the configuration of the address range register becomes even more complex. PC CardBus (PC Cardbu
s) Hot-pluggable devices such as cards
Problems arise because the address range changes with the insertion or removal of hot-pluggable devices. Accordingly, it is desirable to eliminate this level of complexity while at the same time providing a greater number of PCI loads for full functionality and scalability. Transparent bridges make the bridge invisible to software,
Attempts have been made to solve this configuration problem. However, the performance of such bridges is often not very high. Cycles implemented on the primary bus at the top speed of the PCI bus take three times as long on the secondary bus if they follow the original PCI timing conventions. Therefore, a higher performance transparent bridge is desired.

[0011]

According to the present invention, there is provided a computer comprising:
The system increases the number of capacitive loads on the PCI bus without requiring significant changes to the software.
Includes CI bridge or repeater. PCI repeaters are
Connect the primary part of the PCI bus to the secondary part of the PCI bus. These parts function as one logical bus, but are electrically separated for loading.
An arbiter controls access to the bus. Transactions initiated on the primary bus and directed to targets on the secondary bus are downstream transactions. Transactions initiated on the secondary bus and directed to targets on the primary bus are upstream transactions. Transactions initiated on the primary bus go to the secondary bus,
Or, in the opposite direction, it is repeated (echoed), sent and reflected.

Since the signal is clocked through the PCI repeater, a one clock delay is built-in. Due to intrinsic delays, one of the buses may end the transaction sooner than the other. To prevent an early-ending bus from starting another transaction while a late-ending bus is still executing a transaction, the arbiter removes all pending grants and terminates late. The bus is not granted to either device on either bus until the bus that completes the transaction. This method works particularly well for burst-type transactions where the target cannot move data at the same rate as the initiator.

An upstream transaction is:
It is processed like a downstream transaction, except that there is a subtractive decoding agent on a secondary bus, such as an ISA bus bridge. Since there can be only one subtractive decoding agent on a bus, transactions are performed both upstream in the primary bus direction and downstream in the ISA bus direction.
It is not decodable to subtractive. In the first method, the subtractive decoding to the ISA bus by the PCI / ISA bridge is disabled if the transaction is initiated on the secondary bus.
This gives peer / peer transactions only between devices on the primary and secondary buses. In the second method, ISA subtractive decoding is enabled. After the transaction starts on the secondary bus, the clock on the secondary bus is stopped, allowing the target on the primary bus to claim the transaction. If the transaction is not charged,
Either terminate operation on the secondary bus and the secondary bus target charges positively or the PCI ISA bus bridge charges subtractively. As described above, the upstream address decoding is performed by the PC.
Not required on I repeaters.

In a third preferred method, the repeater snoops a configuration cycle on the primary PCI bus to provide memory and I / O corresponding to devices attached (coupled) to the primary PCI bus. Build an address map for the address range. The configuration cycles of the devices attached to (coupled to) the secondary PCI or ISA bus are preferably not snooped. The address map is built at initialization, or at any time, devices are added or removed according to standard PCI and Cardbus conventions. The address map provides a look-up table for transactions initiated on the secondary PCI bus. This look-up table provides a reliable indication as to whether the targeted device is on the primary PCI bus. If the target is on the primary PCI bus, the repeater sends the transaction upstream. Otherwise, the transaction is assumed to be directed to a target on the secondary PCI bus or any device attached to a subtractive decoding agent, such as a PCI / ISA bridge.

[0015]

Referring now to the drawings, there is shown a computer system C according to a preferred embodiment of the present invention. To provide sufficient processing and power, computer C uses one or more processors, such as the Pentium Pro Processor available from Intel Corporation of Santa Clara, California, USA. Pentium Pro Processor 100 includes primary and secondary caches. Of course, other types of processors can be used with minimal changes. Processor 10
0 is connected to a Pentium Pro host bus, referred to as the processor bus 102, which is a gunning transceiver logic commonly defined by Pentium Pro specifications.
logic = GTL).

In addition to the processor 100, a processor
The bus 102 is a data bus such as an Intel 82452GX.
Pass Unit (DP) 106 and Intel 82453
Connected to a memory controller (MC) 106, such as a GX, which collectively forms a memory control subsystem for the memory unit 108, and further, such as an Intel 82451KX (not shown) Are connected to a plurality of memory interface elements. The data path unit 104, the memory controller 106, and the memory interface element collectively form a memory control subsystem for the memory unit 108. The memory unit 108
Includes a plurality of slots for receiving memory modules, such as 2-pin EDO DRAM modules. Memory controller 106 provides address, control, and timing to memory unit 108, and data path unit 104 interfaces the 72-bit data portion of processor bus 102 to memory unit 108. Memory controller 106 and data path unit 104 can receive a memory request from processor 100, queue it, and respond after the requested operation has been completed. In addition, the memory controller 106 performs error correction on the memory, including the ability to detect one or more bits of error in progress. Memory controller 106
Can handle up to 4 gigabytes of DRAM. Non-interleaved, memory configurations with x2 and x4 interleaved configurations are supported by the memory control subsystem.

[0017] In addition to the memory subsystem, the processor bus 102 includes one or more processors, such as the Intel 82454GX.
Alternatively, it is connected to a plurality of PCI bridges 110. P
CI bridge 110 provides the necessary logic and control to route bus cycles between processor bus 102 and primary PCI bus 112. Note that although a hierarchical configuration is shown, the invention works equally well in peer-to-peer configurations. The primary PCI bus 112 has a SCSI (small
One or more PCI devices 114, such as a computer system interface (controller) controller 114a and a video system 114b, are coupled. SC
The SI controller 114a is connected to the hard disk drive 124, and the video system 114b including the video memory is connected to the monitor 126. P
The CI device 114 also includes a card bus device. In addition to the PCI device 114, the P
The CI repeater or bridge 116 is connected to the primary PCI bus 1
12 and a secondary PCI bus 118. PC
The I repeater 116 connects the secondary PCI bus 118 to the primary PC.
Although electrically isolated from the I bus 112, both buses appear as one logical PCI bus in appearance. The PCI repeater 116 does this transparently to the system software, so that the number of PCI loads can be increased without adding significant complexity to the system software.

The secondary PCI bus 118 includes one or more PCI devices or slots 120 and a PCI / ISA
The bridge 122 is connected. The PCI / ISA bridge 122 is connected to the secondary PCI bus 118 and the ISA bus 1.
28 cycle. The ISA bus 128 has
A keyboard controller 130, a ROM 134,
Multi I / O unit 136 supporting two serial ports, a parallel port, a floppy disk controller connected to a floppy drive, and an optional IDE hard disk drive or CD-ROM drive IDE interface.

Referring now to FIG. 2, a block diagram of the PCI repeater 116 is illustrated. Repeater 116
Is the primary bus unit 2 connected to the primary bus 112
00 and a secondary bus unit 202 connected to the secondary bus 118. Each bus unit has a selectable voltage converter 204 that converts the voltage level of the signal to a common voltage, such as 3.3 volts. For example, the primary PCI bus 112 and the PCI repeater 1
16 operates at 3.3 volts and the secondary PCI bus operates at 5 volts, the secondary voltage converter 204
Converts the output signal to 5 volts and the input signal from 5 volts to 3.3 volts. To facilitate voltage conversion, the primary is connected to the + Vp voltage and the secondary is connected to + Vp.
connected to the s voltage to select the voltage. This is useful in applications such as portable computers and docking stations. This means that portable computers operate at the 3.3 volt level to save power,
The docking station is operating at normal 5 volts. Repeater 116 is located at either the portable computer or the docking station and provides a connectable PCI bus to the docking station.

The repeater 116 has a read prefetch buffer (RPB) 208 on each side.
And a write posting buffer (WPB) 210
And a primary PCI bus 112 and a secondary PC.
Arbiter 2 arbitrating access to I bus 118
06 is included. Read prefetch buffer 20
8 preferably has a depth of two DWORDs,
Any depth is acceptable. For example, in another embodiment, it can be configured to have an external arbiter. A single clock input is used to provide timing to both primary bus unit 200 and secondary bus unit 202. Therefore, the primary PCI bus and the secondary PCI bus
The bus is required to operate at the same frequency. In another embodiment, a second clock input and synchronization logic are used to operate the bus at different frequencies. However, in that case, the PCI repeater 116 only operates at the same speed as the slowest bus. PCI repeater 1
16 supports a state where the power consumption is zero.

The primary bus unit 200 has a primary PCI unit.
It includes conventional configurable address decode logic that positively and subtractively charges transactions from bus 112. In the secondary bus unit 202, for the reasons described later,
No address decoding is performed. PCI repeaters 116 differ from conventional bridges because they prefer not to store or transmit data. Generally, incoming signals are clocked on the rising edge of the PCI bus clock and routed to other buses. However, the repeater 116 has a function of controlling the echo and repeat of a signal from one bus to another bus without violating any of the operating rules of the PCI. The functionality of the PCI repeater will now be discussed in relation to the downstream cycle and the upstream cycle. Single and burst data cycles are a subset of each of the downstream and upstream cycles.

Downstream Transaction A downstream transaction or cycle refers to a transaction that begins on the primary PCI bus 112 and targets devices on the secondary PCI bus 118 or lower. PCI repeater 116
Is the only subtractive decoding device on the primary PCI bus 112 that follows the PCI conventions. Decoding downstream transactions subtractively, rather than positively, further eliminates BIOS (basic input / output system) and operating system overhead. The PCI repeater 116 generally transmits the entire transaction on the secondary PCI bus 118, as if it were on the primary PCI bus 112, regardless of whether the transaction was directed to the secondary bus 118. Echo. The PCI repeater 116 reflects the signal on the primary PCI bus 112 delayed by one clock, so that the PCI repeater 116 applies one clock to the beginning of the cycle and one clock to the data return for every downstream transaction. Add two clocks. Thus, transactions charged positively on the secondary bus at intermediate decode timings are:
To a device on the primary bus, it looks like a subtractively decoded transaction.

In a downstream transaction, the initiator on the primary PCI bus 112
The signal echoed to the target on CI bus 118 is
FRAME_p, AD [31: 0] p, C / BE [3: 0] p, and IRDY_p. The signals echoed from the secondary PCI bus 118 to the initiator on the primary PCI bus 112 are TRDY_s, STOP_s, DEVSEL
_s. In an upstream transaction,
From the initiator on the secondary PCI bus 118 to the primary PCI
The signal echoed to the target on bus 112 is FRAM
E_s, AD [31: 0] s, C / BE [3: 0] s, and IRDY_s. Primary PC
The signals echoed from the I bus 112 to the initiator on the secondary PCI bus 118 are TRDY_p, STOP_p, and DEVSEL_p.

Next, referring to FIGS. 3 and 4, the primary P
A timing diagram for two single DWORD transactions starting on the CI bus 112 and directed to the secondary PCI bus 118 is illustrated. The first transaction is a write transaction positively claimed by a device on the secondary bus 118 using intermediate timing, and the second transaction is a sub-transaction on the primary bus 112 and the secondary bus 118. Active read transaction. In the following drawings, as shown in FIG. 2, signal names suffixed with a lower case “p” indicate the primary PCI bus 11.
The signal of the second PCI bus 118 is a signal of the secondary PCI bus 118 with the signal name ending with a small letter “s”. Broken circles indicate a turn-around cycle, as defined in the PCI specification. In response to a transaction initiated on the primary PCI bus 112, the PCI repeater 116
FRAME_s, AD [31: 0] s, and C / BE [3: 0] s are asserted on the CI bus 118 with a delay of one clock (clocks 2 and 8). IRDY_ is also the secondary PCI at clocks 3 and 9.
Echoed on bus 118. Although not shown,
Other master signals, such as the LOCK_ and IDSEL signals, are also echoed on the secondary PCI bus 118 as needed.

The PCI repeater 116 senses DEVSEL_p deasserted at clocks 5 and 11, and therefore receives cycles using the subtractive decode timing instead of the secondary PCI bus 118. For a write transaction, once DEVSEL_s has been sampled low (clock 5), the PCI repeater 116 will generate a slave signal (DEVSEL_s, TRDY_s, STOP).
_s) is copied from the secondary PCI bus 118 to the primary PCI bus 112. When PCI repeater 116 senses that DEVSEL_s and TRDY_s are asserted low (clock 5), IRDY_s is deasserted and completes the transaction on secondary PCI bus 118. The transaction is performed on the primary PCI bus 11
In 2, the operation is completed with a delay of one clock (clock 6). DE
Echoing VSEL_s and TRDY_s onto the primary PCI bus 112 ensures that the master issue has ultimate responsibility for performing the cycle. For a read cycle, the PCI repeater 116
When detecting that DEVSEL_s is asserted (clock 13), the slave signals (DEVSEL_s, TRDY_s, STOP_
s, AD [31: 0] s), the status of the secondary PCI bus 118
To the primary PCI bus 112. PCI repeater 116 preferably also does not post such data transfers. The data transfer is a single data transfer
Consists of phases. This simplifies the design of the PCI repeater 116 and allows the repeater to back out of any transfers retried by the target. PCI repeater 116
Is 2 clocks in addition to the target latency.

Referring now to FIGS. 5 and 6, there is illustrated a target disconnect or disconnect write transaction followed by a target retry read transaction. Primary PCI
In response to a write transaction initiated on bus 112, PCI repeater 116 responds to FRAME_s, AD [31:
0] s and C / BE [3: 0] s are asserted on the secondary PCI bus 118 one clock later (clocks 2 and 8). IRDY
The assertion of _p is also echoed on the secondary PCI bus 118 at clocks 3 and 9. The PCI repeater 116 senses that DEVSEL_p remains deasserted at clocks 5 and 11, and therefore receives the transaction using the subtractive decode timing instead of the secondary PCI bus 118. For the write cycle, when DEVSEL_s is sampled and asserted (clock 5), the PCI repeater 116 transmits the slave signals (DEVSEL_s, TRDY_s, ST).
The status of (OP_s) is copied from the secondary PCI bus 118 to the primary PCI bus 112 (clock 6). Secondary P
Write transactions blocked on the CI bus 118 are also blocked on the primary PCI bus 112 because the STOP_p signal is driven to the primary simultaneously with TRDY_p. Waiting for DEVSEL_s and TRDY_s before receiving data on the primary PCI bus 112 ensures that the master startup has ultimate responsibility for executing the transaction.

For a read transaction, P
When the CI repeater 116 senses that DEVSEL_s is asserted (clock 13), the slave signal (AD)
[31: 0] s, DEVSEL_s, TRDY_s, STOP_s) status are copied from the secondary PCI bus 118 to the primary PCI bus 112 (clock 14). The retried transaction on the secondary PCI bus 118 is also retried on the primary PCI bus 112, with STOP_p being driven to the primary at the same time as TRDY_p being negated.

Referring now to FIGS. 7 and 8, a downstream burst write transaction is illustrated. A write burst through the PCI repeater 116 is accomplished by receiving burst data with zero wait states when a transfer is received by the target. Since both IRDY_p and FRAME_p are asserted, the PCI repeater 116
At clock 3, a burst sequence is sensed.
Since this transaction is a burst write transaction, the repeater does not assert IRDY_s at clock 3 as in a single DWORD transaction. Instead, the PCI repeater 116
Asserts IRDY_s on the secondary PCI bus 118,
PCI repeater 116 uses subtractive decode timing at clock 5 on primary PCI bus 112 to delay until clock 6, which is the clock after receiving the first data transaction. This delay causes the PCI repeater 116 to enable the byte of the next transaction in time for the PCI specification (this is possible at clock 8, the first clock after TRDY_p is asserted). Is necessary to guarantee

In response to a transaction initiated on the primary PCI bus 112, the PCI repeater 116 sends a FRAME_s, AD [31: 0] s, C / BE on the secondary PCI bus 118.
[3: 0] s is asserted with a delay of one clock (clock 2). The request / grant (request / grant) signal pair (REQ1_ / GNT1_) corresponds to the primary master requesting / granting access to the bus 112. PC
I-repeater 116 senses that DEVSEL_p is deasserted at clock 5 and therefore clock 5
By asserting DEVSEL_p on the primary PCI bus 112 at, instead of the secondary PCI bus 118,
Decode the transaction subtractively.
On the secondary PCI bus 118, the target 120 decodes the address and command using intermediate decode timing, and asserts DEVSEL_s and TRDY_s at clock four. On the other hand, the PCI repeater 116 senses the assertion of DEVSEL_s and TRDY_s, echoes TRDY_p one clock later (clock 5), and starts a subsequent data transaction. Although intermediate decode timing is illustrated on the secondary PCI bus 118, any timing that has the effect of making the first data transaction longer is supported. PCI repeater 116 receives the data without waiting. If the target 120 cannot receive data without waiting, the PCI
The repeater 116 writes data to the
The buffer is stored in the buffer 210. The secondary transports data at a speed limited to the speed of the target.

If there is a speed difference between the initiator and the target, the PCI repeater 116 may have unfinished cycles in its write posting buffer 210. PCI repeater 1
If the bus master initiates another transaction before 16 has emptied its write posting buffer, PCI repeater 116 waits until its write posting buffer 210 has been emptied before the secondary PCI bus 1
18 may not yield and a deadlock condition may occur. Thus, according to the preferred embodiment, P
To prevent the initiator from acquiring the primary PCI bus 112 while the CI repeater 116 is busy, the PCI repeater 116
At the same time, while the burst sequence on the secondary PCI bus 118 is being terminated, it is notified that the grant (permission) of the primary PCI bus 112 needs to be stopped. At the same time, the repeater does not relinquish the secondary PCI bus 118 until its write posting buffer 210 is emptied, so that no other initiator will
8 cannot be accessed. The sideband signal No More Grant (NOMOGNTS_) is
Then, the grant request is forcibly stopped. NOMO
While the GNTS_ signal is asserted, the arbiter 111
Is the grant signal for all pending, for example, GN
Deassert T1. Burst sequence is secondary PC
Upon completion on the I bus 118 (clock 10), the PCI
Repeater 116 deasserts the NOMOGNTS_ signal. N
After the OMOGNTS_ signal is deasserted, the PCI arbiter 111 can freely issue a grant signal again.

At clock 6, first data is received at the repeater primary, thereby enabling data and byte enables for the next transaction. The PCI repeater 116 then asserts IRDY_s so that a write data transfer can occur. The write transfer continues until the initiator is terminated or shut off by the PCI repeater 116 asserting STOP_p, as shown by clock 9 in FIGS. The STOP_p signal is asserted when the write posting buffer approaches its limit, as in this example. The PCI repeater 116 adds additional latency (delay) to the transaction, but the burst rate approaches the limit of the PCI bus.

Next, referring to FIG. 9 and FIG.
A prior art burst read transaction attempt between a master on a primary PCI bus, such as I bus 112, and a target on a secondary PCI bus, such as secondary PCI bus 118, is illustrated. The dashed line indicates an undesired condition, which is solved by the invention. If a master on primary PCI bus 112 attempts to read multiple DWORDs across PCI repeater 116 (or a repeater according to the prior art), PCI repeater 116 will respond after a single data phase (clock 7). Attempt to end the transaction. This is because the PCI repeater 116 does not have the next set of byte enables from the requesting master. The master must then perform another transaction to read the remaining data.
Thus, a transaction is broken down into multiple single data transfers.

FIGS. 9 and 10 also show the secondary bus grant (SBGNT_) signal. This signal is provided by an arbiter, such as arbiter 111, to enable a secondary bus arbiter, such as secondary bus arbiter 206. Normally, the SBGNT_ signal is asserted at clock 2, allowing the secondary arbiter to issue a grant such as GNT2_. Thus, the secondary PCI bus 118
Completes the transaction (clock 5), GNT2
Secondary bus asserting request corresponding to _
The device will have a secondary PCI bus (clock 6). Due to the inherent latency (delay) of PCI repeater 116 (and prior art repeaters), transactions on secondary PCI bus 118
It may start before the bus 112 is ready to receive the echoed transaction (clock 6). This state is as follows in clock 6
This is indicated by the dashed transaction starting on the CI bus 118.

In order to prevent this problem from occurring, the PCI repeater 116 of the present invention uses a PCI repeater 116.
Detects a memory read command, the NOMOGN
Assert the TS_ signal (clock 3) and FRAME_p remains asserted to indicate that the master on primary PCI bus 112 wants to burst the read transaction. NOMOGNTS_ signal is PCI repeater 1
16 remain asserted (TRDY_p and STOP_p) until 16 signals the master on primary PCI bus 112 to shut down.
Is asserted at clock 6). This prevents arbiters 111 and 206 from asserting the grant signal until the transaction is completed on both buses. If repeater 116 detects that the master and target are on the same bus (ie, primary PCI bus 112), DEVSEL_p is asserted (not shown) and arbiter 111 issues a grant as normal. As soon as it is possible to pipeline, it deasserts the NOMOGNTS_ signal instead. In this manner, the PCI repeater 116 handles read transactions to non-prefetchable areas where the read transaction has been broken down into multiple single data transfers.

Referring now to FIGS. 11 and 12, another problem of the prior art PCI repeater with respect to memory read lines and multiple PCI commands for memory read is illustrated. The memory read line and the memory read multiple command are used to access data in a prefetchable address range. 11 and 12 illustrate the case where the master on the primary PCI bus initiates a memory read line or multiple memory read commands. Prior art PCI repeaters start the cycle on the secondary side and de-asserted FRAM
Continue to request new data until E_p is sampled. The target adds a wait state to the transfer, thus
While the primary PCI bus is free to initiate another cycle targeting a slave on that primary PCI bus,
A problem arises when keeping the secondary PCI bus busy (clock 10). In this case, the prior art PCI repeater will miss the entire transaction since the transaction on the secondary PCI bus does not end until clock 12.

Referring now to FIGS. 9A and 9B, a downstream system with arbiter intervention according to the preferred embodiment is described.
A burst read sequence is illustrated. This solves the problems shown in FIGS. Master
A memory read line or multiple memory read commands are initiated on primary PCI bus 112 toward a target on secondary PCI bus 118. PCI repeater 1
16 initiates a command on the secondary PCI bus 118 at clock two. The requesting master byte enable, which can read all bytes and read (ie, prefetch) before the master on the primary PCI bus 112, and the PCI repeater 116 independent of the byte enable Set to all zeros. At clock 5, the PCI repeater 116 determines that the transaction is downstream, since the transaction has not been positively charged on the primary PCI bus 112,
It asserts the NOMOGNTS_ signal to notify the PCI arbiter 111, and reconciles the current grant or grant (GNT1_) and all subsequent grants on the primary PCI bus 112 until the secondary PCI bus 118 completes its current transaction. Remove. The NOMOGNTS_ signal is deasserted at clock 12 when the read ends on the secondary PCI bus 118.

Read prefetch terminates on secondary PCI bus 118 as soon as PCI repeater 116 detects the last data phase on primary PCI bus 112. The last data phase is the FR at clock 8
Notified by deassertion of AME_p and IRDY_p at clock 9. At clock 9, the PCI repeater 11
6 indicates that when the FRAME_s signal is deasserted at clock 9, its last data phase is the secondary PCI bus 1
18 to end. In this way, the master on primary PCI bus 112 will send the PCI repeater the next DWORD from the target on secondary PCI bus 118.
While the data is still being read, the reading is terminated. PC
In order not to violate the I protocol, the PCI repeater
C / BE [3: 0] s and IRDY until the last data phase on secondary PCI bus 118 ends at clock 12.
_s signal is held on the secondary PCI bus 118. After the PCI repeater 116 detects the last data phase, it repeats AD [31: 0] p and C at the end of the secondary PCI bus 118 read transaction.
Drive the / BE [3: 0] p bus to a valid state (clock 1
1 to clock 12). Therefore, PCI repeater 1
16 tries to precede the requesting master by requesting more data. Unused data is
Discarded by PCI repeater 116.

Upstream Transaction An upstream transaction is a secondary PCI
A transaction that starts on bus 118 and targets devices on primary PCI bus 112. P
CI repeaters process upstream transactions in the same way as downstream transactions, with a few exceptions. PCI
Repeater 116 does not respond to an upstream configuration cycle.

A problem facing the PCI repeater 116 is how to determine which cycle is pointing upstream and which cycle is pointing downstream. Two solutions are possible. In the first method, the subtractive decode logic of the PCI / ISA bridge is enabled only during downstream transactions.
PCI repeater 116 broadcasts all transactions initiated on secondary PCI bus 118 to primary PCI bus 112. The transaction is
If the device on secondary PCI bus 118 is not positively charged, repeater 116 charges it subtractively. In this way,
Transactions are sent upstream,
Devices on secondary PCI bus 118 and ISA bus 128
Peer-to-peer transactions with the above device
I can not use it. In the second method, the PCI repeater 116
Stops operating on the secondary PCI bus 118 and echoes the transaction to the primary PCI bus 112.
If the target is on the primary PCI bus 112, the target charges the transaction positively. If the transaction is not positively charged by the primary bus PCI agent,
PCI repeater 116 bills the transaction subtractively and runs it on secondary PCI bus 118. PC if the target is an ISA device
The I-ISA bridge 122 subtracts out transactions from the secondary PCI bus 118.
This preferred method has the advantage of handling a hierarchy of buses.

FIGS. 15 to 22 correspond to the first method described above. The principles shown in these figures and described below apply equally to memory or I / O transactions. Referring to FIGS. 15 and 16, there are illustrated two single DWORD transactions beginning on the secondary PCI bus 118 and ending on the primary PCI bus 112. The first transaction is a write transaction positively claimed by the device on the primary PCI bus 112 using intermediate decode timing, and the second transaction is claimed using intermediate decode timing. Read transaction. The first upstream transaction starts at clock 1 on the secondary PCI bus 118. The transaction is echoed upstream at clock 2 towards the primary PCI bus 112. The PCI repeater 116 detects that FRAME_s is deasserted at clock 3, determines that this is a single data transaction, and asserts IRDY_p to allow this write transaction to complete. Transactions are decoded positively on primary PCI bus 112 at clock 4 with intermediate decode timing. Immediately after sampling the DEVSEL_p asserted at clock 5, the repeater 116 changes the state of DEVSEL_p to the remaining slave signal (TR
Along with DY_p and STOP_p) to DEVSEL_s.

The upstream read transaction follows in a similar manner. The transaction starts on the secondary PCI bus 118 at clock 7 and is echoed on clock 8 to the primary PCI bus 112.
The transaction is the primary PCI
Received on bus 112 and at clock 11 DEVSEL
_s is echoed to the secondary PCI bus 118. Clock 1
At 2, the target places the requested data on the primary PCI bus 112, asserts TRDY_p, and ends the transaction. At clock 13, AD [3
1: 0] p and TRDY_p are echoed to the secondary PCI bus 118.

Referring now to FIGS. 17 and 18, a target disconnect write transaction and a subsequent target retry read transaction are shown. The PCI repeater 116 has a single data
Because it does not post transactions, it handles upstream target disconnects and retries in the same way it handles downstream transactions. At clock 4, the target on primary PCI bus 112 announces the shutdown, and at clock 5, the secondary PCI bus 11
8 is echoed to the initiator. Similarly, a retry is announced at clock 12 by the target on primary PCI bus 112, which is echoed at clock 13 by PCI repeater 116 to the initiator on secondary PCI bus 118.

Next, referring to FIGS. 19 to 22, an upstream burst write sequence and an upstream read sequence are shown, respectively. Upstream burst transactions allow the arbiter 111 to provide PCI buses 112 and 1 to any agent until the current transaction ends.
Similar to a downstream burst transaction in that it must not grant 18. This is accomplished by asserting the NOMOGNTS_ signal as soon as the PCI repeater 116 determines that the transaction initiated on the secondary PCI bus 118 has been received by the target on the primary PCI bus 112. The target on the primary PCI bus 112, as shown at clock 3,
Using the timing, DEVSEL_p is asserted to instruct receipt of a transaction. NOMOGN
The TS_ signal remains asserted until the transaction ends on the primary PCI bus 112, as shown at clocks 4-11. In these examples,
The NOMOGNTS_ signal remains asserted while the target on the primary PCI bus 112 inserts a wait state before receiving the last write cycle.

FIGS. 23 to 28 correspond to the above-described second method. 23 and 24 illustrate the primary PCI bus 112.
Figure 9 illustrates an upstream single data phase write transaction positively charged above. FIGS. 25 and 26 illustrate upstream single data phase write transactions that are not positively charged on primary PCI bus 112 or secondary PCI bus 118 but are subtractively charged on ISA bus 128. ing. The principles shown in these figures apply equally to memory and I / O transactions. In FIGS. 23 and 24, the transaction starts on the secondary PCI bus 118 at clock 1 and is echoed on the primary PCI bus 112 at clock 2.

In order to provide sufficient response time for the primary bus target in the future, the clock (CLK) on the secondary PCI bus 118 is set to two clocks at the end of clock 2 by the clock disable (CLK_DIS) signal. Stopped during PCI clock cycle. The two clock delay allows the transaction to be claimed by the primary PCI bus 112 target or the secondary PCI bus 118 target before the ISA-PCI bridge 122 subtractively subtracts the transaction. Primary bus agent is clock 3, 4 or 5
In, a transaction can be requested by asserting DEVSEL_p. The secondary bus agent can claim the transaction by asserting DEVSEL_s at clock 2, 5, or 6.

In FIGS. 23 and 24, the primary bus target asserts DEVSEL_p at clock 5 to request a transaction at a slow decode timing. At clock 6, the PCI repeater senses the assertion of DEVSEL_p, and DEVSEL_p and TRDY_p
On the secondary PCI bus 118, and the transaction ends on the secondary PCI bus 118. That is, it is not subtractively decoded by the ISA / PCI bridge 122.

Referring now to FIGS. 25 and 26, at clock 1 a transaction starts on the secondary PCI bus 118 and at clock 2 the secondary PCI bus 11
8 and the conventional decode logic of the primary bus unit 200 has a secondary PCI address range.
It is possible to determine whether to correspond to a target on the bus 118. Secondary PCI bus clock (CL
K) stops again for two clocks, as in the case of FIGS. However, in this case, the transaction is not claimed on the primary PCI bus 112. At clock 6, the PCI repeater 116
Detects the negated state of _p and sets the target to the primary PC
It determines that it is not on the I bus 112, asserts DEVSEL_p, and requests a subtractive transaction from the primary PCI bus 112. Secondary PCI bus 118
Above, the transaction is still unclaimed. At clock 7, the PCI repeater 116
DEVSEL_s has not been asserted yet, and DEVSEL_p
Is asserted at the subtractive decode timing, and therefore the ISA bus 128
Judge that there is a target above. At clock 7, I
The SA / PCI bridge senses that DEVSEL_s has not yet been asserted and asserts DEVSEL_s to claim the transaction subtractively. The transaction ends normally at clock 9. In this manner, the target of the transaction is determined transparently without requiring that any special upstream address decode logic be included in the PCI repeater 116.

Referring now to FIGS. 27 and 28, there is shown a burst read sequence that can be prefetched upstream. In this second method, the upstream burst transaction is a downstream burst transaction in that arbiter 111 must not grant PCI buses 112 and 118 to any agent until the current transaction is completed. Similar to a transaction. The transaction starts on the secondary PCI bus 118 at clock 1 and is echoed on the secondary PCI bus 118 at clock 2 to determine if the target is on the primary bus. Byte enable C / BE [3: 0] p is forced to zero, thereby causing a prefetch. IRDY_s is
At clock 2 it is asserted by the initiator on the secondary PCI bus 118 and at clock 3 it is echoed on the primary PCI bus 112.

While a future target on primary PCI bus 112 is decoding a transaction, the PCI clock (CLK) on the secondary PCI bus is stopped by PCI repeater 116 for two clocks. At clock 5, the secondary PCI bus 118 is started again. The target on the secondary PCI bus 118 receives the transaction by asserting DEVSEL_p at clock 4 and the PCI repeater 116
At clock 5, the signal (DEVSEL_s) is echoed onto the secondary PCI bus 118. Thus, the subtractive decode agent of the secondary PCI bus 118 assumes that the transaction has been positively charged on the secondary PCI bus 118. At clock 5, PCI repeater 116 senses that FRAME_p and DEVSEL_p are asserted, and responds NOMO
Arbiter 111 asserts GNTS_ until the current sequence ends on primary PCI bus 112
Prevents granting the I bus to the initiator of the secondary bus. At clock 9, the PCI repeater 116
It senses the completion of the burst read sequence and, in response, deasserts the NOMOGNTS_ signal.

If detection of a burst was not solicited by the target on primary PCI bus 112, the secondary PC
The sequence may be claimed by the target on the I bus 118. PCI repeater 1 by first detecting the transaction upstream to decode the signal on the primary bus before the transaction on the secondary bus is performed (run)
16 is a unique address decoding / decoding of the PCI device.
Logic can be used. Therefore, PCI
Repeater 116 does not require downstream or upstream decode logic to process these transactions.

FIG. 29 shows a third embodiment which is another preferred example of the PCI repeater 116. In particular, in this embodiment, the primary PCI bus 118
It includes logic to determine which transaction to send to CI bus 112. As described above, the primary bus unit 200 and the secondary bus unit 202 are configured to process the reception and transmission of both the master cycle and the slave cycle. Additionally, PCI repeater 116 includes snoop logic 212 for snooping configuration cycles on primary PCI bus 116.

A configuration cycle is a transaction that specifies a configuration address space for writing to or reading from a configuration register. Each PCI
Device 114 is required by the PCI local bus specification to support a minimal set of configuration registers. The configuration register contains the PCI device 114
Defines at least one of a memory range and an I / O space address range for responding. Therefore,
The PCI device 114 is a programmable location. Configuration cycles and configuration registers are disclosed in more detail in the PCI Local Bus Specification, which is referenced in the present invention.

When the configuration cycle is snooped by snoop logic 212, the primary bus unit 200 stores the address range in address map 214. Address map 214 includes both memory and I / O space. Since the repeater typically transfers transactions from the primary PCI bus to the secondary PCI bus, snoop cycles for the primary PCI bus are distinguished by a configuration cycle that ends with a TRDY_P signal. Configuration cycles completed on the secondary PCI bus 118 are snooped (the cycle is
The data held in the configuration cycle (since it is directed to 112 on the I bus) is stored in the address map 214.

The configuration cycle is P
It is defined in the CI local bus specification, which is used at initialization and when the computer system C
This is required whenever the device 114 is mounted or unplugged from the system C. In this manner, address map 214 is implemented on snoop logic 212 and primary bus unit 200 without the need for specific configuration software. When the address map 214 is equipped, the secondary PC
The transaction directed to the I bus 118 is shown in FIG.
28 can be decoded positively as compared with the case described with reference to FIG. The secondary bus unit 202 responds to secondary bus transactions by searching an address map and finding the address
Determine if it is for a PCI device 114 coupled to bus 112. If so, the transaction is requested positive and the primary PCI bus 11
2 is transmitted. In the opposite case, the transaction remains on the secondary PCI bus and is charged subtractively, that is, positively charged by the PCI device 114 coupled to the secondary PCI bus 118. In this manner, PCI repeater 116 can forward transactions according to address map 214 without requiring system intervention.

Another advantage of having the address map 214 in the PCI repeater 116 is that the primary P
Transactions destined for CI bus 112 no longer need to be subtractively requested on the primary side of PCI repeater 116. When a transaction is initiated on primary PCI bus 112, primary bus unit 200 searches address map 214 to determine whether the target device is a device coupled to primary PCI bus 112. . If so, send the transaction on the primary bus.
Otherwise, the transaction is positively charged to send to the secondary PCI bus 118.

FIG. 30 is a circuit diagram of the snoop detection logic 212. The harm snoop detection logic 212 includes an AND gate 220 to which bits 1-3 of the command / byte enable (C / BE #) signal are input. Bit 2 is inverted, so that C / BE =
In the case of [101], the output of the AND gate 220 is high,
That is, it is asserted. The output of the AND gate 220 is A
The signal is input to the non-inverting input terminal of the ND gate 222. FR
The AME # signal is supplied to the D input terminal of flip-flop 224. The flip-flop is clocked by a PCI clock signal to provide a synchronous frame (SFRAME #) signal. The SFRAME # signal is a one-shot FRAME # signal supplied when the FRAME # signal is first asserted. F
The RAME # signal is supplied to a second input terminal (inverting input terminal) of the AND gate 22, and the SFRAME # signal is
The signal is supplied to a third input terminal (non-inverting input terminal) of the AND gate 222. The output of AND gate 222 indicates when a configuration cycle is detected (SN
OOP_CONFIG), high or asserted.

The SNOOP_CONFIG signal is the primary P
Only the configuration cycles of the devices coupled to CI bus 112 are ensured with the TRDY_P signal as stored in the address map. I /
Both O-space addresses and memory space addresses are stored in the address map. Therefore, the system
It will be apparent that there has been provided a novel apparatus and method for mediating, ie, repeating, PCI transactions via a bridge transparent to software.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a computer system according to a preferred embodiment.

FIG. 2 is a block diagram illustrating a PCI repeater according to a preferred embodiment.

FIG. 3 is a timing diagram illustrating a downstream single data phase write transaction followed by a downstream single data phase read transaction.

FIG. 4 is a timing diagram illustrating a downstream single data phase write transaction followed by a downstream single data phase read transaction.

FIG. 5 is a timing diagram illustrating a target disconnect write transaction and a subsequent target retry read transaction.

FIG. 6 is a timing diagram illustrating a target disconnect write transaction and a subsequent target retry read transaction.

FIG. 7 is a timing diagram illustrating a downstream burst write sequence.

FIG. 8 is a timing diagram illustrating a downstream burst write sequence.

FIG. 9 is a timing diagram illustrating a downstream burst read sequence.

FIG. 10 is a timing diagram illustrating a downstream burst read sequence.

FIG. 11 is a timing diagram illustrating a downstream burst read sequence without arbiter intervention.

FIG. 12 is a timing diagram illustrating a downstream burst read sequence without arbiter intervention.

FIG. 13 is a timing diagram illustrating a downstream burst read sequence with arbiter intervention.

FIG. 14 is a timing diagram illustrating a downstream burst read sequence with arbiter intervention.

FIG. 15 is a timing diagram illustrating an upstream single data phase write transaction and a subsequent upstream single data phase read transaction.

FIG. 16 is a timing diagram illustrating an upstream single data phase write transaction followed by an upstream single data phase read transaction.

FIG. 17 is a timing diagram illustrating a target disconnect write transaction followed by an upstream read retry transaction.

FIG. 18 is a timing diagram illustrating a target disconnect write transaction followed by an upstream read retry transaction.

FIG. 19 is a timing diagram illustrating an upstream burst write sequence.

FIG. 20 is a timing diagram illustrating an upstream burst write sequence.

FIG. 21 is a timing diagram illustrating an upstream burst read sequence.

FIG. 22 is a timing diagram illustrating an upstream burst read sequence.

FIG. 23 is a timing diagram illustrating a positively charged upstream single-phase write transaction on the primary bus.

FIG. 24 is a timing diagram illustrating a positively charged upstream single-phase write transaction on the primary bus.

FIG. 25 is a timing diagram illustrating an upstream single data write transaction echoed on the primary bus and subtractively claimed on the secondary bus.

FIG. 26 is a timing diagram illustrating an upstream single data write transaction echoed on the primary bus and subtractively claimed on the secondary bus.

FIG. 27: Upstream billing on primary bus
FIG. 4 is a timing chart illustrating a burst read sequence.

FIG. 28: Upstream billing on primary bus
FIG. 4 is a timing chart illustrating a burst read sequence.

FIG. 29 is a block diagram illustrating the logic of a PCI repeater snooping a configuration cycle.

FIG. 30 is a block diagram illustrating another logic for snooping a configuration cycle.

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Claims (14)

[Claims] 1. A device coupled to a first bus and a second bus.
The first and second devices each respond to one configuration cycle, and wherein each of the first and second devices responds to one configuration cycle. A transaction communication method, comprising a configuration register for holding a programmable base address written in between, wherein: (a) a configuration communicated on said first bus and including a base address; Snooping a cycle; (b) storing, in an address map, the base address included in a configuration cycle responded by a device connected to the first bus; (c). A transaction occurring on the second bus The action,
Transferring the transaction to the first bus if the transaction is intended for a device included in the address map. 2. The method of claim 1, wherein the first
A transaction communication method, wherein the configuration cycle responded by the device coupled to the bus is terminated using a first bus target ready signal. 3. The method of claim 1 wherein step (c) further comprises the step of: positively claiming said bus transaction on said second bus. 4. The transaction communication method according to claim 1, wherein steps (a) and (b) are repeated for each configured device. 5. The transaction communication method according to claim 1, wherein said base address is a memory address. 6. The transaction communication method according to claim 1, wherein said base address is an input / output space address. 7. A bus repeater coupling a first bus to which a first device is coupled to a second bus to which a second device is coupled, wherein said bus transaction including an address is performed by said bus repeater. A first bus unit communicating with a first bus; and a snoop logic for snooping a configuration cycle on the first bus, wherein the first bus unit communicates with the first bus.
The device coupled to the bus
Snoop logic for providing a snoop indication when acknowledging a configuration cycle including data indicating the range; and receiving the device address range from the first bus unit and responding to the snoop indication. An address map storing the device address range; and a second bus unit communicating a bus transaction between the second bus and the first bus unit, wherein the second bus unit communicates a bus transaction between the second bus and the first bus unit. A second bus unit that positively claims and repeats the bus transaction if the address of the bus transaction from the second bus to the first bus is included in the address map. A characteristic bus repeater. 8. The bus repeater according to claim 7, wherein said first bus unit transmits a bus transaction generated on said first bus to a device coupled to said second bus. A bus repeater configured to request if an address corresponding to the bus transaction is not included in the address map. 9. The bus repeater according to claim 7, wherein said first bus unit is operative to subtractively request a bus transaction for said second bus. repeater. 10. The bus repeater according to claim 7, wherein said second bus unit performs a bus transaction from said second bus to said first bus, and said bus transaction includes said address transaction. A bus repeater that operates so as not to be charged if not included in the map. 11. A computer system, comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; and a first coupled to the first bus. One or more devices, one of which is a hard disk system, a second bus, coupled to the second bus, one of which is the first bus and the second bus. One or more devices that are repeaters coupled to and from a second bus, the repeater communicating a bus transaction including an address to and from the first bus. A unit and a device that snoops a configuration cycle on the first bus, wherein a device coupled to the first bus includes a configuration that includes data indicating a device address range. Snoop logic for providing a snoop indication when acknowledging a configuration cycle; receiving the device address range from the first bus unit; and responding to the snoop indication, An address map for storing a range; and a second bus unit operable to communicate bus transactions with said second bus and said first bus unit, wherein said second bus unit operates from said second bus. A second bus bus that positively charges and reflects a bus transaction to the first bus if the address of the bus transaction is included in the address map;
A computer system comprising: a unit; 12. The computer system according to claim 11, wherein said first bus unit is connected to said second bus unit.
Is configured to positively charge a bus transaction occurring on the first bus for a device coupled to the other bus if the address corresponding to the bus transaction is not included in the address map. A computer system characterized by: 13. The computer system according to claim 11, wherein said first bus unit is connected to said second bus unit.
A computer system configured to subtractively charge a bus transaction for a given bus. 14. The computer system according to claim 11, wherein said second bus unit comprises said second bus unit.
A bus transaction from the first bus to the first bus if the bus transaction is not included in the address map.