JPH1185671A - Direct memory access controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily restart direct memory access(DMA) transfer from a following address after the DMA transfer is interrupted by forced end or the like by switching the selection of whether the transfer is to be restarted or not while using the address of a transfer resource just after the interruption of transfer, the address of the transfer destination and the number of remaining transfer bytes. SOLUTION: When transferring data for first one transfer unit by restarting DMA transfer after the temporary interruption, a switch 20 is turned on in its read cycle, and the starting address of the transfer source held in a SARL 8 is outputted. A transfer source memory 2 is accessed while using this starting address of the transfer source, and the data for one transfer unit are read from the starting address of the transfer source in the transfer source memory 2. Therefore, when a DMA permit bit and a DMA request flag are set after the DMA transfer is interrupted in the middle by the forced end or the like, the DMA transfer is restarted from the next transfer address of interruption without resetting a DMA transfer parameter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer, which requires a large amount of high-speed data exchange between memories.
When controlling OA (office automation) equipment such as a copying machine and a facsimile, direct memory access (e.g., a microcomputer) that controls the transfer of data without the intervention of a central processing unit (CPU). (Hereinafter referred to as DMA) controller.

[0002]

2. Description of the Related Art FIGS. 6 and 7 are explanatory diagrams showing the operation of a conventional DMA controller. FIG. 6 shows the operation of a DMA controller in a first transfer cycle, and FIG. The basic operation of the DMA controller in a cycle is shown. FIG.
FIGS. 7A and 7A show the operation in the read cycle, and FIGS. 6B and 7B show the operation in the write cycle. In these figures, 1 is a DMA controller, 2 is a transfer source memory, and 3 is a transfer destination memory. 4 is a transfer source address register, 5 is a transfer destination address register, 6 is a transfer counter register, 7 is a register portion (hereinafter referred to as SAR) of the transfer source address register 4, and 8 is a latch portion (hereinafter, referred to as SAR).
SARL), 9 is a register section (hereinafter, referred to as DAR) of the transfer destination address register 5, 10 is a latch section (hereinafter, referred to as DARL), and 11 is a transfer counter register 6
, A latch unit (hereinafter, TCRL). Further, 13 is an incrementer / decrementer, 14 is a decrementer, 15
Is a DMA latch.

Next, the operation will be described. When a DMA request is input in the DMA enabled state, the DMA controller 1
A transfer is started. When performing a DMA transfer by the DMA controller 1 in order to transfer a large amount of data between the transfer source memory 2 and the transfer destination memory 3 at a high speed, first, a transfer source start address of the transfer source memory 2 and a transfer destination memory 3 is specified in the source address register 4, the destination address register 5, or the transfer counter register 6, and the values are respectively assigned to the SAR 7,
Write to the DAR9 or TCR11, and write the respective SARL8, DARL10, or TCRL.
12 is held.

Here, in order to transfer the data of the first transfer unit, first, in a read cycle, FIG.
As shown in (1) in (a), the transfer source memory 2 is accessed using the transfer source start address held in the SARL 8, and one transfer unit read from the transfer source start address of the transfer source memory 2 is read. As shown by (2) in FIG.
The data is sent to the DMA latch 15 and temporarily held. At that time,
The number of transfer bytes held in the TCRL 12 is sent to the decrementer 14 as shown by (3) in the figure and updated, and as shown by (4) in this figure, this decrementer 1
The value updated in 4 is stored in the TCR 11 as the number of remaining bytes of the data to be transferred. Similarly, as shown by (5) in the figure, the transfer source start address held in the SARL 8 is sent to the incrementer / decrementer 13 and updated, and the incrementer / decrementer 13 is updated.
Is updated and stored in the SAR 7 as the transfer source address, as indicated by (6) in FIG.

Next, in a write cycle, FIG.
As shown in (1) in (b), the transfer destination memory 3 is accessed using the transfer start address held in the DARL 10, and is read from the transfer start address of the transfer source memory 2 and the DMA is read. 1 temporarily held by the latch 15
The data in the transfer unit is written to the specified transfer destination start address in the transfer destination memory 3 as shown by (2) in FIG. At this time, as shown by (3) in the figure, the transfer destination start address held in the DARL 10 is sent to the incrementer / decrementer 13 to be updated, and the value updated by the incrementer / decrementer 13 is transferred to the transfer destination. The address is stored in the DAR 9 as shown by (4) in FIG.

When transferring the data of the second transfer unit and thereafter in one transfer unit, first, in the read cycle, the data shown in FIG.
As shown by (1) in (a), the source memory 2 is accessed using the source address held in the SAR 7, and the data of one transfer unit read from the source address of the source memory 2 is read. As shown by (2) in the figure, the data is sent to the DMA latch 15 and temporarily stored. At that time, TCR11
The remaining number of bytes of data to be transferred held in
The transfer source address which is updated by the decrementer 14 as shown by (3) in the drawing and is held in the SAR 7 is updated by the incrementer / decrementer 13 as shown by (4) in the drawing.

Next, in a write cycle, FIG.
As shown in (1) in (b), the transfer destination memory 3 is accessed using the transfer destination address held in the DAR 9, and is read from the transfer source address of the transfer source memory 2 and the DM is read.
The data of one transfer unit temporarily held in the A latch 15 is written to the specified transfer destination address of the transfer destination memory 3 as shown by (2) in FIG. At that time, the transfer destination address held in the DAR 9 is updated by the incrementer / decrementer 13, as shown by (3) in FIG. When the DMA transfer is completed, the remaining transfer byte number held in the TCR 11 becomes equal to the decrementer 14
Is detected by having become "0" by the decrement by.

When the DMA transfer ends normally and when the DMA transfer is forcibly ended, the SARL8, DARL10, TCRL12
Holds the values of the transfer source start address of the transfer source memory 2, the transfer destination start address of the transfer destination memory 3, and the number of transfer bytes, which are written first before the transfer. Therefore, DMA
If you want to restart the transfer from the beginning, you do not need to reset those values.

When it is desired to resume the DMA transfer from the subsequent address after the forced termination, the contents of the transfer source address register 4, the transfer destination address register 5, and the transfer counter register 6 are read once, and the values are read again. It is necessary to rewrite the source address register 4, the destination address register 5, and the transfer counter register 6 again.

That is, after the forced termination, when the contents of the transfer source address register 4, the transfer destination address register 5, and the transfer counter register 6 are read, SAR7, DAR
9. The value of the TCR 11, that is, the source address, the destination address, and the remaining number of bytes to be transferred next, can be read. When this is written in each of the transfer source address register 4, the transfer destination address register 5, and the transfer counter register 6, SAR7, DAR9, TC
At the same time as R11, SARL8, DARL10, TCRL
12 is also written. If the DMA permission bit and the DMA request flag are set in this state, the data transfer can be resumed from the continuation of the address transferred before the forced termination.

As a document describing a technique related to such a conventional DMA controller, there is, for example, Japanese Patent Application Laid-Open No. 4-306754.

[0012]

Since the conventional DMA controller is configured as described above, DMA transfer can be performed first without resetting values such as a source start address, a destination start address, and the number of transfer bytes. Can be restarted, but when the DMA transfer is forcibly terminated, if it is desired to resume the transfer from the next address, the DMA transfer is restarted only by resetting the DMA permission bit and the DMA request flag. There was a problem that it was not possible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides a DMA controller capable of easily resuming DMA transfer from a subsequent address after interrupting DMA transfer due to forced termination or the like. The purpose is to:

[0014]

According to a first aspect of the present invention, there is provided a DMA controller having a transfer parameter reset bit, and a transfer source set at the start of the DMA transfer in accordance with the setting of the transfer parameter reset bit. Selection of whether to restart the transfer using the start address, the transfer start address and the number of transfer bytes, or to restart the transfer using the transfer source address, transfer destination address and the remaining transfer byte number immediately after the transfer was interrupted Is switched.

According to a second aspect of the present invention, in the DMA controller, the DMA controller includes a transfer parameter reset bit for DMA control.
It is arranged in an empty bit of the control register.

According to the third aspect of the present invention, the DMA controller includes SAR, DAR and DMA as DMA transfer parameters such as a transfer source address, a transfer destination address, and the number of remaining transfer bytes in accordance with the setting contents of the transfer parameter reset bit. The selection of whether to output the contents of the TCR or the contents of the SARL, DARL, and TCRL is switched.

According to a fourth aspect of the present invention, in the DMA transfer termination processing cycle, the DMA controller according to the setting contents of the transfer parameter reset bit.
The values held by R, DAR and TCR are represented by S
This is to switch whether or not to transfer to ARL, DARL and TCRL.

In the DMA controller according to the present invention, in a predetermined DMA transfer mode such as a repetitive transfer mode, the SAR, DAR, and TCR always output D to D.
This is to output the value of the MA transfer parameter.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 shows D according to Embodiment 1 of the present invention.
FIG. 3 is an explanatory diagram illustrating the concept of an MA controller. In the figure, 1 is a DMA controller, 2 is a transfer source memory storing data to be subjected to DMA transfer by the DMA controller 1, and 3 is a transfer destination to which data read from the transfer source memory 2 is transferred. Memory. In the DMA controller 1, reference numeral 4 denotes a transfer source address register in which a transfer start address of the transfer source memory 2 is written at the start of the DMA transfer, and which designates a transfer source address of the transfer source memory 2. Reference numeral 5 denotes a transfer destination address register in which the transfer start address of the transfer destination memory 3 is written at the start of the DMA transfer, and specifies the transfer destination address of the transfer destination memory 3. Reference numeral 6 denotes a transfer counter register in which the number of transfer bytes of the data transferred from the transfer source memory 2 to the transfer destination memory 3 is written at the start of the DMA transfer, and counts the transfer bytes for judging the end of the DMA transfer.

7 in the transfer source address register 4 is DM
A SAR holding the transfer source address of the data to be transferred next by the A controller 1, and 8 is an SA that keeps holding the value (transfer source start address) first written in the SAR 7.
RL. The transfer source address register 4 stores these SARs
7 and SARL8. Reference numeral 9 denotes a DAR in the transfer destination address register 5, which holds a transfer destination address of data to be transferred next by the DMA controller 1. Reference numeral 10 denotes a DARL that keeps holding the value (transfer destination start address) first written in the DAR 9. The transfer destination address register 5 stores these DAR9 and DARL10
Is formed. 1 in the transfer counter register 6
Reference numeral 1 denotes a TCR holding the number of remaining bytes of data to be transferred by the DMA controller 1, and reference numeral 12 denotes a TCR.
11 is a TCRL that keeps holding the value (the number of transfer bytes) initially written to the address 11. The transfer counter register 6 is formed by these TCR11 and TCRL12.

Further, in the DMA controller 1, reference numeral 13 denotes an incrementer / decrementer for updating the contents of the SAR 7 of the transfer source address register 4 and the contents of the DAR 9 of the transfer destination address register 5 by incrementing or decrementing them. Is a decrementer for decrementing and updating the contents of the TCR 11 of the transfer counter register 6. Reference numeral 15 denotes a DMA latch for temporarily holding the transfer source data read from the transfer source memory 2 until the transfer source data is transferred to the transfer destination memory 3. These components are the same as those in the related art, which are denoted by the same reference numerals in FIGS.

Reference numeral 20 denotes a switch for turning on / off the transfer of the contents held in the SARL 8 of the transfer source address register 4 to the transfer source memory 2 and the incrementer / decrementer 13. Reference numeral 21 denotes the SAR 7 of the transfer source address register 4.
Source memory 2 and incrementer /
A switch 22 turns on / off the transfer to the decrementer 13, and a switch 22 turns on / off the transfer of the transfer source address incremented or decremented by the increment / decrementer 13 to the SAR 7. Reference numeral 23 denotes a switch for turning on / off the transfer of the contents held in the TCRL 12 of the transfer counter register 6 to the decrementer 14, and reference numeral 24 denotes the TCRS 11 of the transfer counter register 6.
Is a switch for turning on / off the transfer of the contents held in the decrementer 14 to the decrementer 14, and 25 is the TCR11 of the remaining transfer byte number decremented by the decrementer 14.
This is a switch for turning on / off the transfer to the server.

Further, reference numeral 26 denotes a DMA latch 15 for transferring data read from the transfer source memory 2 to the transfer source memory 2.
A switch 27 for turning on / off the transfer to the transfer destination memory 3;
A switch for turning on / off the transfer from the to the transfer destination memory 3. 28 is DARL1 of the transfer destination address register 5
A switch for turning on / off the transfer of the contents held in the DAR 9 of the transfer destination address register 5 to the transfer destination memory 3 and the increment / decrementer 13. Switch to turn on / off the transfer to
Reference numeral 30 denotes a transfer destination address incremented or decremented by the incrementer / decrementer 13.
A switch for turning on / off transfer to DAR9.

FIG. 2 is an explanatory diagram showing a DMA control register in which a transfer parameter reset bit is arranged. In the figure, reference numeral 40 denotes the DMA control register, and the DMA controller 1 usually has the DMA control register 40 as a register for controlling the DMA transfer. Reference numeral 41 denotes a transfer parameter reset bit allocated to the empty bit when there is an empty bit in the DMA control register 40. If there is no empty bit in the DMA control register 40, the transfer parameter reset bit 41 is arranged in one bit in another register. DMA such as transfer source address, transfer destination address, and remaining transfer byte number immediately after transfer interruption
The transfer parameters are reset, and the transfer source address, transfer destination address register 5, and transfer counter register 6 set the transfer source start address set at the start of the DMA transfer,
When resuming the interrupted DMA transfer using the transfer destination start address and the number of transfer bytes, the transfer parameter reset bit 41 is set to “0”, and the D immediately after the transfer is interrupted is set.
Using MA transfer parameters without resetting
To restart the MA transfer, the transfer parameter reset bit 41 is set to "1".

Next, the operation will be described. When the DMA permission bit and the DMA request flag are set and a DMA request is input in the DMA permission state, the DMA controller 1 starts the DMA transfer, and firstly, the transfer source start address of the transfer source memory 2 and the transfer of the transfer destination memory 3. First starting address, and DM
A The number of transfer bytes of data to be transferred is designated in the transfer source address register 4, the transfer destination address register 5, or the transfer counter register 6, respectively. The transfer source address register 4 stores the specified transfer source start address in SAR7.
And the value is held in SARL8. Similarly, the transfer destination address register 5 writes the designated transfer start address into DAR9, and stores the value in DARL10.
And the transfer counter register 6 writes the specified number of transfer bytes into the TCR 11, and the value TCRL1
Hold at 2.

Here, the basic operation of the DMA controller 1 when transferring data in one transfer unit is that data read from the transfer source memory 2 in the read cycle is temporarily held in the DMA latch 15. And then
In the write cycle, the contents of the DMA latch 15 are written to the transfer destination memory, and two-bus cycle transfer is performed.

First, the transfer parameter reset bit 41
Is set to “0”. DMA
When the transfer is suspended and then resumed to transfer the data of the first transfer unit, in the read cycle, the switch 20 is turned on and the transfer source start address held in the SARL 8 is output. You. The transfer source memory 2 is accessed using the transfer source start address, and data of one transfer unit is read from the transfer source start address of the transfer source memory 2. At that time, the switch 26 is turned on, and the data read from the transfer source memory 2 is transferred to the DMA latch 1.
5 and temporarily stored there.

On the other hand, the transfer source start address output from the SARL 8 is also sent to the increment / decrementer 13 via the switch 20, and the value is incremented or decremented. When the transfer source start address is updated by the increment / decrementer 13, the switch 22
Is turned on, sent from the incrementer / decrementer 13 to the SAR 7 and stored as a transfer source address. At that time, the switch 23 is also turned on, so that TCRL
The number of transfer bytes held in 12 is decrementer 14
When the switch 25 is turned on, the value updated by the decrementer 14 is stored in the TCR 11 as the number of remaining bytes of data to be transferred.

Next, in the write cycle, the switch 28
Is turned on, and the switch 27 is also turned on. When the switch 28 is turned on, the transfer destination start address held in the DARL 10 is output and input to the transfer destination memory 3 and the incrementer / decrementer 13. The transfer destination memory 3 is accessed using the transfer destination start address, and the data of one transfer unit temporarily held in the DMA latch 15 and transmitted via the switch 27 is written to the transfer start address. It is. On the other hand, the incrementer / decrementer 13 receiving the transfer destination start address output from the DARL 10 updates the value by incrementing or decrementing the value. Thereafter, when the switch 30 is turned on, the value updated in the incrementer / decrementer 13 is stored in the DAR 9 as a transfer destination address.

In the read cycle for transferring the second and subsequent data in one transfer unit, the switch 2
1 is turned on, and the transfer source address held in the SAR 7 is output. Using the transfer source address, the transfer source memory 2
From the transfer source address of the transfer source memory 2
Reads data in transfer units. At that time, the switch 26 is turned on, and the data read from the transfer source memory 2 is temporarily held in the DMA latch 15. Meanwhile, SA
The transfer source address held in R7 is also sent to the increment / decrementer 13 via the switch 21 and is incremented or decremented. When the transfer source address is updated by the increment / decrementer 13, the switch 22 is turned on, and the updated transfer source address is sent to the SAR 7 and stored. At this time, the switch 24 is also turned on, so that the remaining number of transfer bytes held in the TCR 11 is sent to the decrementer 14 and updated, and thereafter, when the switch 25 is turned on, the updated value is stored in the TCR 11. Is done.

Next, in the write cycle, the switch 29
Is turned on, and the switch 27 is also turned on. The transfer destination memory 3 is accessed using the transfer destination address sent from the DARL 10 via the switch 29,
The data of one transfer unit temporarily held in the A latch 15 is sent to the transfer destination memory 3 via the switch 27, and written to the transfer destination address. At that time, DARL
The transfer destination address output from 10 is also input to the incrementer / decrementer 13 via the switch 28, the value of which is incremented or decremented, and stored in the DAR 9 when the switch 30 is turned on.

Therefore, after the DMA transfer is interrupted halfway due to forced termination or the like, the DMA permission bit and the DM
When the A request flag is set, it appears that the DMA transfer parameters are once reset and the DMA transfer is restarted. FIG. 3 is an explanatory diagram showing the data reading order when the transfer parameter reset bit 31 is set to "0". As shown in the figure, when the DMA transfer is restarted, data reading from the transfer source memory 2 is started from the transfer source start address set first at the start of the DMA transfer. The operation when the transfer parameter reset bit 41 is set to “0” is as follows.
This is the same as the operation of the conventional DMA controller.

Next, the transfer parameter reset bit 41
Is set to “1”. When the transfer parameter reset bit 41 is "1", the switches 20, 23 and 28 are always off, and the switches 21, 24 and 2
9 turns on / off as needed. Therefore, the source address stored in the SAR 7 is transmitted from the source address register 4 and the DAR is transmitted from the destination address register 5.
9 is always output, and the transfer counter register 6 always outputs the remaining number of transfer bytes held in the TCR 11.

Therefore, the switch 21 is turned on also in the read cycle for transferring the data of one transfer unit at the time of resuming the interrupted DMA transfer.
Is output immediately after the DMA transfer is interrupted. The transfer source memory 2 is accessed using the transfer source address, and data of one transfer unit is read from the transfer source address of the transfer source memory 2. When the switch 26 is turned on, the read data is sent to the DMA latch 15 via the switch 26 and is temporarily held. S
The transfer source address held in the AR 7 is also sent to the incrementer / decrementer 13 via the switch 21 and its value is updated. When the switch 22 is turned on, the updated transfer source address is stored in the SAR 7. You. At this time, since the switch 24 is also turned on, the remaining number of transfer bytes held in the TCR 11 is sent to the decrementer 14 and updated. Thereafter, when the switch 25 is turned on, the remaining transfer byte number updated by the decrementer 14 is stored in the TCR 11.

In addition, when the DMA transfer which has been interrupted is resumed, the switch 29 and the switch 27 are turned on even in the write cycle for transferring the data of the first transfer unit. DAR
9, the transfer destination address immediately after the DMA transfer is interrupted is output. The transfer destination memory 3 is accessed using the transfer source address, and the data of one transfer unit received from the DMA latch 15 via the switch 27 is written to the transfer destination address. The transfer source address held in the SAR 7 is also sent to the incrementer / decrementer 13 via the switch 21 to update the value, and the switch 30
Is turned on and stored in DAR9.

When the interrupted DMA transfer is resumed, the read cycle and the write cycle for transferring the data of the second and subsequent one transfer units are also the same as those for transferring the data of the first one transfer unit. It operates similarly to the read cycle and the write cycle.

Therefore, after the DMA transfer is interrupted halfway due to forced termination or the like, the DMA permission bit and the DM
When the A request flag is set, the DMA transfer is restarted from the next interrupted transfer address without resetting the DMA transfer parameters. FIG. 4 is an explanatory diagram showing the data reading order when the transfer parameter reset bit 41 is set to "1". As shown, the DMA
When the transfer is resumed, data reading from the transfer source memory 2 is started from the transfer source address held in the SAR 7 when the DMA transfer is interrupted. Note that this DMA transfer is performed by TCR
When the number of remaining transfer bytes held in 11 becomes “0”, the process ends.

The transfer parameter reset bit 41
Is set to “1” from the beginning, the value of the transfer source start address written in the transfer source address register 4 is simultaneously written to the SAR 7 and the SARL 8 as in the conventional DMA controller. All of the DMA transfer including the transfer of the data of one transfer unit is performed in SA
The transfer source address is read only from R7.

As described above, according to the first embodiment, even after the DMA transfer is forcibly terminated, the contents of the transfer parameter reset bit 41 are manipulated to retain the data in the SARL 8 and the DARL 10 when the transfer is resumed. It is possible to switch between the use of the transfer source start address and the transfer start address, or the use of the transfer source address and the transfer destination address held in the SAR7 and the DAR9. There is an effect that it is easy to select whether to restart the DMA transfer or to restart the DMA transfer from the address immediately after the interrupted transfer.

Embodiment 2 In the first embodiment, the case where the order of exchange of address values and the like between the register unit and the latch unit such as the transfer source address register 4 and the incrementer / decrementer 13 and the like is changed is described. An address value or the like may be exchanged between a register unit such as the original address register 4 and a latch unit.

FIG. 5 shows such a second embodiment of the present invention.
FIG. 3 is an explanatory diagram showing a concept of a DMA controller according to the first embodiment.
Here, FIG. 5 mainly shows a portion related to the transfer source address register 4, and omits illustration of a portion related to the transfer destination address register 5 and the transfer counter register 6. In the figure, reference numeral 31 denotes a transfer parameter reset bit 41 according to a set value thereof.
S of the content held in SAR7 of transfer source address register 4
A switch for turning on / off the transfer to the ARL8. The other parts are the parts corresponding to those in the first embodiment shown in FIG.
The description is omitted.

Next, the operation will be described. As shown in FIG. 5, SAR7 to SAR of transfer source address register 4
A path for transmitting the transfer source address is provided in L8, and a switch 31 is arranged on the path. When the transfer parameter reset bit is "1", the transfer end processing is performed when the DMA transfer is forcibly terminated or normally terminated. The switch 31 is turned on in the cycle. On the other hand, when the transfer parameter reset bit is "0", this switch 31 remains off in the transfer end processing cycle when the DMA transfer is forcibly ended or normally ended.

As described above, when the transfer parameter reset bit 41 is set to "1", the switch 31 is turned on in the transfer end processing cycle at the time of forcibly terminating or normally terminating the DMA transfer. Immediately after the interruption, the transfer source address held in the SAR 7 is sent to the SARL 8 via this switch 31, and is held there. Therefore, the DMA permission bit and the DMA request flag are set again, and the suspended D
When the MA transfer is restarted, the switch 20 is switched in the read cycle when the data of the first transfer unit is transferred.
Is turned on, and the transfer source address transferred to the SARL 8 immediately after the DMA transfer is interrupted is output to the transfer source memory 2 and the increment / decrementer 13. Source memory 2
Is accessed by the transfer source address, and data read from the transfer source address is temporarily held in a DMA latch (not shown). The transfer source address is updated by the incrementer / decrementer 13, and when the switch 22 is turned on, the transfer source address is stored in the SAR7.

In the read cycle when transferring the second and subsequent data in one transfer unit, the switch 2
1 is turned on and the transfer source address stored in the SAR 7 is output, so that the data read from the transfer source address in the transfer memory 2 is temporarily stored in a DMA latch (not shown). At the same time, the transfer source address is updated by the incrementer / decrementer 13 and stored in the SAR 7. Therefore, if the transfer parameter reset bit 41 is set to “1”, as shown in FIG.
When the transfer is resumed, data reading from the transfer source memory 2 is started from the transfer source address held in the SAR 7 when the DMA transfer is interrupted.

When the final transfer cycle is completed,
In the transfer end processing cycle after the MA transfer ends normally, the switch 31 is turned on again, and the value of the transfer source address held in the SAR 7 is transferred to the SARL 8 and held.

On the other hand, the transfer parameter reset bit 41
Is set to “0”, this switch 31
Since it is not turned on in the transfer end processing cycle at the time of forcible termination of MA transfer or normal termination, SARL
8 holds the transfer source start address set at the start of the DMA transfer. Therefore, once again DMA
When the permission bit and the DMA request flag are set and the interrupted DMA transfer is resumed, as shown in FIG. 3, instead of the transfer source address immediately after the DMA transfer is interrupted,
As in the conventional DMA controller, the access to the transfer source memory 2 is performed from the transfer source start address set first.

The DAR of the transfer destination address register 5
9 and DARL10, and between TCR11 and TCRL12 of the transfer counter register 6, switches equivalent to the above-described switch 31 are arranged. When these switches are turned on, the contents of the register section immediately before the interruption are changed. It is sent to the latch unit and held.

As described above, according to the second embodiment, only by setting the transfer parameter reset bit 41 to "0", the transfer source address, the transfer destination address and the remaining DMA transfer parameters such as the number of transfer bytes are read out from SAR7, DAR9, and TCR11,
Even if the data is not rewritten into the RL 12, the DMA transfer can be resumed from the address immediately after the transfer has been interrupted just by setting the DMA permission bit and the DMA request flag again.

Embodiment 3 In each of the above embodiments, the transfer parameter reset bit 41 is provided, and depending on the content, the DMA transfer is reset from the beginning when the DMA transfer is restarted.
Although a description has been given of a case where the transfer is restarted or a restart is performed from the next address, the DMA transfer may be restarted from the continued address where the DMA transfer is interrupted only in a specific mode of the DMA transfer. Next, such a DMA controller according to Embodiment 3 of the present invention will be described with reference to FIG.

Normally, the DMA transfer mode includes a single transfer mode in which, when a DMA request is received, one transfer of data of one block of the memory is completed once, and a repetitive transfer mode in which data of one block of the memory is repeatedly transferred. is there. In the case of the single transfer mode, when the DMA transfer is resumed by setting the DMA permission bit and the DMA request flag again after normal termination or forced termination, the switch 20 shown in FIG.
Is turned on. Thereby, the DM
At the start of the A transfer, the DMA transfer based on the transfer source start address written in the transfer source address register 4 and the transfer destination start address written in the transfer destination address register 5 is restarted.

On the other hand, in the case of the repetitive transfer mode, the switch 21 of FIG. 1 is turned on at the time of restart after forced termination (only when repeated transfer is terminated by forced termination). This makes it possible to restart the DMA transfer from the address immediately after the forced termination. Note that, in this case, the DMA address starts from the address written in the transfer source address register 4 and the transfer destination address register 5 first.
When the transfer is to be performed again, the transfer source start address, the transfer destination start address, and the number of transfer bytes written first are written to the transfer source address register 4, the transfer destination address register 5, and the transfer counter register 6 again.

Also, in the repetitive transfer mode, when restarting after forced termination, the switch 20 of FIG. 1 is turned on, and the DMA is started from the address written in the transfer source address register 4 or the transfer destination address register 5 first. "Repeated transfer 0 mode" for restarting transfer, and switch 2 in FIG.
1 turns on and DMA starts from the address immediately after forced termination.
The transfer may be divided into the “repeated transfer 1 mode” in which the transfer is restarted.

Incidentally, these transfer modes are usually specified by bits of a DMA mode register.

As described above, according to the third embodiment, when resuming the interrupted DMA transfer, whether to restart from the transfer source start address and the transfer destination start address which were set first at the start of the DMA transfer. Whether to restart from the transfer source address and the transfer destination address immediately after the DMA transfer is interrupted,
There is an effect that it is possible to specify and use each transfer mode.

[0055]

As described above, according to the present invention, the DM
When restarting the DMA transfer after forcibly terminating the A transfer, and wishing to restart the DMA transfer from the address immediately after the interruption,
A The DMA transfer is restarted using the first DMA transfer parameter set at the start of the A transfer, or the DM
The selection as to whether to restart the DMA transfer using the A transfer parameter can be switched according to the setting of the transfer parameter reset bit, and the DMA transfer parameter is read once from SAR, DAR, TCR, etc. , DARL, TCRL, etc., there is no need to rewrite data, so that there is an effect that a trouble in program creation can be saved and a program can be created more easily.

Further, according to the present invention, when resuming the DMA transfer, it is determined whether to restart the DMA transfer from the first address set at the start of the DMA transfer or to restart the DMA transfer from the continued address. In addition, there is an effect that it is possible to specify and use each transfer mode.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a concept of a DMA controller according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a DMA control register in which transfer parameter reset bits are arranged according to the first embodiment;

FIG. 3 is an explanatory diagram showing data reading from a transfer source memory when the content of a transfer parameter reset bit is “0” in the first embodiment;

FIG. 4 is an explanatory diagram showing data reading from a transfer source memory when the content of a transfer parameter reset bit is “1” in the first embodiment;

FIG. 5 is an explanatory diagram showing a concept of a DMA controller according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a basic operation in a first transfer cycle of a conventional DMA controller.

FIG. 7 is an explanatory diagram showing a basic operation in a second and subsequent transfer cycles of a conventional DMA controller.

[Explanation of symbols]

1 DMA controller, 4 source address register, 5 destination address register, 6 transfer counter register, 7 SAR (register unit), 8 SARL (latch unit), 9 DAR (register unit), 10 DARL
(Latch), 11 TCR (register), 12 T
CRL (latch unit), 40 DMA control register, 41
Transfer parameter reset bit.

Claims (5)

[Claims] 1. A transfer source address register including a register unit for storing a transfer source address of data to be transferred by direct memory access, and a latch unit for holding a value first written in the register unit; A transfer destination address register including a register unit for storing a transfer destination address of data to be transferred by memory access, and a latch unit for holding a value initially written to the register unit; Register section for counting the number of remaining transfer bytes of data to be transferred,
And a transfer counter register comprising a latch unit for holding a value initially written to the register unit, wherein the direct memory access transfer that has been interrupted is resumed by the direct memory access controller. The transfer is performed using the values of the source start address, the transfer destination start address and the number of transfer bytes set at the start of the memory access transfer, or the transfer source address, the transfer destination address and the transfer address immediately after the direct memory access transfer is interrupted. A direct memory access controller characterized in that the selection as to whether to use the remaining number of transfer bytes is switched according to the setting of a transfer parameter reset bit. 2. A direct memory access control, wherein a transfer parameter reset bit is arranged in an empty bit of a direct memory access control register provided in the direct memory access controller. The direct memory access controller according to claim 1. 3. When resuming a suspended direct memory access transfer, a transfer source address, a transfer destination, or a transfer source address register, a transfer destination address register, and a transfer counter register are read from any of the register units or the latch units. 3. The direct memory access controller according to claim 1, wherein selection of whether to output a value of the address and the number of bytes to be transferred is switched according to the setting of a transfer parameter reset bit. 4. A transfer source address register, at the end processing cycle of direct memory access transfer,
The transfer source address register, the transfer destination address register, and the transfer counter register determine whether or not to transfer the values held in the respective register units of the transfer destination address register and the transfer counter register to the respective latch units of the transfer counter register. 3. The direct memory access controller according to claim 1, wherein the switching is performed according to a setting content of a parameter reset bit. 5. A transfer source address register comprising a register unit for storing a transfer source address of data to be transferred by direct memory access, and a latch unit for holding a value initially written in the register unit; A transfer destination address register including a register unit for storing a transfer destination address of data to be transferred by memory access, and a latch unit for holding a value initially written to the register unit; Register section for counting the number of remaining transfer bytes of data to be transferred,
And a transfer counter register comprising a latch unit for holding a value first written in the register unit, wherein in a predetermined transfer mode, the transfer source address register, the transfer destination Held in each register section of the address register and the transfer counter register, respectively.
A direct memory access controller for outputting values of a transfer source address, a transfer destination address, and a remaining transfer byte count.