JPH1185569A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To specify an abnormal cause and to decide a fault that causes an operation failure as abnormal especially just after the power of a CPU is turned on and just after resetting by supervising whether a supervisory object item is processed within a set supervisory time by a supervisory object device. SOLUTION: A controlling part 105 of an SCF(system supervisory mechanism) 104 performs a supervisory operation by a tamer mechanism of a compact OS2 stored in ROM 106. An interface area 119 can be made direct read and write accesses from both a CPU 100 and the SCF 104 and consists of a flag 1, i.e., an area 110 which writes phases of the CPU 100, a flag 2, i.e., an area 111 which writes the supervisory time of each phase of initialization and an initial diagnosis and a command parameter area 112 that transfers a parameter when the CPU 100 and the SCF 104 perform mutual supervision. It sets a supervisory object item and its supervisory time and supervises whether the supervisory item is processed within the set supervisory time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing apparatus having a system monitoring mechanism.

[0002]

2. Description of the Related Art In recent years, information processing apparatuses such as servers and workstations are required to have higher reliability than before. When an information processing device fails, there is a strong demand for reducing the system down time by grasping the failure location in detail and automatically restarting immediately after the failure location is detected.

[0003] Therefore, in a computer system, a main processor (hereinafter referred to as "Central Processing Uni-
t: a memory that can be shared and accessed by a CPU, a system monitoring mechanism having a mechanism capable of controlling the power supply of the computer system and a mechanism capable of notifying the CPU of an interrupt (hereinafter referred to as a System Control Facility: SC).
F), the CPU inside the processor
2. Description of the Related Art System monitoring of a computer system using a general-purpose processor having no monitoring mechanism as a CPU is performed.

At this time, the CPU software needs a monitoring program that polls the SCF for system monitoring. An SCF that can flexibly respond to the monitoring program according to the system configuration is required.

[0005]

However, in the conventional system monitoring, since the watchdog timer is monitored by hardware, dynamic change of the monitoring period, control of the start and end of the monitoring, and monitoring with the increase in the number of CPUs are performed. Correspondence of the number of targets, event notification to the cluster system, etc. could not be performed.

Therefore, according to the present invention, the CPU monitoring can be started and stopped by a flexible non-monitoring program, and when a CPU monitoring error occurs, the cause of the error is identified by hardware / firmware and which part of the hardware identifies the error. In particular, it is an object of the present invention to provide a processing device that can cause an operation failure immediately after turning on the power or immediately after reset among CPU failures.

It is another object of the present invention to provide a processing apparatus capable of obtaining error log information from which detailed information of an error content can be determined at the time of a CPU monitoring error and automatically recovering after an error is detected, thereby reducing system down time. .

[0008]

According to a first aspect of the present invention, there is provided means for setting a monitoring target item of a monitoring target device,
Means for setting a monitoring time of the monitoring target item, and means for monitoring whether the monitoring target device processes the monitoring target item within the monitoring time for the set monitoring target item. It is.

According to the first aspect of the invention, the time to be monitored differs depending on the item to be monitored of the device to be monitored. Therefore, the monitoring time can be dynamically set so that an abnormality can be detected according to the system configuration. . Further, in the second invention according to the present invention, in addition to the first invention, when the monitored item is not processed within the monitoring time, a means for instructing the monitored device to perform a failure process; Means for instructing the monitored device to perform a reset process if the processing is not performed within the monitoring time.

According to the second aspect of the present invention, the failure processing is notified to the user of the failure processing of the device to be monitored so that the occurrence of the failure can be easily understood, and the failure that cannot be recovered by the notification of the failure processing has occurred. In such a case, the automatic recovery can be performed early by instructing the reset processing. According to a third aspect of the present invention, in addition to the first aspect, there is provided means for retaining the set monitoring target item until monitoring of the monitoring target item is completed.

According to the third aspect, even when a plurality of items to be monitored exist simultaneously in the device to be monitored, the contents can be held for each item to be monitored, and
Monitoring can be performed in parallel, and when an error occurs, error log information can be obtained from the held target item.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an information processing apparatus according to an embodiment of the present invention. In FIG. 1, a CPU 1
The CPU 115 and the information processing apparatus including the SCF 116, which have the same configuration as the information processing apparatus including the SCF 00 and the SCF 104, are connected via a remote cabinet interface (RCI) 117 for exchanging information of each apparatus to form a cluster configuration.

The CPU 100 includes a control unit 101 and a ROM 1
The control unit 101 activates a control program stored in the ROM 102 to perform various processes. The interrupt register 103 has the SCF
Is a register that can generate an asynchronous interrupt to the CPU by writing the data.

The SCF 104 includes a control unit 105, a ROM 1
06, a RAM 107, a command register 108, an interface area 109, a power control register 113, and an interface unit 114. Control unit 105
Starts a control program stored in the ROM 106 to perform various processes, and also executes a general-purpose real-time OS COS2 (Compac
The monitoring operation is performed by the timer mechanism of the tOperating System 2).

The RAM 107 has a memory area for storing a monitoring cycle and a monitoring component. The command register 108 causes an interruption to the SCF when the CPU performs writing, and details thereof will be described later. The interface area 109 includes a CPU and an S
A flag 1 for writing a phase of the CPU, a flag 2 for writing a monitoring time for each phase of initial setting / initial diagnosis, a flag area for a command, and an area for a command. And SCF
Is comprised of a command parameter area 112 for passing parameters during mutual monitoring.

The power supply control register 113 is a power supply control register for performing power-on / power-off / reset operations. The interface unit 114 is connected to the RCI and exchanges information on system operations between the SCFs. The means for setting the monitoring target item according to claim 1 of the present invention corresponds to the flag 1 and the command parameter area 112 in FIG. 1, and the means for setting the monitoring time corresponds to the flag 2 and the command parameter area 112 in FIG. The means for monitoring whether the monitoring target item is processed within the monitoring time corresponds to the control unit 105 in FIG.

The means for instructing the failure processing and the means for instructing the reset processing according to claim 2 of the present invention correspond to the control unit 105 in FIG. The means for holding the items to be monitored until the end of the monitoring according to claim 3 of the present invention corresponds to the RAM 107 in FIG. Next, the configuration of the command register 108 will be described.

FIG. 2 is a diagram showing a configuration of a command register according to an embodiment of the present invention. Command register (hereinafter referred to as SCF Command / Status Register: SCST
R) is a 4-byte register, which is a CPU and SC
Both F and F can be accessed for reading and writing, and the upper one byte is read-only for the CPU only. 31-bit “BUSY” indicates that a command is issued to the SCF
Indicates that interrupt processing is in progress.
ON when writing to lower 3 bytes of this register
The state is set to "1", and when "0", the SCF is not busy and the command can be issued, and when "1", the SCF is busy and the command cannot be issued.

The 29-bit "DBSY" indicates that the SCF has accepted the command and is processing the command, and the SCF has finished the interrupt processing, the BUSY bit is turned off, and the DBSY bit is turned on at the same time. In the case of "0", the SCF is not busy and the command can be issued, and in the case of "1", the SCF is busy and the command cannot be issued.

The "STS" of 27 to 24 bits is an SCF
Is an area in which the processing result of the command is written, and when "0", indicates that the command has been completed normally in the SCF.
If the value is other than "0", it indicates that the command has abnormally ended in the SCF. 23 to 16-bit "COM" is an area for writing a command code defined by the CPU and the SCF. For example, a command for CPU monitoring is defined as "0x31".

"SUBCOM" of 15 to 8 bits is C
This is an area for writing a subcommand code of a command specified by the PU and the SCF. For example, the start command of CPU monitoring is “0x12”, and the end command is “0x12”.
10 ". "COUNT" of 7-0 bits is
This is an area in which the number of bytes of the effective parameter in the parameter area 112 is written.

The "rsv" of 30 and 28 bits is
It is a reserved bit and an empty bit. CPU is S
When writing to the lower 3 bytes of the CSTR, the BUSY bit turns ON (1), an interrupt occurs in the SCF, and the SC
F recognizes that a command has been issued from the CPU and writing has been performed due to the occurrence of the interrupt.

FIG. 10 is a diagram showing a configuration example of a monitoring command code and parameter values according to the embodiment of the present invention.
When a CPU monitoring command (monitoring start / monitoring end) is issued, the values written by the CPU in the SCSTR and the parameter area 112 and the return value from the SCF in the case of normal termination are shown.

Note that "TT" indicates a monitoring time,
“XX” indicates monitoring data (monitored component). The operation of the information processing apparatus of the present embodiment configured as described above will be described below with reference to a flowchart and a monitoring sequence. FIG. 3 is a first flowchart illustrating an operation of the SCF according to the embodiment of the present invention.
FIG. 4 is a first flowchart illustrating the operation of the CPU according to the embodiment of the present invention, and FIG. 11 is a first diagram illustrating a monitoring sequence according to the embodiment of the present invention.

In the monitoring sequence shown in FIG. 11, when the hardware is in an unstable state immediately after the power is turned on or reset and a failure or abnormality is likely to occur, a software hang-up or the like that cannot be detected by the hardware by the firmware can be performed. CPU abnormality is detected. After the breaker is turned on (S300 in FIG. 3), the SCF 104 sets the flag 1 (1
10), the initial value “0x00” of the phase code is set (S301 in FIG. 3), and the power of the CPU 100 is turned on using the power control register 113 (S302 in FIG. 3).

The SCF 104 turns on the power of the CPU 100 and sets an initial value of the monitoring time “10 seconds” to the timer 1.
Is set (S303 in FIG. 3), and the timer 1 is started (S304 in FIG. 3). The CPU 100 is powered on by the SCF 104 (S40 in FIG. 4), and starts the operation of a hardware diagnostic program (hereinafter referred to as “Power On Self Test: POST”) (S41 in FIG. 4).
The monitoring time "a (second)" in the next phase is written in 11) (S42 in FIG. 4), and the initial value "0" is written in the flag 1 (110).
The next phase code "0x01" other than "x00" is written (S43 in FIG. 4).

Thereafter, each time the phase of the diagnosis changes (S44 in FIG. 4), the CPU 100 determines whether the diagnosis has been completed (S45 in FIG. 4).
0) is written in the diagnostic end code “0x80” (FIG. 4S
46), terminate the process. On the other hand, if the diagnosis is not completed, the process returns to S42, where the next phase code “0x02” and the monitoring time “b (second)” in that phase are written in the flag 1 (110) and the flag 2 (111), respectively, and the diagnosis is performed. The processing from S42 to S45 is repeated until the processing is completed.

The SCF 104 is in the monitoring time (S30 in FIG. 3).
5) Whether the next phase code is written in flag 1
(110) is referenced every second (FIG. 3, S306).
If it changes from the initial value “0x00” within seconds, it is determined that POST is operating and the timer 1 is stopped (S30 in FIG. 3).
8) If it does not change, it is considered that the CPU has hung up and abnormal processing is performed (S307 in FIG. 3), and the processing ends.

The SCF 104 stops the timer 1 and determines whether the newly written phase code is a diagnosis end code (S309 in FIG. 3). If the phase end code is a diagnosis end code, the SCF 104 terminates the monitoring process. If “0x01”, the flag 2 (11
The monitoring time “a (second)” of the phase code “0x01” written in 1) is newly set in the timer 2 (FIG. 3).
(S310), and return to S304.

The SCF 104 returns to S304,
Is started, and a phase code “0x02” different from the current one is rewritten within the monitoring time “a (second)”.
0) is referenced every second and the phase code “0x01”
Is monitored, and the processing from S304 to S308 is repeated. Regarding the phase code “0x02”, the monitoring time “b (second)” of that phase is newly set in the timer 3, it is monitored whether or not the phase code is rewritten to the next phase code within the monitoring time, and the processing from S304 to S308 is repeated. .

As described above, after the POST starts to operate, the information of the initialization / initialization of the initial diagnosis / initial diagnosis / diagnosis phase is registered in the SCF, and the SCF checks whether each phase is completed within a specified time. I do. The SCF can detect that an abnormality has occurred because there is no registration of a new phase even after a lapse of a prescribed time, and can detect a detailed abnormality location using the phase code.

Further, since the time required for the initial setting and initial diagnosis differs depending on the system configuration and each phase, the prescribed time for ending each phase can be dynamically set on the POST side for each phase of the initial setting and initial diagnosis. The monitoring phase updating process of the POST process can be flexibly performed, and the abnormality can be detected more quickly and accurately.

Next, for each component of the CPU, the SCF
Will be described. FIG. 5 is a second flowchart illustrating the operation of the CPU according to the embodiment of the present invention, and FIGS. 6 to 9 are second to fifth flowcharts illustrating the operation of the SCF according to the embodiment of the present invention. FIG. 12 is a diagram illustrating a monitoring sequence according to an embodiment of the present invention.
FIG. 13 is a third diagram illustrating a monitoring sequence according to the embodiment of the present invention.

In the monitoring sequence of FIG. 12, since the time that the SCF wants to monitor differs depending on the component of the CPU, the monitoring time is dynamically set so that the abnormality of the CPU can be detected more quickly and accurately. Is notified to the user by panic, and if an abnormality that cannot be recovered by panic occurs, the SCF reb
To do so.

The monitoring sequence shown in FIG. 13 performs monitoring independently for each component of the CPU. When starting the component operation, the CPU 100 reads “BUSY” and “DBSY” of the SCSTR 108 and determines whether both are “0” (S500 in FIG. 5). If both are “0”, the parameter value is stored in the command parameter area 112. The monitoring data “A” indicating the type of the monitored component and the monitoring cycle “a (second)” are written (S501 in FIG. 5).

Next, the CPU 100 stores C in the SCSTR 108.
The PU monitoring start command issuance value “00311202” is written (S502 in FIG. 5), and the “BU” of the SCSTR 108 is written.
SY ”to“ 1 ”(SCSTR 108 value is“ 80 ”
311202 "), thereby causing the SCF 104 to generate an interrupt (S503 in FIG. 5). CPU is SCF104
Causes an SCF in SCSTR 108
Since polling is performed until a command reception response is written from 108, the polling timeout time “X
Milliseconds ”is set in the timer 1 (S504 in FIG. 5), and the timer 1 is started (S505 in FIG. 5).

At this time, the polling timeout period is set to be much shorter than the designated monitoring period. For example, if the monitoring period is set to 1 s, the timeout period is 1 unit.
The unit is ms. Within the polling monitoring time (S506 in FIG. 5), the CPU 100 checks every second whether “BUSY” and “DBSY” of the SCSTR 108 are “0” (S508 in FIG. 5), and within “X milliseconds,” “BUSY” and “DBSY”. Are changed to “0”, the command is received and the timer 1 is stopped (S509 in FIG. 5).
If it does not change, it is considered that the SCF 104 has hung up, and the SCF 104 is reset (S50 in FIG. 5).
7), end the process.

After stopping the timer 1, the CPU 100 sets S
It is determined whether or not “STS” of CSTR 108 is “0” (S510 in FIG. 5). If “0”, the command is SCF1.
If the command ends normally in 04, the process is terminated. If not “0”, the command is regarded as abnormally terminated in the SCF 104, and abnormal processing is performed (S511 in FIG. 5), and the process is terminated. C
The PU 100 transmits the next monitoring start command or transmits a monitoring end command to the SCF during a period shorter than the monitoring cycle specified by the monitoring start command, and repeats the processing from S500 to S510 for each command.

The SCF 104 sends the SCST
It is determined whether there is a write in R108 and an interrupt has occurred (S60 in FIG. 6).
108 (S61 in FIG. 6), the command receiving process is performed, and “BUSY” of the SCSTR 108 is changed to “0”.
“DBSY” is set to “1”, and the value of the SCSTR 108 is set to “20311202” (S62 in FIG. 6).

When the SCF 104 receives the CPU monitoring start command, the SCF 104 stores it in the RAM 107 together with the monitoring period and the monitoring data, which are the parameter values written in the command parameter area 112 (S63 in FIG. 6). SCF10
4 starts the command processing of the received CPU monitoring start command (S64 in FIG. 6), and sets the return value “00311200” of the CPU monitoring start command in the SCSTR 108.
Is written (S65 in FIG. 6).

The SCF 104 prepares a table for distinguishing the monitored component in the RAM 107. If there is no monitored component being monitored, enter "0" in the table. Data other than the unique “0” indicating the monitored component is entered. SCF104 is CP
CP received as command processing of U monitoring start command
The monitoring data of the U monitoring start command is confirmed and the table is referred to (S70 in FIG. 7). It is determined whether the monitored component is already in the table and the monitoring timer is operating (S71 in FIG. 7). Is stopped (S72 in FIG. 7).

The SCF 104 writes the monitoring data "A" of the received CPU monitoring start command in the table (FIG. 7).
S73), the monitoring cycle “a” of the monitoring data “A” is set in the timer 2 (S74 in FIG. 7), and the timer 2 is started (S75 in FIG. 7). When the SCF 104 receives the CPU monitoring start command of the monitoring data “A” during a time shorter than the monitoring cycle “a”, the SCF 104 repeats the processing from S70 to S75 as the command processing of the received CPU monitoring start command. The monitoring data of the executed CPU monitoring start command is confirmed, and the table is referred to. Since the monitored component is already in the table and the monitoring timer is operating, the timer 2 is stopped.

The SCF 104 writes the monitoring data "A" of the received CPU monitoring start command in the table, sets the monitoring cycle "b" of the monitoring data "A" in the timer 4, and starts the timer 4 (S75 in FIG. 7). The SCF 104 monitors the monitoring data “A” during a time shorter than the monitoring cycle “a”.
Of monitoring data "B" which is a different component from C
When the PU monitoring start command is received, the command processing of the received CPU monitoring start command is executed as a command process from S70 to S75.
The monitoring process is repeated to check the received monitoring data of the CPU monitoring start command, refer to the table, determine whether the monitored component is already in the table, and whether the monitoring timer is operating. Stop the timer.

The SCF 104 writes the monitoring data “B” of the received CPU monitoring start command in the table, sets the monitoring cycle “b” of the monitoring data “B” in the timer 2 and activates the timer 2. When the SCF 104 receives the CPU monitoring end command of the monitoring data “A” during a period shorter than the monitoring period “a”, the SCF 104 checks the monitoring data of the CPU monitoring end command received as the command processing of the CPU monitoring end command. Referring to the table (S80 in FIG. 8),
It is determined whether the monitored component is already in the table and the monitoring timer is operating (S81 in FIG. 8), and if not, the process is terminated as it is.

If the monitoring timer is operating, the SCF 104 stops the monitoring timer (S82 in FIG. 8), deletes the monitoring data “A” of the monitored component from the table (S83 in FIG. 8), and ends the processing. The SCF 104 sets the same monitoring data C
When a timeout occurs without receiving a PU monitoring start command or an end command, a bit is set in the interrupt register 103 to notify a timeout (S91 in FIG. 9), and the CPU
The system is panicked by giving an interrupt to 100 (S92 in FIG. 9).

The SCF 104 starts the timer 4 again (S93 in FIG. 9), and sets C in the monitoring cycle “b” (S94 in FIG. 9).
The CPU 100 waits for the writing of a CPU monitoring start command or an end command of the same monitoring data from the PU 100, and if there is a writing within the monitoring period “b”, stops the timer 4 (S97 in FIG. 9), and there is no writing and the timeout continues. If it occurs twice, it is determined that the CPU 100 has hung up and a reset is issued to the CPU 100 (S9 in FIG. 9).
5) Reboot the system and end the process.

As described above, during the operation of the apparatus, the operation phase of the system and the component to be monitored are registered in the SCF, and it is checked whether or not the CPU notifies the SCF within a certain time. The location and the system operation phase can be determined. Also,
A request is issued to instruct the system to panic in the first monitoring abnormality, and in an abnormal state in which the panic instruction is not accepted, a two-step abnormality process of restarting the system is performed to determine an abnormality level and perform appropriate abnormality processing. be able to.

Further, by monitoring the response from the SCF to the periodic instruction to start and continue monitoring from the CPU, the SCF to be monitored is also monitored from the CPU, thereby increasing the reliability of the entire system. It becomes possible.

[0049]

As described above, according to the present invention, C
Since the time that the SCF wants the SCF to monitor differs depending on the PU component, the monitoring time is set dynamically and monitoring is performed independently for each component. There is an effect that can be monitored.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a command register according to the embodiment of the present invention.

FIG. 3 is a first flowchart showing an operation of the SCF according to the embodiment of the present invention.

FIG. 4 is a first flowchart showing the operation of the CPU according to the embodiment of the present invention.

FIG. 5 is a second flowchart illustrating the operation of the CPU according to the embodiment of the present invention.

FIG. 6 is a second flowchart showing the operation of the SCF in the embodiment of the present invention.

FIG. 7 is a third flowchart illustrating the operation of the SCF in the embodiment of the present invention.

FIG. 8 is a fourth flowchart illustrating the operation of the SCF in the embodiment of the present invention.

FIG. 9 is a fifth flowchart illustrating the operation of the SCF in the embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration example of a monitoring command code and a parameter value in the embodiment of the present invention.

FIG. 11 is a first diagram illustrating a monitoring sequence in the embodiment of the present invention.

FIG. 12 is a second diagram illustrating a monitoring sequence in the embodiment of the present invention.

FIG. 13 is a third diagram illustrating a monitoring sequence in the embodiment of the present invention.

[Explanation of symbols]

 100, 115 ... CPU 104, 116 ... SCF 101, 105 ... control unit 102, 106 ... ROM 103 ... interrupt register 107 ... RAM 108 ... command register 109 ... Interface area 110: Flag 1 111: Flag 2 112: Command parameter area 113: Power control register 114: Interface unit 117: RCI

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeo Tata 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kazuhiro Yuki 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 1-1 Fujitsu Limited (72) Inventor Naoki Izumida 4-1-1 Kamikodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (3)

[Claims] 1. A means for setting a monitored item of a monitored device, a means for setting a monitoring time of the monitored item, and for the set monitored item, the monitored item is determined by the monitored device. Means for monitoring whether processing is performed within the monitoring time. Means for instructing the monitored device to execute a failure process if the monitored item is not processed within the monitoring time; and providing means for instructing the monitored device if the fault processing is not processed within the monitored time. The processing apparatus according to claim 1, further comprising: means for instructing a reset process. 3. The processing apparatus according to claim 1, further comprising means for holding the set monitoring target item until monitoring of the monitoring target item is completed.