JPH1185308A - Internal clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a skew occurred in a clock buffer system to the minimum without correcting it by a PLL circuit and a DLL circuit. SOLUTION: Unsaturated logic circuits 1-3, which do not have saturation characteristic for stopping the output level at a prescribed value with respect to the fluctuation of an input level and a logic threshold deciding operation point constitute an internal clock generation circuit. A triangular wave having a waveform whose edge curve is dull compared to a rectangular wave and whose period is slower than the operation speed of a logic circuit is inputted. Thus, an inconvenience that the circuit does not substantially operate until a value reaches the logic threshold is prevented and the delay of an internal clock with respect to the input clock is reduced. Thus, the skew of the clock buffer system can be suppressed to be less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal clock generation circuit, and more particularly to a clock generation circuit for generating a clock used in a high-speed small-amplitude interface circuit, for example, a clock for determining an integration period in an integration type input circuit. It is suitable.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit (LSI) such as a microprocessor or a semiconductor memory has been required to operate at a high frequency in order to increase processing speed. Accordingly, synchronization between each LSI chip or each LSI
The frequency of a clock for synchronizing circuits in a chip has been increasing. Further, as the clock frequency increases, the amplitude of data transmitted and received in synchronization with the clock decreases.

For example, when making a circuit that takes in data in synchronization with such a clock, each circuit is usually configured to operate in accordance with one system of clocks. It is necessary to distribute to. Therefore, some kind of buffering means must be provided to amplify the clock power and send it to each circuit.

FIG. 4 shows a configuration of a conventional internal clock generation circuit. As shown in FIG. 4, a clock generated by an oscillation circuit (not shown) or externally supplied is supplied to a buffer circuit 42 via an input circuit 41, amplified, and output to each internal circuit (not shown). Here, a circuit operating at a high frequency, for example, a very high-speed DR
In the case of AM, as an input clock, a rectangular wave with a sharp rising curve and as clean as possible is usually used as shown in FIG.

[0005]

The input circuit 41 described above
Has a predetermined logical threshold, and starts operating when the level of the rectangular wave clock exceeds the threshold. The buffer circuit 42 is configured by connecting, for example, two CMOS inverters. This CMOS inverter also has a predetermined logical threshold value, and the logical value of the clock is inverted at the threshold value. Therefore, apparently, the circuit does not operate until the threshold is reached.

Further, even if the input rectangular wave clock is high-speed, it operates at a lower speed in the circuit, so that the rising / falling of the obtained internal clock is as shown in FIG. Become slow. Therefore, it takes time to reach the logical threshold value that determines the operating point of the buffer circuit 42. As a result, the obtained internal clock is
As shown in FIG. 5B, there is a phase difference (skew) delayed by a certain time with respect to the input clock.

When the skew is large, if the internal clock is used as it is, synchronization between the devices cannot be achieved properly, which may cause a malfunction or the like. Therefore, conventionally, PLL (Phase Locked Loop) circuit and DLL
(Delay Locked Loop) circuit was corrected to reduce skew. However, such a method requires complicated processing to adjust the lock-in time,
There were problems such as increased power consumption.

The present invention has been made in order to solve such a problem, and it is possible to minimize skew generated in a clock buffer system without performing correction by a PLL circuit or a DLL circuit. The purpose is to:

[0009]

An internal clock generating circuit according to the present invention is an internal clock generating circuit for processing an input clock to generate an internal clock, has a dynamic range sufficiently larger than the amplitude of the input clock, and The internal clock generating circuit is constituted by a logic circuit having a sufficiently large bandwidth for a Fourier component (harmonic component) constituting the input clock, and the input clock to the internal clock generating circuit is compared with a rectangular wave. A clock having a slow rising / falling waveform is input.

Here, the logic circuit may be an unsaturated logic circuit having no logic threshold value for determining an operating point. Further, the input clock may be a clock having a triangular wave or sine wave waveform with a period slower than the operation speed of the logic circuit. Further, the logic circuit includes an unsaturated input circuit to which a clock is input,
An unsaturated buffer circuit for amplifying the output of the unsaturated input circuit may be used. Further, the logic circuit has an unsaturated input circuit to which a clock is input, an unsaturated buffer circuit that amplifies an output of the unsaturated input circuit, and a degree of unsaturation as compared with the unsaturated buffer circuit. It may be constituted by a quasi-unsaturated buffer circuit having low characteristics and amplifying the output of the unsaturated buffer circuit.

Another feature of the present invention is that in an internal clock generating circuit for generating an internal clock for determining an integration period in an integration type input circuit, the rise / fall is slower than that of a rectangular wave. A circuit to which a clock having a waveform whose cycle is slower than the operation speed of the circuit is inputted, which has a dynamic range sufficiently larger than the amplitude of the input clock, and has a Fourier component (harmonic component) constituting the input clock. An input circuit having a sufficiently large bandwidth, and an unsaturated buffer circuit that generates an internal clock by amplifying the output of the unsaturated input circuit are provided.

According to the present invention configured as described above, a logic circuit that generates an internal clock from an input clock has neither a logical threshold value for determining its operating point nor a saturation characteristic. The inconvenience of not operating properly can be prevented. In addition, the operation speed of the unsaturated circuit is higher than that of the saturated circuit, and the clock input to the unsaturated circuit has a slower rise / fall time than that of the rectangular wave. Since the waveform has a cycle lower than the speed, the input clock is amplified and output from the logic circuit with almost no delay. Therefore, the delay of the internal clock with respect to the input clock is small, and the skew, which is the phase difference of the internal clock with respect to the input clock, can be reduced.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing one embodiment of an internal clock generation circuit according to the present invention, and FIG.
FIG. 5 is a diagram for explaining the operation of the internal clock generation circuit according to the present embodiment shown in FIG. Hereinafter, FIGS. 1 and 2
The internal clock generation circuit of the present embodiment will be described with reference to FIG.

In FIG. 1, reference numeral 1 denotes an unsaturated input circuit to which a clock generated by an oscillation circuit (not shown) or externally supplied is input. Here, the unsaturated type refers to having a dynamic range sufficiently larger than the amplitude of the input clock and having a sufficiently large bandwidth for a Fourier component (harmonic component) constituting the input clock. This means that there is no region where the signal level of the output clock is constant even if the signal level fluctuates.

In terms of the circuit, M which constitutes the circuit
This means that an OS transistor or the like does not have an operation region in which the drain current is constant regardless of the drain voltage, or a bipolar transistor does not have an operation region in which the collector current is constant regardless of the collector voltage. The unsaturated input circuit 1 is constituted by, for example, a current mirror type differential amplifier circuit. The unsaturated input circuit 1 including the current mirror type differential amplifier circuit does not have a logical threshold for determining an operating point.

Reference numeral 2 denotes an unsaturated buffer, for example, a current mirror type CMOS differential amplifier.
The unsaturated type here also means that there is no region where the signal level of the output clock is constant even if the signal level of the input clock fluctuates. Therefore, the unsaturated buffer 2 also has no logical threshold. Reference numeral 3 denotes a quasi-unsaturated buffer, which is constituted by, for example, a differential amplifier with an AGC (Auto Gain Control). Here, the term “quasi-unsaturated” means that the degree of unsaturation is lower than that of the unsaturated buffer 2, that is, the buffer has a slightly saturated characteristic. The unsaturated buffer 2 and the quasi-unsaturated buffer 3 form a buffer circuit.

The clock input to the internal clock generation circuit of the present embodiment configured as described above is, for example, as shown in FIG.
This is a triangular wave as shown in FIG. The triangular wave is a waveform that has a slower rising / falling time than a rectangular wave and has a period that is slower than the operation speed of the differential logic of the buffer circuit. When a clock having such a waveform is input, each of the circuits 1 to 3 does not have a logical threshold value for determining an operating point, and the clock is almost delayed because the operation speed of each of the circuits 1 to 3 is faster than the clock cycle. Each circuit 1-3 without
Output from

Further, in the unsaturated input circuit 1 and the unsaturated buffer 2, the signal level of the clock output relative to the input clock does not saturate. Therefore, the clock output from the unsaturated buffer 2 is
As shown in FIG. 2B, the delay with respect to the input clock is small, and the waveform is still a triangular wave. Thereafter, the internal clock processed and output by the quasi-unsaturated buffer 3 is clipped by a certain value at the vertex of the triangular wave, and thus has a trapezoidal waveform as shown in FIG.

However, the quasi-unsaturated buffer 3 also has some saturation characteristics, but does not have a logical threshold value for determining an operating point. Therefore, it is possible to prevent a disadvantage that the circuit does not substantially operate until the logical threshold value is reached, and Since a higher operation speed can be secured as compared with a pure saturation type buffer circuit, a delay with respect to an input clock is small. As a result, the skew, which is the phase difference of the internal clock with respect to the triangular wave input clock, as a whole, is significantly reduced as compared with the related art.

As described above, in the present embodiment, the internal clock generating circuit is constituted by an unsaturated type logic circuit having no saturation characteristics and no logical threshold value, and a cycle slower than the operation speed of the circuit is used as the input clock. Since a triangular wave having the skew is used, the skew generated in the clock buffer system can be minimized, and the skew correction by the PLL circuit or the DLL circuit is not required. The power consumption is slightly higher in unsaturated logic, but when using a very fast clock, the through current is large even in saturated logic.
This is much better than using a PLL circuit or a DLL circuit.

In the above embodiment, a triangular wave clock is used as an input clock. However, a waveform such as a sine wave may be used as long as the waveform has a transient time slower than the operation speed of the circuit.

Although the buffer circuit is constructed by cascading the unsaturated buffer 2 and the quasi-unsaturated buffer 3, the buffer circuit does not necessarily have to be multistage as described above. It may be constituted by a buffer. The reason why the quasi-unsaturated buffer 3 is provided in the last stage in the above-described embodiment is that the waveform of the triangular wave is approximated to a rectangle as much as possible when an internal clock is supplied to an internal circuit (not shown). That's why.

That is, as described in the description of the conventional example,
When a very high-speed DRAM or the like operating at a high frequency is considered as an internal circuit, it is preferable that a clock serving as a reference for operation is closer to a rectangular wave. Therefore, in the present embodiment, an internal clock having a trapezoidal waveform close to a rectangle is obtained by using a circuit having no logic threshold value but having a slight saturation characteristic in the last stage.

On the other hand, when an internal clock is supplied to the integration type input circuit, a triangular wave clock can be used as it is. That is, the integration type input circuit is provided with an integration circuit at its first stage, and the internal clock applied thereto is used only as a signal for determining an integration period in the integration circuit. In other words, even if the internal clock has a waveform like a triangular wave, the integration period can be determined almost correctly as long as the phase relationship between the data and the internal clock matches (the integration period is somewhat narrow or wide). The integrated value for determining 0/1 of the data is not so large.)

FIG. 3 is a diagram showing another embodiment of the internal clock generating circuit according to the present invention, in which the internal clock generated here is supplied to an integrating input circuit and other internal circuits. FIG. As shown in FIG. 3, in the present embodiment, the unsaturated differential amplifiers 11 to 13 are used.
Are connected in three stages to amplify an input triangular or sine wave clock. Of course, the invention is not limited to this number.

In the internal clock generation circuit of the present embodiment,
A buffer circuit having a slightly saturated characteristic corresponding to the quasi-unsaturated buffer 3 of FIG. 1 is not used. Therefore, the waveform of the internal clock output from the third-stage unsaturated differential 13 remains a triangular wave or a sine wave, similarly to the input clock. The internal clocks generated by the unsaturated differential amplifiers 11 to 13 are supplied to an integral input circuit 14 and a saturated buffer circuit 15.

The integration type input circuit 14 has two integration circuits of the same configuration in the first stage. One of the integrating circuits will be described. The integrating circuit includes a PMOS transistor 21a functioning as a switch for determining an integration period based on an applied internal clock, a PMOS transistor 22a receiving small amplitude data, and
PMOS transistor 23 supplied with reference voltage _Vref
a, a capacitor 24a connected to the PMOS transistor 22a for data, and a PMO for the reference voltage.
Capacitor 25a connected to S transistor 23a
And a cross-coupled amplifier 26a that amplifies the difference between the potentials charged in the two capacitors 24a and 25a. Corresponding components of another integration circuit are indicated by the same reference numerals with the letter b.

As shown in FIG. 3, an internal clock such as a triangular wave generated by the internal clock generating circuit of the present embodiment is applied to PMOS transistors 21a and 21b provided at the first stage of the integration type input circuit 14. Can be Then, these PMOS transistors 21a, 21b
Turns ON / OFF depending on whether the signal level of the internal clock exceeds the physical threshold value of the transistor.

As shown in FIG. 3, in this embodiment, two clocks having phases opposite to each other are input as input clocks. The above two PMOS transistors 21a, 2
1b is turned on with phases opposite to each other based on the internal clock generated from the input clocks having different phases. As a result, the integration is alternately performed by the two integrating circuits approximately every half cycle of the internal clock.
Note that the integration period may slightly overlap,
Since / 1 / is determined by the capacity of integration, there is no significant effect.

As described above, the integration type input circuit 14 is configured to directly perform integration by the integration circuit provided at the first stage. Therefore, the PMOS transistors 21a, 21
1b and the timing of the internal clock
It is necessary that the timing of the data supplied to the S transistors 22a and 22b substantially coincides. That is,
If there are many clock skews, the integration period cannot be set correctly, and the data cannot be read correctly. On the other hand, in the internal clock generating circuit according to the present embodiment, the skew can be minimized, so that the above-described inconvenience can be surely prevented.

On the other hand, the internal clock such as a triangular wave supplied to the saturation type buffer circuit 15 is formed into a rectangular wave clock here, and then supplied to another internal circuit 16.
As described above, in a circuit other than the integration type input circuit, in particular, in a very high-speed circuit operating at a high frequency, a clock serving as a reference for operation is preferably a rectangular wave, and thus a saturation type buffer circuit having a logical threshold value is used. 15 is used to obtain a rectangular wave clock.

It should be noted that the configuration of each part shown in the above embodiment is merely an example of the embodiment for carrying out the present invention, and thus the technical scope of the present invention is limited. It must not be interpreted. The present invention can be embodied in various forms without departing from the spirit or main features thereof. Therefore, the above embodiments are merely examples in all respects, and should not be construed as limiting.

[0033]

As described above, the internal clock generating circuit of the present invention has a dynamic range sufficiently larger than the amplitude of the input clock, and has a sufficiently large band for the Fourier component (harmonic component) constituting the input clock. The above internal clock generation circuit is composed of a logic circuit with a width,
A clock having a waveform whose rising / falling time is slower than that of a rectangular wave is input as an input clock to the internal clock generation circuit, so that the delay of the internal clock with respect to the input clock can be reduced, and the clock buffer can be reduced. The skew generated in the system can be significantly reduced as compared with the related art. As a result, it is not necessary to perform skew correction using a complicated circuit such as a PLL or a DLL, and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of an internal clock generation circuit according to the present invention.

FIG. 2 is a diagram for explaining the operation of the internal clock generation circuit according to the present embodiment shown in FIG. 1;

FIG. 3 is a diagram showing another embodiment of the internal clock generation circuit according to the present invention, showing an application example in which the generated internal clock is supplied to an integration type input circuit and other internal circuits. is there.

FIG. 4 is a diagram showing a configuration example of a conventional internal clock generation circuit.

FIG. 5 is a diagram for explaining an operation of a conventional internal clock generation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Unsaturation type input circuit 2 Unsaturation type buffer 3 Semi-unsaturation type buffer 11-13 Unsaturation type differential amplifier 14 Integral type input circuit 15 Saturation type buffer circuit 16 Other internal circuits 21a, 21b PMOS transistor Switch to decide)

Claims (6)

[Claims] 1. An internal clock generating circuit for processing an input clock to generate an internal clock, comprising a dynamic range sufficiently larger than the amplitude of the input clock, and a Fourier component (harmonic component) constituting the input clock. The internal clock generation circuit is composed of a logic circuit having a sufficiently large bandwidth with respect to the above. As the input clock to the internal clock generation circuit, a clock having a waveform whose rising / falling time is slower than that of a rectangular wave is input. An internal clock generation circuit characterized in that: 2. The internal clock generation circuit according to claim 1, wherein said logic circuit is an unsaturated logic circuit having no logic threshold value for determining an operating point. 3. The internal clock generation circuit according to claim 1, wherein the input clock is a clock having a triangular wave or a sine wave having a period slower than an operation speed of the logic circuit. . 4. The logic circuit according to claim 1, wherein the logic circuit includes an unsaturated input circuit to which a clock is input, and an unsaturated buffer circuit that amplifies an output of the unsaturated input circuit. 1 to
4. The internal clock generation circuit according to claim 3. 5. The unsaturated logic circuit according to claim 1, wherein the logic circuit includes an unsaturated input circuit to which a clock is input, an unsaturated buffer circuit for amplifying an output of the unsaturated input circuit, and an unsaturated buffer circuit. The internal clock according to any one of claims 1 to 3, wherein the internal clock comprises a quasi-unsaturated buffer circuit having a characteristic of low saturation and amplifying an output of the unsaturated buffer circuit. Generator circuit. 6. An internal clock generation circuit for generating an internal clock for determining an integration period in an integration type input circuit, wherein a rising / falling time is slower than that of a rectangular wave and a period of time is slower than an operation speed of the circuit. A circuit to which a clock having a waveform is input, the input having a dynamic range sufficiently larger than the amplitude of the input clock and a sufficiently large bandwidth for a Fourier component (harmonic component) constituting the input clock. An internal clock generation circuit comprising: a circuit; and an unsaturated buffer circuit that generates an internal clock by amplifying an output of the unsaturated input circuit.