JPH1185118A - Video overlay device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable setting an appropriate pixel clock frequency and adjusting an overlay coordinate. SOLUTION: When video reproduction software is started, a video window is displayed on a graphic screen. A start code and a finish code including a specific color pattern are generated by adjusting to the display timing of the video window. A code detecting circuit 405 detects these codes out of graphic signals 401. A coordinate counter 406 counts pixel clocks, and a pixel clock control circuit 408 adjusts frequencies of pixel clocks in a video overlay. And an overlay control circuit 409 detects a coordinate of the video window on a video overlay screen by counting adjusted pixel clocks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video overlay apparatus for overlaying an externally input image on a graphic screen of a computer at a specific position.

[0002]

2. Description of the Related Art FIG. 8 shows the overall configuration of a video overlay apparatus. The host computer 200 includes a video overlay block 201 and a graphic block 2.
02 is provided. Graphic block 202
Outputs a graphic screen of the host computer 200. Video overlay block 201
Is the VGA or X output from the graphic block 202.
A graphic signal 204 such as GA is input and a video image is overlaid on an area (window) designated by the host computer 200. When the video overlay output signal 205 is sent to the monitor 203, the user can see an externally input moving image on the graphic screen.

FIG. 9 shows graphic coordinates. The graphic coordinates are logical coordinates on the OS of the computer (PC). However, when displaying on the monitor 203, there is a blanking interval between the horizontal synchronization signal (hereinafter, referred to as HSYNC) and the origin Gx0 of the x-axis. Because of this blanking interval, the number of pixels between HSYNC cannot be uniquely determined. Coordinates Gx1, Gx2,
The theoretical values of Gy1 and Gy2 are known on the OS. The position of Gx1 on the monitor is (reference value of HSYNC + blanking section + Gx1). Therefore, if the time of the blanking interval is not known, the exact number of pixel clocks between HSYNC cannot be known.

FIG. 10 shows coordinates on a video overlay block. Vx1 and Vx2 can be determined by the count number of the pixel clock from HYSNC. Vy
1, Vy2 can be determined from the vertical synchronization signal (hereinafter, referred to as VSYNC) by the count number of HSYNC. However, since the pixel clock is not present in the graphic signal 204, the pixel clock must be reproduced by the video overlay block. To play this, (1) Graphic screen resolution (VGA, SVGA, X
GA, etc.) must be known. (2) Graphic screen refresh rate (VSYN
C frequency). (3) The horizontal and vertical blanking intervals must be known.

[0005] (1) can be known by the OS. (2) and (3) are generally unknown.
Therefore, in order to reproduce the pixel clock on the video overlay block, it is necessary to know the video display area (window) on the graphic screen in some way.

If the frequency of the pixel clock does not match between the graphic screen and the video screen, FIG.
As shown in (1), the graphic coordinate system (Gx, Gy) deviates from the video overlay coordinate system (Vx, Vy), and the position and size of the video display area A1 on the graphic screen and the display area A2 on the video overlay do not match. So, on the video overlay block,
If the pixel clock can be set to an appropriate frequency, the video display area on the graphic screen and the display area on the video overlay can be located at the same position.

FIG. 12 shows a configuration diagram of a conventional video overlay block 201. As an output signal 1 of the computer, VSYNC, HSYNC, and R, G, and B signals, which are graphic signals, are given to the video overlay block 201, respectively. On the other hand, when the video playback software in the GUI environment is started by the user, a rectangular area for video display (hereinafter referred to as a video window)
Is displayed. The computer indicates a video window to the video overlay block 201 by a graphic signal. At this time, the computer paints the area of the video window with a predetermined color (hereinafter referred to as a color key).

In this case, the R signal, the G signal, and the B signal each have a predetermined signal level in the video window. The color key detection circuit 2 detects a color key from three signal level values, and outputs a color key area signal
Output to the GB signal switching circuit 5. On the other hand, the digital video signal 7 to be overlaid on the graphic screen is input to the overlay control circuit 4 together with the video synchronizing signal 8 irrespective of the graphic signal.

The overlay control circuit 4 is composed of an IC, and the computer can set the coordinates of the video display area, the enlargement or reduction ratio of the video, the video display mode, etc. arbitrarily through the host bus 6. The digital video signal 7 input to the overlay control circuit 4
From the interlaced scanning signal to the non-interlaced scanning signal, and from the luminance signal and the color difference signal (hereinafter referred to as YUV signal),
It is converted to the same RGB signal as the graphic signal. After being subjected to signal processing according to the enlargement or reduction ratio set by the computer, it is stored in a dedicated video memory.

The overlay control circuit 4 receives HSYNC and VSYNC, which are the output signals 1 of the computer, and receives the pixel clock from the pixel clock generation circuit 3. The pixel clock generation circuit 3 generates a pixel clock having a frequency adapted to a graphic screen based on a signal input from a computer through the host bus 6. Then, the overlay control circuit 4 counts the input HSYNC, VSYNC, and pixel clock, respectively, and obtains coordinates on a graphic screen or converts a digital video signal into an analog RGB signal based on these count results.

The overlay control circuit 4 outputs a video window area signal 11 when the graphic signal is in the video window. Fig. 13
Shown in The vertical axis in FIG. 13 is the horizontal synchronization signal (HSYNC) 3
00, the horizontal axis indicates the vertical synchronization signal (VSYN).
C) 301 indicates a scan line to be output. The coordinate x1 indicates the horizontal start position of the video window 306,
The coordinate x2 indicates the end position. These coordinates x1 and x2 are obtained by counting pixel clocks from the HSYNC 300. Similarly, the coordinates y1 are displayed in the video window 306.
, And the coordinate y2 indicates the end position. Coordinates y1 and y2 are H from the reference point of VSYNC 301.
The SYNC 300 can be obtained by counting. The overlay coordinates are such coordinates x1, x2, y1, y
2 determined.

When the coordinate values based on the pixel clock and the HSYNC count fall within the overlay coordinates set by the computer, the overlay control circuit 4 outputs a video output 9 obtained by digital-to-analog conversion at the timing of the pixel clock and a video window area. The signal 11 is output to the RGB signal switching circuit 5. The RGB signal switching circuit 5 switches the computer output signal 1 to the video output 9 when the video window area signal 11 and the color key area signal 10 are both active. The output signal 12 supplied to the monitor in this manner is a signal obtained by overlaying a video signal input from the outside at a predetermined position on the graphic screen.

[0013]

However, in order for the video output 9 to be output at a predetermined position on the graphic screen in a timely manner, the pixel output must be adjusted in accordance with the R, G, and B signals output from the computer. The clock frequency must be set. In addition, the coordinates (graphic coordinates) of the video window and the video overlay coordinates (video coordinates) obtained from the overlay block 201 must match.

However, in order to generate a suitable pixel clock, the frequency of the pixel clock must vary with the frequency of the vertical synchronization signal, even if the resolution of the graphic screen of the computer is known.
In such a case, the conventional video overlay block 201 cannot accurately generate a pixel clock suitable for the image signal. To adjust the frequency of the pixel clock, it is necessary to determine the horizontal time of the video display area.However, the video display area detection method using the color key has an image of the same color as the color key other than the video display area. And accurate detection is not always possible.

A conventional video overlay block 2
In No. 01, since the number of pixel clocks and the number of lines in blanking cannot be specified, it is not possible to set accurate coordinates of a display position where a video image (moving image) is overlaid.

As described above, the initial state of the computer in which the pixel clock does not match the graphic signal,
When the computer user changes the resolution of the graphic screen or changes the frequency of the vertical synchronization signal, the conventional method is used to adjust the frequency of the pixel clock and set the video overlay coordinates. A special setting mode had to be provided and adjusted manually.

However, in the initial state where the pixel clock is not properly adjusted, adjusting the pixel clock anew and adjusting the video overlay coordinates is a complicated operation for a user who does not know the configuration of the apparatus. Become. Also, once the pixel clock and the coordinates of the video display area are set optimally, if the user changes the settings of the resolution of the graphic screen and the frequency of the vertical synchronization signal,
When the proper frequency of the pixel clock changes, it is necessary to adjust the frequency of the pixel clock and the position of the video overlay coordinates each time, which is not preferable in use.

The present invention has been made in view of such a conventional problem, and when software for displaying a video signal is started, an appropriate pixel clock is automatically converted from a graphic signal output from a computer. It is an object of the present invention to realize a video overlay apparatus having a function of adjusting a frequency and further obtaining a video overlay coordinate that matches a video window coordinate from a horizontal synchronization signal, a vertical synchronization signal, and a pixel clock on a graphic screen.

[0019]

In order to solve such a problem, the invention according to claim 1 of the present application provides a graphic screen for displaying a signal output from a computer on a specific window of the graphic screen. A video overlay device that displays an image input from an external device as an overlay image, which receives an external image signal, converts the image signal into a scanning image signal that can be displayed on the graphic screen, and is set by software of a computer. Video overlay control means for reducing and enlarging the image signal according to the reduction / enlargement ratio, and a start code and an end code for determining the coordinates of the window when the position of the window on the graphic screen is set by the software. Code generating means for generating, When overlaying the image signal in the window set by software,
A video overlay coordinate detection means for detecting overlay coordinates on the graphic screen based on a start code and an end code of the code generation means, and a pixel clock having an arbitrary frequency with a horizontal synchronization signal as a reference clock; Pixel clock adjusting means for adjusting the pixel clock so that the size of the overlay image matches the size of the window based on the overlay coordinates detected by the video overlay coordinate detecting means and the resolution of the graphic screen; and Image switching means for detecting a switching signal indicating a display area, switching from a graphic signal to the image signal, and outputting an image signal according to a pixel clock controlled by the pixel clock adjusting means. It is an feature.

According to a second aspect of the present invention, in the video overlay apparatus according to the first aspect, the code generation means uses a combination of specific color signals among R, G, and B signals to generate the first and the second color signals. A second stripe pattern is generated, and the first and second stripe patterns are used as a start code and an end code of a video overlay.

According to a third aspect of the present invention, in the video overlay apparatus according to the first aspect, the video overlay coordinate detecting means detects the start code and the end code generated by the code generating means. An x counter that counts a pixel clock output from the pixel clock adjusting unit while the code detection circuit detects the start code and the end code and generates an x coordinate of the window; A y counter for counting the number of horizontal synchronization signals of the graphic screen while the start code and the end code are detected by a circuit, and generating a y coordinate of the window. Generating the video overlay coordinates from the counting result. .

According to a fourth aspect of the present invention, in the video overlay device according to the first aspect, the pixel clock adjusting means uses a horizontal synchronization signal as a reference clock and a pixel clock having an arbitrary frequency based on a frequency control signal. A size of the overlay image and the window are matched based on a pixel clock generating circuit for generating and providing the video overlay control means to the video overlay control means and the resolution of the graphic screen and the overlay coordinates generated by the video overlay coordinate detection means. And a pixel clock control circuit for supplying the frequency control signal to the pixel clock generation circuit.

According to such a configuration, when the software is started from the computer and the moving picture is reproduced in a specific window, the pixel clock is automatically adjusted, so that the coordinates of the video overlay screen are appropriately adjusted. However, the image of the external input can be appropriately displayed in the window on the graphic screen without the user's hand.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video overlay device according to an embodiment of the present invention will be described with reference to the drawings. When the user starts the software in order to play back a video, the software program creates a video display area 602, which is a video display window, in a designated size, as shown in FIG. When a window position on the graphic screen is set by software, a code generation unit (not shown) generates a start code 605 and an end code 606 indicating a window range. Then, to adjust the pixel clock to the optimal value, the video display area 602
A predetermined color pattern determined by the start code 605 and the end code 606 is created. In this case, HSYNC and graphic signals are shown at the bottom of FIG. 1 to clarify the relationship between the graphic screen 601 and the time in the horizontal direction.

In order to clarify the relationship between the graphic screen 601, the vertical synchronizing signal, and the drawing section, VSYN
C and the vertical drawing section are shown in the right part of FIG. The sections 608 and 614 shown on the left and right are blanking sections in the horizontal direction in which the graphic screen is not displayed on the monitor.
The section 609 and the section 613 are sections of the graphic screen other than the video display area. Section 610 is a start code section, section 611 is a video display section, and section 612 is an end code section. Section 616 shown above and below
And the section 620 are vertical blanking sections.
The section 617 and the section 619 are sections of the graphic screen other than the video display section, and the section 618 is a video display section in the vertical direction.

FIG. 2 shows the configuration of the video overlay block 400 provided in the video overlay apparatus of the present embodiment. This video overlay block 400
Are a waveform shaping circuit 403, a comparison circuit 404, a code detection circuit 405, a coordinate counter 406, a pixel clock generation circuit 407, a pixel clock control circuit 408, an overlay control circuit 409, a color key detection circuit 410,
It is configured to include an RGB signal switching circuit 411. In addition,
The overlay control circuit 409 is composed of an IC,
Is the same overlay control means as the conventional overlay control circuit 4 shown in FIG. Further, detailed description of the circuits having the same names as those of the conventional example will be omitted.

As described above, the graphic screen includes HSYNC, which is included in the output signal 401 from the computer.
VSYNC is created by R, G, and B signals, which are analog graphic signals. Waveform shaping circuit 4
03 detects the rise or fall of HSYNC and VSYNC and outputs them to other circuits as HS420 and VS421, respectively. The reason based on the rise or fall is that HSY depends on the resolution of the graphic screen.
This is because the logics of NC and VSYNC change. Here, the timing when HSYNC and VSYNC become high level is defined as the synchronization timing of positive logic, and HS420 and VS421 are generated by the rising edge. Also, HS
The time when YNC and VSYNC go low is defined as negative logic synchronization timing.
20 and VS421 are generated.

The comparison circuit 404 is a circuit for comparing each of the R signal, the B signal, and the G signal with an arbitrary threshold voltage. FIG. 3 is a block diagram showing a specific configuration of the comparison circuit 404.
The comparison circuit 404 includes three voltage comparators 503 and 50
7,511. The voltage comparator 503 compares the graphic R signal 501 with the threshold voltage 502, and
This is a circuit that outputs a compare signal 504. The voltage comparator 507 is a circuit that compares a graphic G signal 505 with a threshold voltage 506 and outputs a G compare signal 508. The voltage comparator 511 has a graphic B
This circuit compares the signal 509 with the threshold voltage 510 and outputs a B compare signal 512.

Although an analog voltage comparator is used in this embodiment, a digital signal comparator may be provided after analog-to-digital conversion for comparison. Each of these voltage comparators compares with a threshold voltage and outputs an H level or L level comparison result.

These binary signals are applied to the code detection circuit 405 and the color key detection circuit 410 of FIG. The code detection circuit 405 determines the start code 605 and the end of the video display area from a combination of binary signals (strictly speaking, serial-parallel conversion of R, G, and B signals of a certain bit to form an 8-bit code). Code 606 is detected. FIG. 4 shows this state. Since this time is an initial state, the frequency of the pixel clock is not properly set. Therefore, in the present embodiment, the combination of the R compare signal 504 and the G compare signal 508 can be detected as a start and end code, and the B compare signal 512 is used as a synchronous clock that changes every pixel. Is drawn in the video window.

In the video display area 602, the display color 7
Since an image such as 02 is output line by line,
The stripe pattern of each color is drawn in the initial frame in the vertical direction. The code detection circuit 405
Using the compare signal 512 as a synchronization clock,
When the compare signal 504 and the G compare signal 508 match the set codes, a start code 605 and an end code 606 are output. Also, a code detection circuit 405
Is synchronized with HS420,
It is used as an interrupt signal to the host computer until the pixel clock reaches an appropriate frequency and only when both the start code 605 and the end code 606 are detected.

The reason is that even if the image signal has a specific pattern, it is a combination of finite colors,
This is because there is a possibility of erroneous detection. Also, in a computer system in a GUI environment, when a general mouse cursor comes over a drawing area used for a code in a video window, the code on the graphic screen is broken. Therefore, the adjustment range of the frequency of the pixel clock is limited to a valid line in which the start code and the end code are detected.

The start code 605 and the end code 6 in FIG.
Reference numeral 06 denotes a coordinate counter 406 and a pixel clock control circuit 40 as a code detection signal 416 as shown in FIG.
8 is output. The pixel clock generation circuit 407 includes:
PLL (Phase Locked)
An initial value is set via the host bus 412 by the video playback software when the software is activated. Then, a clock is oscillated by the pixel clock generation circuit 407 at the set frequency of the initial value.

The pixel clock control circuit 408 starts counting pixel clocks when the start code 605 is detected, and ends counting when the end code 606 is detected. Since the proper pixel clock count value can be determined from the size of the video window,
By comparing the actual pixel clock count value with the theoretical count value, it is possible to determine whether the current frequency of the pixel clock is high, low, or appropriate.

The result of this determination is loaded into a status register in the pixel clock control circuit 408. This loading is performed at the timing when the end code 606 is detected, and the computer can freely read out the determination result later. In the present embodiment, the host computer reads the determination result from the status register via the host bus 412 based on the signal of the INT 417. As a result, the pixel clock generation circuit 407 generates a pixel clock having an optimum frequency. When the frequency of the pixel clock is adjusted to an appropriate value, the pixel clock control circuit 408 outputs EVEN 413 to the code detection circuit 405. Here, the waveform shaping circuit 40
3, the comparison circuit 404, the code detection circuit 405, and the coordinate counter 406 constitute a function of a video overlay coordinate detection means. The color key detection circuit 410 and the RGB signal switching circuit 411 constitute an image switching unit.

The host computer operates the EVEN 41
3 can be obtained via the status register on the pixel clock control circuit 408, so that after adjusting the pixel clock, the operation for video overlay coordinate detection is performed as follows.
Change to drawing behavior in the video window. This is shown in FIG.

The number of pixels 801 indicates the number of pixel clocks from the start position of the video window. The pixel clock 802 is a pixel clock adjusted by the pixel clock control circuit 408 and the pixel clock generation circuit 407 as pixel clock adjustment means. The R compare signal 504, the G compare signal 508, and the B compare signal 512 are graphic signals binarized by the comparison circuit 404, respectively.
The start code 605 is synchronized with the pixel clock 802 by synchronizing the R compare signal 504 and the G compare signal 50.
8 is a signal that becomes active when a specific code is obtained by performing serial-parallel conversion on 8.

In the coordinate counter 406, the code detection circuit 405 detects the start code and the end code on the video window, and counts the pixel clock with reference to HSYNC to obtain the coordinates of the start position on the video overlay in the horizontal direction. Find the coordinates of the end position. Also, the coordinate counter 406 determines that the vertical direction is VSY
By counting the HSYNC of the line where the start code or the end code is detected with reference to the NC, the coordinates of the start position and the end position on the video overlay in the vertical direction are obtained. FIG. 6 shows this state.

The horizontal reference 901 indicates the output timing of the HS 420 and is used to clear the horizontal coordinate counter. The vertical reference 902 indicates the output timing of the VS421, and is used to clear the vertical coordinate counter. First start code 60 from horizontal reference 901
The count value obtained by subtracting 8 pixels from the count value up to 5 becomes the horizontal left coordinate 906 of the video display area 602. The count value from the horizontal reference 901 to the end code 606 is the light coordinates 907 of the video display area.

The vertical coordinates are obtained by counting HSYNC from the vertical reference 902 until either the first start code 605 or the end code 606 is detected. Therefore, the vertical top coordinate 908 of the video display area 602 is 1
This is the value obtained by subtracting the line. Also, the bottom coordinate 90 in the vertical direction
9 is the first start code 605 from the vertical reference 902
Alternatively, after detecting either one of the end codes 606, the count value is obtained by subtracting one line from the count value obtained by counting HSYNC until neither of them can be detected.

However, the counting of the coordinates in the vertical direction is controlled by detecting either the start code 605 or the end code 606. This is a countermeasure in the case where the start or end code is destroyed by the mouse cursor, but increases the possibility of erroneous coordinate counting due to erroneous code detection. Therefore, in the present embodiment, the procedure of counting the coordinates of the video display area 602 is performed again with another drawing data, so that the error of the coordinate count is eliminated. If the first count value and the second count value do not match, the host computer changes the drawing data again, performs coordinate detection, and recognizes the coordinates of the video display area by majority decision.

FIG. 7 is a configuration diagram of the coordinate counter 406. The horizontal count is x1 counter 1007 and X
H counter H, which is an HSYNC whose waveform has been shaped through the waveform shaping circuit 403 first.
Cleared by S1002. x1 counter 1007
Counts the left coordinates of the video display area, and the X2 counter 1008 counts the right coordinates of the video display area. That is, the x1 counter 1007 has the start code 6
Pixel clock 1001 until 05 becomes active
Count. The x2 counter 1008 counts until the end code 606 is input. The x1 register 1009 holds the count data of the x1 counter 1007. The x2 register 1010 is an x2 counter 1008
Holds the count data. These count data are read by the host computer. The x load 1017 includes the X1 register 1009 and the X2 register 1
010 is a signal for loading data. After detecting a start code and an end code in one line, the HS1002
Is output in synchronization with.

The vertical coordinate count is performed by the y1 counter 1013 and the y2 counter 1015, but is first cleared by the VS1005 which is VSYNC. The y1 counter 1013 counts the coordinates on the upper side in the vertical direction of the video display area, and the y2 counter 1015
Counts the lower coordinate in the vertical direction of the video display area. The y1 counter 1013 becomes active when detecting the first start code or end code, and counts the HS 1002 until the top detection signal 1011 becomes active. Then, it is cleared at the next VS1005.
The y2 counter 1015 outputs the top detection signal 1011
Becomes active when it can no longer detect either the start or end code,
It counts until the bottom detection signal 1012 becomes active. Then, it is cleared at the next VS1005.

The value of the y1 counter 1013 is held in the y1 register 1014, and the value of the y2 counter 1015 is
It is held in the register 1016. y1 register 1014
And the contents of the y2 register 1016 are stored in the host bus 1006.
Read by the host computer via The data in the y1 register 1014 and the y2 register 1016 is y
It is loaded by the load 1018, and is output when the bottom detection signal 1012 is active and the HS 1002 is active.

The coordinate counter 406 is provided with the status register 1019 as described above. The status register 1019 includes a top detection signal 1011, a bottom detection signal 1012, a start code 605, and an end code 6
06 is held at the timing of the HS 1002, and is freely read by the host computer via the host bus.
Therefore, after drawing the drawing data in the video display area, the host computer executes the above-described video display area coordinate detection procedure a plurality of times while monitoring the status of the status register 1019. Determine the coordinates.

When the video overlay coordinates are determined as described above, the same operation as in the conventional example is performed. That is, in FIG.
When a color key which is a combination of a specific R signal, G signal, and B signal is detected from the comparison result output by
A switching signal 422 is generated. RGB signal switching circuit 411
When the RGB switching signal 422 is provided, the computer switches the computer output signal 401 to the video output 414. The output signal 402 thus provided to the monitor
Is a signal in which a video signal input from the outside is overlaid on a predetermined position on a graphic screen.

Thereafter, when the position or size of the video window is changed by the user, the coordinates to be set in the overlay control circuit 409 and the pixel clock generation circuit based on the coordinates obtained by the video overlay coordinate detection means. If the frequency data to be set to 407 is determined, an appropriate pixel clock frequency and video display adapted to the video window can be realized.

[0048]

As described above, according to the present invention, when an externally applied image signal is displayed as a video overlay on a graphic screen of a computer, the image signal is not displaced on a window specified by software. External images can be displayed. Further, the frequency adjustment of the pixel clock and the detection of the coordinates of the video display screen, which have conventionally been performed manually by the user, can be automatically performed. Therefore, an optimal video overlay display environment can always be realized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a relationship between a graphic screen and a graphic signal in the present embodiment.

FIG. 2 is a configuration diagram of a video overlay device according to the embodiment of the present invention.

FIG. 3 is a configuration diagram of a comparison circuit used in the video overlay device of the present embodiment.

FIG. 4 is a time chart for detecting a drawing code when a pixel clock having an appropriate frequency is not set.

FIG. 5 is a time chart for detecting a drawing code after an appropriate pixel clock frequency is set in the present embodiment.

FIG. 6 is an explanatory diagram of an operation of a coordinate counter in video overlay coordinates.

FIG. 7 is a configuration diagram of a coordinate counter used in the video overlay device of the present embodiment.

FIG. 8 is a configuration diagram of a host computer having a video overlay function.

FIG. 9 is an explanatory diagram of graphic coordinates.

FIG. 10 is an explanatory diagram of video coordinates.

FIG. 11 is an explanatory diagram showing a deviation between graphic coordinates and video coordinates.

FIG. 12 is a block diagram illustrating a configuration example of a conventional video overlay device.

FIG. 13 is an explanatory diagram showing a relationship between a video window on a graphic screen and graphic coordinates.

[Explanation of symbols]

 200 host computer 201 video overlay block 202 graphic block 203 monitor 204 graphic signal 205 video overlay output signal 400 video overlay block 403 waveform shaping circuit 404 comparison circuit 405 code detection circuit 406 coordinate counter 407 pixel clock generation circuit 408 pixel clock control circuit 409 overlay Control circuit 410 Color key detection circuit 411 RGB signal switching circuit 503, 507, 511 Voltage comparator 1007 x1 counter 1008 x2 counter 1009 x1 register 1010 x2 register 1013 y1 counter 1015 y2 counter 1014 y1 register 1016 y2 register 1019 status register

Claims (4)

[Claims] 1. A video overlay device for displaying an image input from the outside in a specific window of the graphic screen as an overlay image on a graphic screen for displaying a signal output from a computer, comprising: Input and convert to a scanning type image signal that can be displayed on the graphic screen,
Video overlay control means for reducing or enlarging the image signal according to a reduction / enlargement ratio set by software of a computer, and for determining the coordinates of the window when the position of the window on the graphic screen is set by the software. Code generating means for generating a start code and an end code; and when overlaying the image signal on the window set by the software, overlay coordinates on the graphic screen based on the start code and the end code of the code generating means. And a pixel clock having an arbitrary frequency using the horizontal synchronization signal as a reference clock, and the overlay coordinates and the graph detected by the video overlay coordinates detecting means. Based on the resolution of Ikku screen, a pixel clock adjustment means for adjusting the pixel clock so that the size of the overlay image and the size of the window coincides detects a switch signal indicating the display area of the window,
An image switching unit for switching from a graphic signal to the image signal and outputting an image signal according to a pixel clock controlled by the pixel clock adjusting unit. 2. The code generating means generates first and second stripe patterns by using a combination of specific color signals among R, G, and B signals, and generates the first and second stripe patterns. 2. The video overlay apparatus according to claim 1, wherein? Is a start code and an end code of the video overlay. 3. The video overlay coordinate detecting means includes: a code detecting circuit for detecting the start code and the end code generated by the code generating means; and while the code detecting circuit detects the start code and the end code. An x counter that counts a pixel clock output from the pixel clock adjusting means and generates an x coordinate of the window; and a display of the graphic screen while the start code and the end code are detected by the code detection circuit. 2. A y-counter that counts the number of horizontal synchronization signals and generates a y-coordinate of the window, wherein the video overlay coordinate is generated from a count result of the x-counter and the y-counter.
A video overlay device as described. 4. A pixel clock generation circuit, comprising: a pixel clock generation circuit that generates a pixel clock having an arbitrary frequency based on a frequency control signal using a horizontal synchronization signal as a reference clock and provides the pixel clock to the video overlay control unit; Based on the overlay coordinates generated by the video overlay coordinate detection means and the resolution of the graphic screen,
2. The video overlay device according to claim 1, further comprising: a pixel clock control circuit that supplies the frequency control signal to the pixel clock generation circuit so that the size of the overlay image matches the window.