JPH1176582A - Control device of game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent illegal plays by an illegal means such as a false signal generator. SOLUTION: The second oscillator is provided for a counter block 102, etc., separately from the first oscillator (oscillator 101). The counter block 102 comprises a counter, a comparator, a setting register, etc., in addition to the second oscillator. The counter receives a pulse outputted from the second oscillator, attenuates a count value, and clears the count value to a predetermined value according to a clear signal outputted from the comparator. The comparator outputs the above-mentioned clear signal only at the time when a set value set at the setting register matches a counter value at the counter. In this way, the counter performs clearing on the basis of the second oscillator. In other words, the counter operates independently of the first oscillator. By this, it is difficult to identify the timing that the counter is cleared. Therefore, as it is impossible to match the timing of a 'hit', it is possible to prevent illegal games.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a gaming machine, and more particularly to a technique for preventing an illegal game.

[0002]

2. Description of the Related Art In a gaming machine such as a pachinko machine or a slot machine, "random" or "out" is determined by a random number value. The value of this random number matches the value of the counter (that is, the count value), and is changed within a predetermined value range every predetermined period (specifically, 2 to 4 milliseconds). That is, normally, the counter value is increased by one, and when the counter value is the upper limit value, the counter is cleared and circulated. For example, assuming that the predetermined value range is 0 to 299, when the counter value is 0 to 298, the counter value is increased by 1 and the counter value is 29
When it is 9, it is cleared to 0. Therefore, the counter is continuously updated periodically when the power of the gaming machine is turned on (or at the time of reset).

[0003] The above count value is often used for symbol display on a symbol display provided in a gaming machine. That is, when a game ball wins at the starting port for starting the symbol change, the count value when the winning is detected is read.
Then, according to the read count value (hereinafter referred to as “read value”), the contents of the symbol displayed on the symbol display are controlled. For example, it is assumed that only “7” in the above predetermined value range is a hit. If the read value is "7", control is performed such that the content of the symbol displayed on the symbol display is stopped in a "hit" mode (specifically, a hit symbol such as "777"). If the read value is a value other than "7", control is performed such that the content of the symbol displayed on the symbol display is stopped in a "losing" mode according to the value.

Here, the timing at which the game balls enter the starting port in the pachinko machine (hereinafter referred to as "winning timing") is uniform because the game balls behave randomly by a large number of obstacles arranged on the game board. Not. Therefore,
Even if the count value of the counter updated every predetermined period is read at the winning timing, the read value becomes a random value as a result. However, since the counter is updated every predetermined period, the cycle from the occurrence of a certain "hit" to the occurrence of the next "hit" becomes constant. The period is equal to the period when the count value goes around the predetermined value range,
Hereinafter, it is referred to as a “count period”. When the 300 values are updated every 4 milliseconds in the above example of the predetermined value range, the count cycle becomes 1.2 seconds. Therefore, if the game ball wins the starting port 1.2 seconds after the read value once reaches the hit value, the read value at that time also becomes the win value.

Incidentally, there is a so-called "body sensation device" which generates a signal such as vibration or sound at regular intervals. If the player turns on / off the launching device in accordance with the signal generated by the bodily sensation device, the game ball can be fired at regular intervals. In addition, depending on the operation pattern of the member, the player may be able to know the above-mentioned fixed cycle regardless of the sensation. Examples of the operation pattern of this member include a blinking pattern of a lamp provided on a game board surface, a sound effect emitted from a speaker, and an operation pattern of an accessory. Also,
The operation pattern of the member is generally operated at a timing independent of one cycle of the counter. However, if the operation is performed in synchronization with one cycle of the counter due to a design or manufacturing error, it becomes possible for the player to know the fixed cycle. If the player turns on / off the firing device according to the operation pattern of this member, the game ball can be fired at regular intervals. However, as described above, since a large number of obstacle nails are provided on the game board surface, the winning timing does not always occur periodically.

[0006]

However, the counter 1
If the game ball is fired in each cycle (1.2 seconds in the above example), the winning timing can be periodically generated. Therefore, it is possible to increase the probability of "winning" at the time of winning the starting opening. Therefore, if a game is played with a bodily sensation device or the like, a "hit" can be almost certainly generated. Such a fraudulent game is a game that is intentionally aimed at a "hit", and is unfair considering ordinary players who aim at a "hit" by chance and should not be allowed. The present invention has been made in view of such a point, and an object of the present invention is to provide a control device of a gaming machine for preventing an illegal game by an illegal means such as a bodily sensation device.

[0007]

According to a first aspect of the present invention, a CPU for controlling a gaming machine, a first oscillator for controlling the operation of the CPU, and a count read by the CPU are referred to. In a control device for a gaming machine having a counter for switching a game state based on a value, the counter is cleared based on a second oscillator provided separately from the first oscillator. Here, “clearing the counter” includes not only setting the count value to 0 but also setting it to a predetermined value such as an upper limit value or a lower limit value. According to the first aspect of the present invention, the counter is cleared by the second oscillator provided separately from the first oscillator. Therefore, it is difficult to specify the time when the counter is cleared. Even if a bodily sensation or the like is used in synchronization with the first oscillator, the counter is cleared by the second oscillator, so that the timing of "hit" cannot be adjusted. Therefore, illegal games can be prevented.

[0008]

According to a second aspect of the present invention, there is provided a game machine control device according to the first aspect, wherein:
The second oscillator is characterized by comprising a self-excited oscillation circuit. According to the invention described in claim 2,
Although the self-excited oscillation circuit outputs a pulse periodically, the interval between the pulses cannot be obtained with high accuracy and becomes non-uniform. Therefore, the timing at which the counter is cleared by the second oscillator also becomes non-uniform, and accordingly, the timing of "hit" also becomes non-uniform. Therefore, illegal games can be more reliably prevented.

[0009]

According to a third aspect of the present invention, there is provided a game machine control device according to the first aspect, wherein:
The second oscillator outputs a pulse at a different cycle for each gaming machine. According to the third aspect of the present invention, the cycle of clearing the counter by the second oscillator differs for each gaming machine. Therefore, the second game machine
Even if the period of the oscillator can be synchronized by unauthorized means such as a bodily sensation device, it cannot be synchronized with other gaming machines, and the possibility of "hit" is extremely low. Therefore, illegal games can be minimized.

[0010]

According to a fourth aspect of the present invention, there is provided a game machine control apparatus as set forth in the first aspect, wherein:
The second oscillator clears the counter at different periods over time. According to the fourth aspect of the invention, the cycle of clearing the counter by the second oscillator changes with time. Therefore, even if the period based on the second oscillator can be synchronized at a certain time by unauthorized means such as a bodily sensation, it cannot be synchronized at a later time, and the possibility of "hit" is extremely low. . Therefore, illegal games can be more reliably prevented.

[0011]

According to a fifth aspect of the present invention, a CPU for controlling a gaming machine, an oscillator for controlling the operation of the CPU, and a count value read by the CPU are referred to. And a counter for switching a gaming state based on the game machine. In the control device for the gaming machine, data for specifying a cycle for clearing the counter is stored in a recording unit different from a recording unit in which a program for controlling the gaming machine is recorded. Characterized in that it is recorded in According to the invention described in claim 5, the timing of clearing the counter is based on data recorded in a recording unit different from the recording unit in which the program for controlling the gaming machine is recorded. Since this data is recorded on a recording unit different from the recording unit on which the program for controlling the gaming machine is recorded, it is extremely difficult to analyze the period. Therefore, the timing of "hit" cannot be matched, and illegal games can be prevented.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, the present invention is applied to a pachinko machine that is one of gaming machines.

[Embodiment 1] First, in Embodiment 1, C
This is a mode in which an oscillator is provided separately from the oscillator that controls the operation of the PU, and will be described with reference to FIGS. Here, FIG. 1 is a front view showing the appearance of the pachinko machine. FIG. 2 is a block diagram showing the configuration of the control unit. FIG. 3 shows the first
Is shown in a block diagram of FIG. FIG. 4 is a flowchart showing the counting process. In FIG.
The configuration of the oscillator is shown in a circuit diagram.

First, in FIG. 1, on a game board surface 12 of a pachinko machine 10, a multifunction device 14, a first-type starting port 18,
The special winning opening 20 and the like are appropriately arranged and provided. The composite device 14 includes a gate sensor 38 and a normal symbol display 4
0, a special symbol display 42 and the like are provided. The first-type starting port 18 is one of the specific areas, and acts like a normal winning port to pay out a prize ball (prize ball). On the other hand, the gate only detects the passage of pachinko balls (game balls) by the gate sensor 38, and does not pay out prize balls. The ordinary symbol display 40 displays ordinary symbols (for example, alphanumeric characters and symbols). This ordinary symbol starts to fluctuate when the pachinko ball passes through the gate, and then stops. Special symbol display 4
2 displays a special symbol (for example, a picture, an alphanumeric character, a symbol, etc.). This special symbol starts to fluctuate when a pachinko ball is awarded in the first type starting port 18 and then stops.

The first-type starting port 18 is provided with a starting port sensor 34. This starting port sensor 34 is
When a pachinko ball that has won the seed starting port 18 is detected, a winning signal is output. The special winning opening 20 is provided with a lid 20 a, which is opened and closed by a solenoid 32. The special winning opening 20 is provided with a V zone 20b as a special area. If a pachinko ball wins in this V zone 20b at a certain time, the jackpot game state can be continued within a certain limit (for example, 16 times). Except for the game board surface 12, a lower plate 26 for temporarily storing pachinko balls including prize balls, and a speaker 2 for outputting sound effects, music, and the like.
8, a touch sensor 24 for detecting whether or not the player's hand is touching the handle 22, a firing motor 21 for operating the handle 22 to launch a pachinko ball, and detecting opening of the glass frame 17. A metal frame sensor 36 is provided. The speaker 28 is provided inside an upper plate 30 that is a receiving tray for award balls, and the touch sensor 24 and the metal frame sensor 36 are provided at predetermined positions. In addition, LEDs, light bulbs, and the like are used for the lamps 16 and are arranged at appropriate positions according to the game content of the pachinko machine 10 and the like.

Next, the main control section 100 will be described with reference to FIG. This main control unit 100
PU (processor) 110, oscillator 101, counter block 102, ROM 104, RAM 106, input processing circuit 108, output processing circuit 112, display control circuit 11
4. The communication control circuit 116 and the like. C
The PU 110 controls the pachinko machine 10 by executing a game control program recorded in the ROM 104 (recording unit). The CPU 110 operates according to pulses output periodically from the oscillator 101. Although an EPROM is used as the ROM 104, an EEPROM, a flash memory, or the like may be used. Various data or input / output signals are stored in the RAM 106. This RAM 106
A DRAM is used for this, but a nonvolatile memory such as an SRAM or a flash memory may be used. Note that the oscillator 101 is an embodiment of the first oscillator.

As shown in FIG. 3A, the counter block 102 includes an oscillator 102a, a counter 102b, a comparator 102c, a setting register 102d, and the like. The oscillator 102a is provided separately from the oscillator 101, and periodically outputs a pulse. Here, the oscillator 102a embodies a second oscillator. The oscillation frequency of the oscillator 102a is preferably different from the oscillation frequency of the oscillator 101, but may be the same. The counter 102b receives the pulse output from the oscillator 102a and counts up (updates) the count value.
I do. This counter 102b includes a setting register 102d
Receiving the clear signal output from the counter, the counter is cleared with a predetermined value (for example, 0). The setting register 102d
The set value set from the CPU 110 or the like via the bus 118 is temporarily recorded (stored). The comparator 102c outputs a clear signal when the count value of the counter 102b matches the set value of the setting register 102d, and does not output anything when they do not match.

Also, the counter block 102 is shown in FIG.
A configuration as shown in FIG. That is, instead of the setting register 102d, a ROM in which set values are recorded in advance
102e is used. In this case, the set value cannot be known from the CPU 110 or the like. Further, the ROM 10
If 2e is formed into one chip together with the counter 102b and the comparator 102c, the contents of the ROM 102e will not be analyzed. Therefore, it is extremely difficult to specify the time when the counter 102b is cleared. Therefore, illegal games can be more reliably prevented.

The setting register 102d and the ROM 10
It is more desirable that the set value set to 2e be set to a different value between the pachinko machines 10. For example, the setting value is specified based on data such as an ID number and a serial number recorded inside the CPU 110. By doing so, the cycle of clearing the counter 102b (that is, the count cycle) can be made different for each pachinko machine 10. Therefore, even if the counter cycle is found in a certain pachinko machine by a fraudulent means such as a bodily sensation device, the timing cannot be adjusted because the count cycles of other pachinko machines are different. Therefore, the possibility of "winning" with other pachinko machines is extremely low, and illegal games can be minimized.

The counter 102b operates according to the processing procedure shown in FIG. Here, the setting register 102d
Has already been set in the pachinko machine 10 in initialization processing or the like. In FIG. 4, when a pulse output from the oscillator 102a is received [Step S10], the counter 1
02b is counted up (updated) [Step S1
2]. If no pulse is received, the process proceeds to step S14 without doing anything. When the clear signal output from the comparator 102c is received [Step S14], the count value is cleared [Step S16]. If the clear signal is not received, the process proceeds to step S18 without doing anything. Further, when there is a request to access the count value from the CPU 110 or the like [Step S18], the count value is output [Step S20]. If the access request has not been received, the process proceeds to step S10 without doing anything to repeatedly execute the process.

According to the counter block 102, the counter 102b increases the count value according to the pulse periodically output from the oscillator 102a, and clears the count value according to the clear signal output from the setting register 102d. When operated in accordance with the above-described counting process, the period from when a clear signal is received at a certain time to when the next clear signal is received is a period in which the count value of the counter 102b goes around a predetermined value range (ie, a count cycle).
Is equal to The updated count value can be referred to at any time from the CPU 110 or the like via the bus 118.

Returning to FIG. 2, the input processing circuit 108 receives the respective detection signals sent from the starting port sensor 34 and the gate sensor 38, and converts them into a data format that can be processed in the main control unit 100. CPU 1 via bus 118
10 or to the RAM 106. On the other hand, the output processing circuit 112
Receives the operation data sent from the CPU 110 via the bus 118, and operates various operating devices provided in the pachinko machine 10, such as the lamps 16 and the solenoid 32. The display control circuit 114 receives display data sent from the CPU 110 via the bus 118, and controls the normal symbol display 40 and the special symbol display 42 to display characters, symbols, images, and the like. . The communication control circuit 116 is a circuit for transmitting and receiving data to and from the frame control unit 200. The frame control unit 200 is configured around a CPU similarly to the main control unit 100, and the configuration is publicly known, so detailed description is omitted. Note that the frame control unit 200 controls firing of a pachinko ball, payout of a prize ball, and the like necessary for performing a pachinko game, and outputs sound effects, music, and the like from the speaker 28, or the frame sensor 3.
Inspection of the door opening etc. at 6 is performed at a predetermined timing. Each of the above components is connected to the bus 118.

Next, a specific circuit configuration of the oscillator 102a shown in FIG. 3A will be described with reference to FIG. Here, FIG. 5A shows an oscillator using a crystal oscillator, FIG. 5B shows an oscillator using a resistor and a capacitor, and FIG. 5C shows an oscillator circuit in which inverters are connected in multiple stages. The configuration is shown respectively. The oscillator shown in FIG. 5A includes inverters (NOT circuits) Q2 and Q4, a resistor R2,
It is composed of a crystal resonator XL and capacitors C1 and C2. A resistor R2 and a crystal oscillator XL are connected in parallel to both ends of the inverter Q2.
1 and C2. An inverter Q4 is connected in series to the inverter Q2, and a pulse is periodically output from the output side of the inverter Q4. Note that another vibrator such as a ceramic vibrator may be used instead of the crystal vibrator XL. The oscillator shown in FIG. 5B includes inverters Q6 and Q8, a resistor R4, and a capacitor C
3. A resistor R4 is connected in parallel to both ends of the inverter Q6. Further, the capacitor C3, the inverter Q6, and the inverter Q8 are connected in series in this order. One side of the capacitor C3 not connected to the inverter Q6 is grounded, and
The pulse is periodically output from the output side of the. The value obtained by multiplying the value of the capacitor C3 by the value of the resistor R4 (= C3 ×
R4) is a time constant, which is substantially equal to the interval between output pulses. The oscillator shown in FIG. 5C includes four inverters Q10, Q12, Q14, and Q16. These inverters Q10, Q12, Q14, Q1
6 are connected in series. Further, the output side of the inverter Q14 is connected to the input side of the inverter Q10 to form a loop. Then, a pulse is periodically output from the output side of the inverter Q16. In this example, four stages are provided for the sake of simplicity, but in practice, tens to hundreds of inverters may be connected in multiple stages.
Each inverter delays by a very short time before the input pulse is output, and this delay time is proportional to the number of inverters connected in multiple stages. Therefore, the number of inverters n
Is multiplied by the delay time t (= n × t) is approximately equal to the interval between the output pulses. The oscillator 102a includes not only the self-excited oscillation circuit, but also a multivibrator, a blocking oscillation circuit, a Colpitts oscillation circuit, a Hartley oscillation circuit, a phase-shift oscillation circuit, a piezoelectric oscillation circuit, a Meissner oscillation circuit, a phase-locked oscillation circuit, and the like. And other self-excited oscillation circuits.

FIG. 6 shows a hit judging process for judging hit / los in the pachinko machine 10. The hit determination process is repeatedly executed at predetermined intervals. In FIG. 6, first, it is determined whether or not a pachinko ball has won the first type start port 18 [Step S3].
0]. Specifically, the determination is made based on whether or not a winning signal output from the starting port sensor 34 has been received. If a pachinko ball wins in the first kind starting port 18 (YE
S), the count value of the counter 102b is obtained from the counter block 102 [Step S32]. Thereafter, it is determined whether or not the obtained count value matches the hit value (step S34). When the acquired count value matches the winning value (YES), a big hit process is performed [Step S36]. The jackpot process controls, for example, the content of the special symbol displayed on the special symbol display 42 to be stopped in a “big hit” mode, or the special jackpot 20.
Various processes for a jackpot game, such as opening and closing control of the lid 20a, are performed.

The setting value set in the setting register 102d shown in FIG. 3A may be updated as needed [Step S38]. This update may be performed for each big hit, or may be performed every fixed period (or indefinite period). By doing so, the counter 102
The cycle for clearing b (that is, the count cycle) can be expanded or contracted. Therefore, the count cycle also changes differently with time, and it is extremely difficult to match the timing. Therefore, illegal games can be more reliably prevented. On the other hand, when the pachinko ball does not win in the first type start-up port 18 in step S30, or when the count value acquired in step S34 does not match the hit value, the hit determination processing is terminated without doing anything.

According to the first embodiment, the oscillator 101
Oscillator 102a provided separately from (first oscillator)
The counter 102b is cleared based on the (second oscillator). In other words, the counter 102b operates independently of the oscillator 101. Therefore, it is difficult to specify the time when the counter 102b is cleared. Even if a bodily sensation or the like is used in synchronization with the oscillator 101, the counter 102b is cleared based on the oscillator 102a, so that the timing of "hit" cannot be adjusted. Therefore, illegal games can be prevented. Further, since the oscillator 102a is constituted by the self-excited oscillation circuit, the interval between the pulses cannot be so high, and becomes non-uniform. Therefore, the cycle of clearing the counter 102b by the oscillator 102a (ie, the count cycle) also becomes non-uniform. Therefore, illegal games can be more reliably prevented.

[Embodiment 2] Next, in Embodiment 2, C
This is a mode of specifying a period for clearing the counter by an oscillator that controls the operation of the PU, which will be described with reference to FIGS. Here, FIG. 7 is a block diagram showing the configuration of the second control unit. 8 and 9 are block diagrams each showing the configuration of the counter block. Note that the same elements as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. Also, the configuration of the pachinko machine 10 is the same as that of the first embodiment, and the description is omitted.

The main control unit 100 shown in FIG. 7 outputs the pulse generated by the oscillator 101 not only to the CPU 110 but also to the CPU 110.
The difference from the main control unit 100 in FIG. The counter block 103
The point of having the frequency divider 103a as shown in FIG.
Is substantially different from the counter block 102 of FIG. That is, the counter 103b includes the counter 102b and the comparator 1
03c is the same as the comparator 102c, and the setting register 103d is the same as the setting register 102d. Here, the frequency divider 103a receives the pulse output from the oscillator 101, divides the pulse based on the frequency division value, and outputs the frequency-divided pulse. This frequency division value can be set at any time from the CPU 110 via the bus 118. Therefore, it is desirable to set a different value for each pachinko machine 10 or at an appropriate time such as a big hit. For example, the frequency dividing value is specified based on data such as an ID number or a serial number recorded inside the CPU 110. By changing the frequency division value in this way, the interval between pulses sent to the counter 103b changes. Therefore, the count cycle changes. The counter 103b operates according to the count process shown in FIG. 4, and the determination of the hit / los is performed according to the hit determination process shown in FIG.

Further, in the first embodiment, the set value is set to R
In the same manner as previously recorded in the OM 102e, the frequency division value may be recorded in the ROM 103e as shown in FIG. In this case, the frequency division value cannot be known from the CPU 110 or the like. Further, the ROM 103e is stored in the counter 103b.
And one-chip with comparator 103c, ROM
The content of 103e is not analyzed. Counter 10
Since it is not possible to specify the interval between the pulses supplied to 3b, it is extremely difficult to specify the time when the counter 103b is cleared. Therefore, illegal games can be more reliably prevented.

According to the second embodiment, the frequency divider 103
By changing the frequency division value set to a, the counter 103b
Is also changed. Since the count cycle changes in this way, even if the count cycle at a certain time is known by an unauthorized means such as a bodily sensation, the timing cannot be adjusted to the next cycle. Here, the frequency division value is set based on data recorded in the inside (recording unit) of the CPU 110 different from the ROM 104 (recording unit in which a program for controlling the gaming machine is recorded). It is extremely difficult. Therefore,
The timing of the "hit" cannot be adjusted, and illegal play can be prevented.

[Other Embodiments] In the control device for a gaming machine described above, the structure, shape, size, material,
The number, arrangement, operating conditions and the like are not limited to the above embodiment. For example, each of the following embodiments to which the above embodiment is applied may be implemented. (1) In the first and second embodiments, the counter 102b,
The period for clearing 103b is specified by data such as an ID number and a serial number recorded inside the CPU 110. Not limited to this mode, the counters 102b and 103b may be based on data (set values and frequency division values) recorded in other elements other than the ROM 104, other computers, or the like.
May be specified. That is, the counting cycle is specified based on data recorded on a recording unit different from the recording unit on which the program for controlling the pachinko machine 10 (game machine) is recorded. Here, examples of the other elements include a ROM in the input processing circuit 108 and the communication control circuit 116 shown in FIG. As another computer, the frame control unit 2 connected by a communication line via the communication control circuit 116 as shown in FIGS.
00 and hall computer 300. In this case, the CPU 110, which has received data from these elements or a computer, sets a set value in the setting register 102d in the counter block 102, or
What is necessary is just to set a frequency division value to a.

(2) According to the above (1), in order to prevent illegal play, based on data (set values and frequency division values) recorded in other elements except the ROM 104 and other computers, etc. , The period for clearing the counter may be specified. Therefore, the present invention can be similarly applied to the conventional pachinko machine 10 (game machine). For example, as shown in FIG. 10, a counter 106a is provided in the RAM 106, and a timer 107 that outputs an interrupt signal every period specified based on the data is provided. Then, C receiving the interrupt signal output from the timer 107
The PU 110 clears the counter 106a. According to the above (1) and (2), it is not possible to determine what the set values and the dividing values are by merely analyzing the ROM 104 in which the program for controlling the pachinko machine 10 is recorded. Therefore, it is difficult to analyze the count cycle, and it is possible to prevent a fraudulent game.

(3) In the first and second embodiments, the data for specifying the period for clearing the counter is stored in the CPU 110.
Was recorded in a part (recording section) of the. Not limited to this mode, the recording unit may be provided in part (or all) of another element, or may be provided in part (or all) of a recording medium accessible by another computer or the like. As this recording medium, R
There are OMs, hard disks, optical (magnetic) disks, flexible disks, bar codes, cards such as paper cards and magnetic cards, and printed matter on which characters, symbols, and the like are printed.

(4) In the first and second embodiments, since the counters 102b and 103b count up, they are cleared to a predetermined value (for example, 0). In the case where the counters 102b and 103b count down instead of this mode, the counter is cleared with a predetermined value (for example, 299) different from the above-mentioned predetermined value. At this time, a countdown (update) is performed in step S12 in the count process shown in FIG. The value to be cleared (updated) may be an arbitrary value (for example, 100). Further, the counters 102b and 103b may be k-ary n-digit counters and have a m-digit value accessible from the CPU 110 or the like. Here, k, n, and m are all integers, and the relationship of k> 1, n> 1, and n>m> 1 holds. In this case, clearing is performed within the range of m digits. For example, four decimal digits (k = 10, n =
When the counters 102b and 103b of 4) are used, 0
Values between 000 and 9999 can be counted. At this time, if the value accessible from the CPU 110 or the like is three digits (m = 3), the possible values are 000 to 99.
It becomes 9. In this example, when the counters 102b and 103b count up after 0999, they become 1000. However, when viewed from the CPU 110 or the like, the counters are cleared from 999 to 000. This is the same when counting down. As described above, even if the counter is not positively cleared by a clear signal or the like, the CPU 110
Etc. can be cleared. The same applies to the case where a counter in which at least one digit of the n-digit counter is another progressive number is applied. For example, a counter in which the lower two digits of a 5-digit decimal counter are counted in a binary number. Further, as in the second embodiment, the oscillator 10
It is more desirable that the pulse output from 1 be divided by the frequency divider 103a before being sent to the counter, since the count cycle changes.

(5) In the first and second embodiments, as shown in FIG. 6, the values of the counters 102b and 103b at the time of winning the first-type starting port 18 are obtained as random numbers and are compared with the hit values. It was determined above whether or not it was a hit. Instead of this mode, in the main control unit 100 shown in FIG.
The value of the counter 106a at the time of winning the first-type starting port 18 is obtained as a random number [Step S32], and the values of the counters 102b and 103b are obtained as a hit value [Step S33]. The random number thus obtained is compared with the winning value to determine whether or not the winning is achieved [Step S
34]. In this case, since the hit value changes, the count cycle also changes. Therefore, the timing of "hit" cannot be adjusted, and illegal games can be prevented.

(6) In the first and second embodiments, the present invention is applied to the pachinko machine 10. Not limited to this mode, a CPU that controls a gaming machine, such as an arrangement ball machine or a video game machine, and an oscillator that controls the operation of the CPU,
The present invention can be applied to a gaming machine having a counter for switching a gaming state based on the count value read and read by the CPU. Even in this case, effects similar to those of the first and second embodiments can be obtained.

[0037]

Other Embodiments The embodiments of the present invention have been described above. This embodiment has aspects of the invention other than the aspects of the invention described in the claims.
Embodiments of the present invention will be enumerated below, and related explanations will be provided as necessary.

[Aspect 1] CPU for controlling a gaming machine
And a first oscillator controlling the operation of the CPU, and the CPU
And a counter for switching a game state based on the count value read with reference to the second oscillator provided separately from the first oscillator. A game machine control device characterized by updating a value. [Relevant Description of Aspect 1] According to this aspect, the count value of the counter is updated by the second oscillator provided separately from the first oscillator. Since the counter operates independently of the first oscillator, it is difficult to specify the count cycle. Even if a bodily sensation or the like is used in synchronization with the first oscillator, the count value of the counter is updated by the second oscillator, so that the timing of "hit" cannot be adjusted. Therefore, illegal games can be prevented.

[Aspect 2] CPU for controlling gaming machine
And an oscillator controlling the operation of the CPU, and a counter for switching the game state based on the count value read and referenced by the CPU. For controlling the game machine, wherein the data for the game machine is recorded on a recording medium different from a recording medium on which a program for controlling the game machine is recorded. [Relevant Description of Aspect 2] According to this aspect, data is recorded on a recording medium different from a recording medium on which a program for controlling a gaming machine is recorded. Therefore, even if the program is analyzed, it is not possible to specify the period for clearing the counter. Therefore, the timing of "hit" cannot be matched, and illegal games can be prevented.

[0040]

According to the present invention, since the counter is cleared by the second oscillator provided separately from the first oscillator, it becomes difficult to specify when the counter is cleared. Therefore, illegal games can be prevented.

[Brief description of the drawings]

FIG. 1 is a front view showing the appearance of a pachinko machine.

FIG. 2 is a block diagram illustrating a configuration of a first control unit.

FIG. 3 is a block diagram showing a configuration of a first counter block.

FIG. 4 is a flowchart illustrating a count process.

FIG. 5 is a circuit diagram showing a configuration of an oscillator.

FIG. 6 is a flowchart illustrating a hit determination process.

FIG. 7 is a block diagram illustrating a configuration of a second control unit.

FIG. 8 is a block diagram showing a configuration of a second counter block.

FIG. 9 is a block diagram illustrating a configuration of a second counter block.

FIG. 10 is a block diagram illustrating a configuration of a third control unit.

[Explanation of symbols]

 DESCRIPTION OF REFERENCE NUMERALS 10 Pachinko machine (game machine) 18 Type 1 starting port 34 Starting port sensor 38 Gate sensor 100 Main control unit 101 Oscillator (first oscillator) 102 Counter block 102 a Oscillator (second oscillator) 102 b Counter 102 c Comparator 102 d Setting register 104 ROM 106 RAM 200 Frame control unit 300 Hole computer

Claims (5)

[Claims] 1. A CPU for controlling a gaming machine and its CP
A game machine control device comprising a first oscillator for controlling the operation of U and a counter for switching a game state based on a count value read and referenced by the CPU, wherein the control device is provided separately from the first oscillator. A controller for the gaming machine, wherein the counter is cleared based on the second oscillator. 2. The control device for a gaming machine according to claim 1, wherein said second oscillator is constituted by a self-excited oscillation circuit. 3. The control device for a gaming machine according to claim 1, wherein the second oscillator clears the counter at a different cycle for each gaming machine. 4. The control device for a gaming machine according to claim 1, wherein said second oscillator clears said counter at different periods over time. 5. A CPU for controlling a gaming machine and its CP
In a control device for a gaming machine having an oscillator controlling the operation of U and a counter for switching a gaming state based on a count value read by reference to the CPU, data for specifying a cycle for clearing the counter is provided. Is recorded on a recording unit different from a recording unit on which a program for controlling the gaming machine is recorded.