JPH1174898A - Cell assembling disassembling device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process constant bit rate CBR data and variable bit rate VBR data at the same time by uniformizing traffic in the case of assembling/ disassembling CBR and VBR cells so as to reduce a delay time and a fluctuated time of the CBR cells. SOLUTION: The device is provided with a clock extract section 6 that extracts a network clock synchronously with an asynchronous transfer mode ATM network, a synchronizing signal transmission section 3 that outputs a synchronizing signal with a prescribed period and a frame signal denoting a periodic number based on the network clock, an SAR function section that assembles/disassembles CBR data sent/received to/from a TDM transmission line and a CBR cell sent/received to/from an ATM transmission line and assembles/disassembles VBR data sent/received to/from a packet bus and a VBR cell sent/received to/from an ATM transmission line, and a cell processing function section A1 that controls assembling/disassembling of CBR data and CBR cell when CBR data are received/outputted and controls assembling/ disassembling of VBR data and VBR cell for other time zone.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function of assembling, into an ATM cell, real-time data such as audio and video which requires a constant bit rate and real-time performance, and packet data whose information amount changes with time. The present invention relates to a cell assembling / disassembling apparatus having a function of decomposing ATM cells into real-time data and packet data.

Here, an ATM cell having a constant transmission rate corresponding to real-time data is stored in a CBR (Constant Bit Rat).
e) An ATM cell whose transmission rate is variable corresponding to packet data is called a VBR (Variable bit rate) cell. Real-time data is called CBR data, and packet data is called VBR data.

[0003]

2. Description of the Related Art In an ATM (asynchronous transfer mode), when assembling signals such as voice, video and data into ATM cells, an AAL (ATM Adaptation) standardizing information to be added in order to absorb differences in quality conditions between the cells. Layer)
Is stipulated. This AAL is a cell assembling / disassembling sublayer (SAR: Segmentation) that provides a function on a cell-by-cell basis.
and Reassembly Sublayer) and the convergence sublayer (CS:
Convergence Sublayer).

FIG. 7 is a block diagram showing a configuration example of a conventional cell assembling / disassembling apparatus.

In the conventional cell assembling / disassembling apparatus, an apparatus for assembling / disassembling a CBR cell (hereinafter, referred to as “CBR-SAR”) 71 and an apparatus for assembling / disassembling a VBR cell (hereinafter, referred to as “VBR-SAR”) 72 are provided. Each is provided exclusively. CBR-SAR71 and VBR-SAR72
Is controlled by a control unit 73 and connected to an ATM network 75 via a multiplexing device 74. A transmission buffer 76 and a reception buffer 77 are connected to the multiplexer 74,
When the R cell and the VBR cell compete with each other, control is performed to give priority to the CBR cell or discard the VBR cell.

For the operation of the multiplexing device 74, for example, the technology disclosed in Japanese Patent Application Laid-Open No. 3-235448 (ATM cell multiplexing system) can be used. That is, it is determined whether or not the CBR cell and the VBR cell compete by checking the presence or absence of the CBR cell. If the CBR cell and the VBR cell compete, the CBR cell is prioritized. If there is no CBR cell, CB
The transmission band of the R cell is used by the VBR cell.

[0007]

In the conventional cell assembling / disassembling apparatus, the CBR-SAR 71 and the VBR-SAR 72 operate independently to perform the assembling / disassembling of the cell.
The multiplexing device 74 separately performs contention control and the like. That is, the mutual cooperation between the CBR-SAR 71 and the VBR-SAR 72 has been realized through the function of the multiplexer 74.

Further, the multiplexing device 74 requires a large amount of buffers to respond to instantaneous traffic.

Further, when real-time data is handled using the VBR-SAR 72, it has been difficult to realize delay fluctuation absorption buffer control and cell loss control. In particular, it was not possible to connect directly to the real-time line interface. On the other hand, the CBR-SAR 71 has a problem that it does not have a processor bus interface for processing packet data.

According to the present invention, the traffic when assembling and disassembling a CBR cell and a VBR cell is made uniform, and the CBR data and the VB cell are reduced while reducing the delay time and fluctuation time of the CBR cell.
An object of the present invention is to provide a cell assembling / disassembling apparatus capable of simultaneously handling R data.

[0011]

According to the present invention, there is provided a cell assembling / disassembling apparatus for extracting a network clock synchronized with an ATM network, and a synchronization signal having a constant period and its cycle number based on the network clock. A synchronizing signal transmitting unit for outputting a frame signal, and a CB transmitted and received on a TDM transmission line.
A SAR function unit that performs assembling and disassembling between R data and CBR cells transmitted and received on an ATM transmission line, and performs assembling and disassembly between VBR data transmitted and received on a packet bus and VBR cells transmitted and received on an ATM transmission line. Based on the synchronizing signal and the frame signal, control the assembly and disassembly of CBR data and CBR cells during input / output of CBR data, and control the assembly and disassembly of VBR data and VBR cells in other time zones. A functional unit.

[0012] Further, the celling function unit is a CBR for temporarily buffering CBR data transmitted / received to / from the TDM transmission line.
A buffer unit, a VBR buffer unit for temporarily buffering VBR data transmitted / received to / from the packet bus, and a CBR
CBR data and AT buffered in the buffer unit
An SAR function unit that performs disassembly and disassembly between CBR cells transmitted and received on the M transmission line, and disassembles and disassembles VBR data buffered in the VBR buffer unit and VBR cells transmitted and received on the ATM transmission line; Based on the synchronizing signal and the frame signal, when inputting / outputting CBR data, the SAR function unit and the CBR buffer unit are controlled to assemble and disassemble the CBR cell.
A control unit that controls the buffer unit to assemble and disassemble the VBR cell.

[0013] The celling function unit may include a CBR cell buffer unit for buffering CBR cells and a VBR cell buffer unit for buffering VBR cells.

[0014]

FIG. 1 is a block diagram showing an embodiment of a cell assembling / disassembling apparatus according to the present invention.

The cell assembling / disassembling apparatus comprises a cell-forming function unit A
1. Synchronous signal sending unit 3 and clock extracting unit 6 As an interface, T on the non-ATM side
DM transmission lines 100 and 101, packet bus 200, AT
M transmission path 401, CPU bus 504, synchronization signal 301,
A frame signal 302 and a network clock 601 are provided.

The TDM transmission lines 100 and 101 are transmission lines of the time division system, for example, transmission lines of the TTC standard. The packet bus 200 is a bus having a bandwidth of several hundred mega. The CPU bus 504 is a control processor bus connected to an external host CPU. The ATM transmission path 401 is a broadband transmission path connected to an ATM network.
The clock extracting unit 6 has a function of extracting a network clock synchronized with the ATM network from the physical signal of the ATM transmission line 401, and generates the extracted network clock 601 and supplies it to the synchronization signal transmitting unit 3. The function of the clock extracting unit 6 is publicly known.

Next, the operation of the synchronization signal transmitting section 3 will be described.
This will be described with reference to FIG.

The synchronizing signal transmitting section 3 indicates a PLL 31 which synchronizes with the network clock 601, a frequency dividing circuit 32 which generates a synchronizing signal 301 having a constant period based on the synchronizing clock of the PLL 31, and a cycle number of the synchronizing signal 301. It comprises a counter circuit 33 for generating a frame signal 302. The synchronization signal 301 is, for example, a signal of 8 kHz, and the frame signal 302 is a signal that repeats 0 and 1 at a period of 8 kHz. By synchronizing the synchronization signal transmitting unit 3 with the ATM network in this manner, real-time data such as voice can be handled.

Next, the configuration and functions of the cell function unit A1 will be described with reference to FIGS.

As shown in FIG. 2, the cell function unit A1
CBR buffer unit 1, VBR buffer unit 2, SAR
It comprises a function unit 4 and a control unit 5.

As shown in FIG. 3 (a), the CBR buffer unit 1 terminates the signals on the TDM transmission lines 100 and 101.
DM termination unit 17 and C received from TDM transmission line 100
Buffer A11 and buffer A for storing BR data
12, a TDM reception control unit 10 for switching between the buffers A11 and A12, a buffer C13 and a buffer D14 for storing CBR data to be transmitted to the TDM transmission line 101, and a buffer C13 and a buffer D14.
TDM transmission control unit 15 for controlling the switching of
00 and each function of the common bus interface unit 16 for transferring CBR transmission / reception data.

As shown in FIG. 3B, the VBR buffer unit 2 includes a packet bus terminating unit 21 for terminating the packet bus 200, a memory unit 22 for storing VBR data, a common bus 400 and VBR transmission / reception data. It has each function of the common bus interface unit 23 that performs transfer.

As shown in FIG. 4, the SAR function unit 4 includes a common bus interface unit 41 having a function of transmitting and receiving data on the common bus 400 and distributing the data, a CBR cell-forming decellularizing unit 42 for assembling and disassembling CBR cells. , A CBR cell buffer unit 45 for temporarily storing CBR cells, a VBR cell conversion decellulation unit 43 for assembling and disassembling VBR cells, and a VBR
It has the functions of a VBR cell buffer 46 that temporarily holds cells and a cell demultiplexer 44 that simply demultiplexes cells. The functions of the CBR cell-forming decellularizing unit 42 and the VBR cell-forming decellularizing unit 43 are, for example, those described in ITU-T I.T. 3
63.

The control section 5 is a functional section including a processor function.

The common bus 400 comprises an address bus, a data bus, and control signals. Each of the buffers A11, B12, and C1 of the CBR buffer unit 1
3, a mechanism capable of controlling the entire physical address space of the buffer D14 and the memory unit 22 of the VBR buffer unit 2. The access method is performed by a DMA method, for example.
The configuration is such that the common bus interface unit 41 of the SAR function unit 4 serves as a master and can execute transmission / reception control of CBR data and VBR data.

In actually executing the DMA, the control unit 5 determines the physical position (which address is to be read or written). The control unit 5 is controlled (set) in advance by a host CPU connected to the CPU bus 504.

Next, the operation of the cell function unit A1 will be described.

The celling function unit A1 operates in synchronization with the synchronization signal 301 and the frame signal 302 output from the synchronization signal transmitting unit 3.

The control unit 5 controls the CBR buffer unit 1 based on the synchronization signal 301 and the frame signal 302,
It is determined whether to control the VBR buffer unit 2. More specifically, CB is a fixed time from when the synchronization signal 301 changes.
Control is performed to enable the R buffer unit 1 and enable the VBR buffer unit 2 at other times.

Here, the fixed time for enabling the CBR buffer unit 1 corresponds to the transmission band time of the TDM transmission lines 100 and 101, and the time is set by the host CPU connected to the CPU bus 504. You. More specifically, CB is a fixed time from when the synchronization signal 301 changes.
Enable the R control signal 500. When the CBR control signal 500 is invalid, the VBR control signal 501 is valid.

The control unit 5 further includes a SAR control signal 505
To control the SAR function unit 4 to operate the CBR cell deceleration unit 42 or the VBR cell deceleration unit 43
Controls whether to operate.

Hereinafter, in the cell function unit A1, (1) T
The operation between the DM transmission lines 100 and 101 and the ATM transmission line 401 and (2) the operation between the packet bus 200 and the ATM transmission line 401 will be described separately.

(1) TDM transmission lines 100 and 101 and ATM
Operation Between Transmission Paths 401 (1-1) Operation of CBR Buffer Unit 1 and Access Operation of Common Bus 400 CBR data input from TDM transmission path 100
Under the control of the DM reception control unit 10, the data is alternately written to the buffers A11 and B12. Regarding which of the buffer A11 and the buffer B12 is enabled,
The determination is made based on the frame signal 302. The TDM reception control unit 10 enables the buffer A11 when the frame signal 302 is “0”, and enables the buffer B12 when the frame signal is “1”.

The control for transmitting the signal to the TDM transmission line 101 is performed in the same manner by the TDM transmission control unit 15.
The transmission control unit 15 controls the buffer C based on the frame signal 302.
13 is enabled or the buffer D14 is enabled.

Here, the actual operation will be described with reference to the time chart of FIG. The operation will be briefly described based on the time T.

In the TDM transmission line data reception control, at time T = 0, the data of the TDM transmission line 100 is stored in the buffer A11.
Is written to the buffer B12 at time T = 1, and thereafter, the data is alternately written to the buffer A11 and the buffer B12. After that, the data in the buffers A11 and B12 is temporarily stored and then sent to the common bus 400 via the bus 160 under the control of the control unit 5. Here, the bus 160 is a bus having an address bus, a data bus, and a read control signal.

The control unit 5 performs CBR based on the synchronization signal 301.
A control signal 500, a CBR data read signal (hereinafter referred to as “CBR-RD signal”) 513, and a CBR data write signal (hereinafter referred to as “CBR-WR”) 514 are transmitted to the common bus interface unit 16 of the CBR buffer unit 1. .

The common bus interface unit 16 has a CBR
When the control signal 500 is “1”, the CBR-RD signal 513 is “1”, and the frame signal 302 is “1”, the contents of the buffer A11 are sent to the common bus 400, and the frame signal 302 is “0”. At this time, the contents of the buffer B12 are sent to the common bus 400. Thus, the CBR data of the TDM transmission line 100 is sent to the common bus 400.

In the transmission control of CBR data, time T = 1
And the SAR function unit 4 receives the CBR control signal 500 and the CBR-W
The CBR data is transmitted to the common bus 400 based on the R signal 514 and the frame signal 302. The common bus interface unit 16 recognizes the reception of the CBR data, and writes the CBR data into the buffer C13. And C at time T = 2
The BR data is written to the buffer D14. Buffer C1
3 and writing to the buffer D14 are performed via the bus 161. Here, the bus 161 is a bus having an address bus, a data bus, and a write control signal. That is, if the frame signal 302 is “1”, the buffer C
13 is written into the buffer D14 if the frame signal 302 is "0". These operations are performed continuously.

The TDM terminating unit 17 receives the frame signal 302
Is "0", the buffer C13 is read, and when the frame signal 302 is "1", the buffer D14 is read and transmitted to the TDM transmission line 101.

(1-2) CBR data cell deceleration operation of the SAR function unit 4 (1-2-1) Reception operation from the common bus 400 C sent from the CBR buffer unit 1 to the common bus 400
The BR data is sent to the CBR celling / decellulating unit 42 via the common bus interface unit 41. The common bus interface unit 41 receives the CBR control signal 500 and the CBR-
Recognizing the reception of CBR data based on the RD signal 513,
After receiving the BR data, the CBR
Distribute BR data.

The CBR cell conversion unit 42 assembles CBR cells in the CBR cell buffer unit 45, and sends the CBR cells to the cell demultiplexing unit 44 after the completion of the assembly. The cell demultiplexing unit 44 sends the CBR cell to the ATM transmission line 401.

Regarding the assembly and disassembly of the CBR cell, see, for example, ITU-TI. 363. Also C
In the BR cell conversion, only data in which CBR data is valid (for a telephone, a connection is established and a call is being made) is converted to a cell. This cell forming method is known.

(1-2-2) Transmission operation to the common bus 400 The cell demultiplexing unit 44 sends the SAR
Header filtering information is set via the control signal 505, and the received cells on the ATM transmission path 401 are sorted. The setting information is, for example, V of the header information of the cell.
If the C number is VC = 01, the cell is a CBR cell and VC = 02
If the cell is a VBR cell, the cell is sent to the CBR cell decelerating unit 42 when the cell of VC = 01 is received, and the VBR cell decelerating unit is received if the cell of VC = 02 is received. An operation for transmitting a cell to the P.43 is performed. Then, the CBR cell conversion / decellulation unit 42 receives the CBR cell and sends a CBR reception request 502 to the control unit 5 indicating that the access to the common bus 400 is to be activated.

Control unit 5 receiving CBR reception request 502
Sets the CBR-WR signal 514 to "1" to activate DMA. Times T = 1 and T2 in FIG. 6 indicate this state. When the CBR control signal 500 is "1" and valid,
The R-WR signal 514 is "1".

Conversely, when there is no CBR reception request 502, the CBR-WR signal 514 is "0" (time T = 3), whereby the buffers C13 and D14 of the CBR buffer unit 1 Access and TD
The CBR data transfer of the M terminating unit 17 is temporarily stopped. The TDM termination unit 17 is stopped after the transmission of the CBR data in the buffers C13 and D14 is completed. This stop control is performed from the common bus interface unit 16 to the TDM transmission control unit 15 and the TDM termination unit 17 via a stop control signal 150.

The CBR cell buffer unit 45 also has a function of temporarily storing data for receiving a very large amount of traffic from the ATM transmission line 401 and controlling the use of the common bus 400.

(2) Packet bus 200 and ATM transmission line 4
01 (2-1) VBR buffer unit 2, control unit 5, packet bus 2
The bus 225 connects the packet bus terminating unit 21 of the VBR buffer unit 2 to the memory unit 22, and the bus 235 connects the memory unit 22 to the common bus interface unit 23. The bus 235 has an address bus, a data bus, and a control signal. It is. Further, the address management (storage management of VBR data) of the memory unit 22 is performed by the control unit 5 using the VBR buffer unit control signal 510. The VBR buffer control signal 510 is a bus having an address bus, a data bus, and a control signal.

VBR control signal 5 output from control unit 5
01 is “0” when the CBR control signal 500 is valid = 1 as shown in the time chart of FIG.
When the BR control signal 500 is invalid = 0, control is performed so as to be “1”.

As described above, the effective time of the CBR control signal 500 varies depending on the band used in the TDM transmission line, and similarly, the VBR control signal 501 varies according to the time width of the CBR control signal.

The packet bus 200 is a bus composed of an address bus, a data bus, and control signals or a high-speed packet transmission path.

(2-2) Operation of VBR buffer function unit 2
Access Operation of Common Bus 400 (2-2-1) Access from Packet Bus 200 to Common Bus 400 VBR data received from packet bus 200 is terminated at packet bus terminating unit 21 and temporarily stored in memory unit 22. Stored. The common bus interface unit 23
Based on a VBR control signal 501, a VBR read signal (hereinafter, referred to as “VBR-RD signal”) 515, and a VBR write signal (hereinafter, referred to as “VBR-WR signal”) 516, VBR data in the memory unit 22 is read. Actually, as described above, DMA transfer is activated and VBR data is read. As shown in the time chart of FIG.
When the BR control signal 501 is “1” and the VBR-RD signal 515 is “1”, the memory unit 22 can be accessed. As a result, the VBR data is transmitted to the common bus 40.
Sent to 0.

(2-2-2) Access from the Common Bus 400 to the Packet Bus 200 The VBR data sent from the SAR function unit 4 is
The control signal 501 is “1” and the VBR-WR signal 51
Processed when 6 is "1". The common bus interface unit 23 writes VBR data in the memory unit 22 based on these signals and the common bus 400. VBR-W
When the R signal 516 is invalid, the common bus interface unit 23 sends out a prohibition signal 250 for prohibiting access to the memory unit 22. Upon receiving the prohibition signal 250, the packet bus terminating unit 21 stops transmitting after transmitting the packet in the memory unit 22 to the packet bus 200.

(2-3) Common bus 400 and ATM transmission line 40
(1) Access operation (2-3-1) Access from common bus 400 to ATM transmission line 401 The common bus interface unit 41 of the SAR function unit 4
D based on the BR control signal 501 and the VBR-RD signal 515
The MA is started, the VBR data is read from the VBR buffer unit 2, and is sent to the VBR celling / decellulating unit 43. The VBR data is converted into a VB
It is assembled into R cells and sent to the cell demultiplexing unit 44.
Thereafter, the data is transmitted to the ATM transmission path 401. The assembly of the VBR cell is performed, for example, according to ITU-TI. 363.

(2-3-2) Access to Common Bus 400 from ATM Transmission Line 401
When a cell is received, filtering of the ATM cell is performed based on preset VC information. And VBR
When the cell is received, the VBR cell is sent to the VBR celling / decellulating unit 43.

The VBR celling decelerating unit 43 sends the VBR cell to the temporary VBR cell buffer unit 46, and then sends the VB
A process for converting the R cell into VBR data is performed. The disassembly of VBR cells is described, for example, in ITU-TI. 363. When sending a VBR cell to the common bus 400,
A BR reception request signal 503 is sent to the control unit 5.

Upon receiving the VBR reception request signal 503, the control unit 5 generates a VBR control signal 501 and a VBR-WR signal 51.
6 to control the DMA activation to the common bus 400. As shown in the time chart of FIG.
Shows the state. Also, the VBR reception request signal 5
When 03 does not occur, the VBR-WR signal 516 is not generated.

With the above operation, the VBR cell on the ATM transmission line 401 can be transmitted to the common bus 400. In addition,
The reason why the VBR cells are temporarily stored is to cope with the traffic of the ATM network and to adjust the bus use time of the common bus 400.

[0059]

As described above, the cell assembling / disassembling apparatus of the present invention operates the CBR cell and the VBR cell alternately on the basis of the synchronizing signal. It is possible to simplify the control that has complicated the bandwidth control and the buffer management of the VBR cell in order to secure the priority. Specifically, the buffer capacity of the multiplexing unit can be reduced and the multiplexing unit can be simplified.

The CBR cell buffer unit and the VBR
By providing the cell buffer unit, it is possible to cope with reception of an extremely large amount of traffic from the ATM transmission line and control of use of a common bus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a cell assembling / disassembling apparatus of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a cellularization function unit A1.

FIG. 3 shows a CBR buffer unit 1 and a VBR buffer unit 2
FIG. 3 is a block diagram illustrating a configuration example of FIG.

FIG. 4 is a block diagram illustrating a configuration example of a SAR function unit 4;

FIG. 5 is a block diagram illustrating a configuration example of a synchronization signal transmitting unit 3;

FIG. 6 is a timing chart illustrating the operation of the example.

FIG. 7 is a block diagram showing a configuration example of a conventional cell assembling / disassembling apparatus.

[Explanation of symbols]

 A1 Celling function unit 1 CBR buffer unit 2 VBR buffer unit 3 Synchronous signal sending unit 4 SAR function unit 5 Control unit 6 Clock extraction unit 10 TDM reception control unit 11 Buffer A 12 Buffer B 13 Buffer C 14 Buffer D 15 TDM transmission control Unit 16 common bus interface unit 17 TDM terminal unit 21 packet bus terminal unit 22 memory unit 23 common bus interface unit 31 PLL 32 divider circuit 33 counter circuit 41 common bus interface unit 42 CBR cell-forming decellularizing unit 43 VBR cell-forming decellularizing Unit 44 cell demultiplexing unit 45 CBR cell buffer unit 46 VBR cell buffer unit

Claims (3)

[Claims] A clock extraction unit for extracting a network clock synchronized with an ATM network; a synchronization signal transmitting unit for outputting a synchronization signal having a constant period and a frame signal indicating the period number based on the network clock; Assemble and disassemble between CBR data transmitted and received on the transmission line and CBR cells transmitted and received on the ATM transmission line, and assemble between VBR data transmitted and received on the packet bus and VBR cells transmitted and received on the ATM transmission line. A SAR function unit for performing disassembly, based on the synchronization signal and the frame signal, controlling the assembling and disassembly of the CBR data and the CBR cell when inputting and outputting the CBR data; A cell assembling / disassembling apparatus comprising: data and a cell function unit for controlling the assembling / disassembling of the VBR cell. 2. The cell conversion function unit includes: a CBR buffer unit for temporarily buffering CBR data transmitted and received on a TDM transmission line; a VBR buffer unit for temporarily buffering VBR data transmitted and received on a packet bus; The CB buffered in the buffer unit
Assembling and disassembling between R data and CBR cells transmitted and received on the ATM transmission line, and assembling and disassembling between the VBR data buffered in the VBR buffer unit and VBR cells transmitted and received on the ATM transmission line. Based on the SAR function unit and the synchronization signal and the frame signal, when inputting and outputting the CBR data, the SAR function unit and the CBR buffer unit are controlled to assemble and disassemble the CBR cell. 2. The cell assembling / disassembling apparatus according to claim 1, further comprising a controller configured to control the SAR function unit and the VBR buffer unit to assemble and disassemble the VBR cell. 3. The cell-forming function unit includes a CBR cell buffer unit for buffering CBR cells and a VBR cell buffer unit for buffering VBR cells. Cell assembly and disassembly equipment.