JPH1174383A - Nonvolatile semiconductor memory device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cause more easily electric field concentration at a tip end of a projection part and cause more frequency a tunneling current, by a method wherein a projection matter formed outside an upper part of a floating gate is formed so as to be enclosed with a control gate. SOLUTION: In order to form a projection part 23 so as to be exposed, a second gate oxide film and a control gate 9 are formed so as to cover the projection part 23. In other words, this leads to a state that the projection part 23 is enclosed with the second gate oxide film and the control gate 9. As the result, a distance between the projection part 23 of the floating gate and the control gate is made closer, a tip end of the projection part 23 is made acute, an interval of electric force rays caused in the control gate 9 from a tip end of the projection part 23 is narrowed, and electric field concentration is easy to occur. Thus, at a time of erase operations, if a source 11 is set 0 V and 15 V is applied to the control gate 9, a tunnel current is easy to occur in larger electric field concentration, whereby stabler erase operations are enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having improved erasing characteristics of retained information and a method of manufacturing the same.

[0002]

2. Description of the Related Art EEPRO which is a nonvolatile semiconductor memory
In the M or flash memory, a stack type, a split gate type, or the like is generally adopted. FIG. 11 shows a memory structure of the split gate type flash memory. As shown in FIG. 11, there is known a split gate type flash memory in which a control gate 9 is formed extending from an upper portion to a side portion of a floating gate 8 with an insulating film 10 interposed therebetween. This split gate flash memory is formed by a manufacturing method described below, and the manufacturing method will be described with reference to FIGS.

First, a first gate oxide film 2 having a thickness of about 100 ° is formed on a semiconductor substrate 1 by thermal oxidation, and a silicon film 3 having a thickness of about 1500 ° is formed by, eg, CVD. Although the silicon film 3 can be applied to a single crystal silicon film, a silicon film will be described here. Further, an oxidation resistant film (silicon nitride film) 4 having a thickness of about 500 ° is formed on the polysilicon film 3. An opening of about 0.5 to 0.7 μm is formed in the silicon nitride film 4 through a not-shown photoresist by a well-known patterning technique. By forming the opening, the polysilicon film at the portion where the LOCOS oxide film is to be formed is exposed (see FIG. 8).

Next, using the silicon nitride film 4 as a mask,
The polysilicon film 3 exposed in the opening 5 is oxidized to
A COS oxide film 6 is formed. The thickness of the LOCOS oxide film 6 is about 1500 ° at the central portion where the LOCOS oxide film 6 is maximum, and becomes thinner toward the outer peripheral portion. In this outer part, LOCO
The S oxide film 6 enters the bird's beak on the lower surface while lifting the silicon nitride film 4. Therefore, the thickness around the LOCOS oxide film 6 is reduced (see FIG. 9).

Then, the silicon nitride film 4 is etched and removed. Next, etching is performed with buffered hydrofluoric acid (for example, HF: H2O: NH4F = 1: 40: 20), and the upper surface of the LOCOS oxide film 6 is formed with a thickness of about 100 [deg.]-.
The exposed polysilicon film 6 is removed by anisotropic etching using the exposed LOCOS oxide film 6 as a mask. Thus, a floating gate 8 as shown in FIG. 10 is obtained. The LOCOS oxide film processed as described above is given a different symbol “7” (see FIG. 10).

Then, the floating gate 7 is made of hydrofluoric acid.
After light etching of the first gate oxide film other than immediately below, a silicon oxide film is formed on the entire surface by, for example, CVD, and the second gate insulating film 10 is formed. Finally, 1
500 ° doped polysilicon film, 1500 ° W
Six films are sequentially formed, and the control gate 9 is formed so as to extend from the upper part to the side part of the floating gate 8 via the second gate insulating film 10. Then
Using the floating gate 8 and the control gate 9 as a mask, an impurity is implanted into the semiconductor substrate to form a source region 11, and then another impurity is implanted again to form a drain region. A memory is formed. By generating the flash memory as described above, the tip of the floating gate 8 protrudes in the region surrounded by the dotted line in FIG.

Next, the principle of erasing and writing of the memory cell shown in FIG. 11 will be briefly described. In the flash memory of FIG. 11, the transistor of a memory cell to be written (hereinafter, referred to as a selected cell) is turned on, and a program is written by injecting electrons into the floating gate 8. In the region surrounded by the dotted line in FIG. 11, the polysilicon film 3 on the upper surface of the floating gate 8 is oxidized, and the LOCOS
By forming the oxide film 7, the projection 14 was formed at the tip of the bird's beak. When erasing information stored in the floating gate 8, the source 11 is grounded,
When a voltage of, for example, 15 V is applied to the control gate 9, an electric field concentration is generated in the protrusion 14, and electrons are drawn from the floating gate 8 to the control gate 9 by utilizing the electric field concentration to perform erasing.

[0008]

As described above, the formation of the projections 14 on the upper outer side of the floating gate 8 causes the electric field to be concentrated, thereby facilitating the flow of the tunneling current from the floating gate 8 to the control gate 9. Was. However, the flow of the tunneling current is insufficient with the shape of the projection 14 formed by the conventional manufacturing method. That is, when the projection 14 is manufactured by the conventional method, the width of the floating gate 8 of the projection 14 becomes narrower than that of the LOCOS oxide film 7 as shown in FIG.
Since the COS oxide film 7 is interposed, a certain distance is formed between the protrusion 14 and the control gate 9. Since the electric field strength is inversely proportional to the distance between the electrodes, the electric field concentration between the floating gate 8 and the control gate did not sufficiently occur, and the tunneling current was not sufficiently generated.

SUMMARY OF THE INVENTION It is an object of the present invention to stably perform an erasing operation by further causing electric field concentration and generating a tunneling current.

[0010]

The present invention is characterized in that a projection formed outside the upper part of the floating gate is formed so as to be surrounded by the control gate.
After the LOCOS oxide film is formed, the first oxide film is etched using the LOCOS oxide film as a mask to form a floating gate, and the LOCOS oxide film is etched so that the shape of the LOCOS oxide film is smaller than the shape of the floating gate. It is characterized by the following.

According to the present invention, since the LOCOS oxide film is formed to be smaller than the floating gate, the projection on the upper outer side of the floating gate is formed so as to be surrounded by the control gate. Electric field concentration is more likely to occur between the object and the control gate.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described. The steps from the step of forming the first gate oxide film 2 on the semiconductor substrate 1 of FIG. 8 to the step of etching the polysilicon film 3 according to the shape of the floating gate expected as shown in FIG. Since this is a process, the description is omitted.

After the step of forming the floating gate 8 by etching the polysilicon oxide film 3 using the LOCOS oxide film 7 formed by etching as shown in FIG. 10 as a mask, hydrofluoric acid (HF: H 2 O) Isotropically etched on the entire surface, and the LOCO
At the same time as the S oxide film 7 is shaved, the first gate oxide film 2 and the first
Of the gate oxide film 2 of FIG. By this etching, the shape of the LOCOS oxide film 7 becomes smaller than the shape of the floating gate 8, as shown in FIG. Note that the floating gate, the projection, and the LOCOS oxide film that have been cut as described above are different from the conventional shape.
This is referred to as an S oxide film 17 (see FIG. 1). Next, a silicon oxide film is formed on the entire surface by, for example, CVD, and the second gate insulating film 10 is formed.
reference).

Subsequently, a silicon nitride film is formed by, for example, CVD, and the formed silicon nitride film is anisotropically etched. The second anisotropic etching is performed on the upper surfaces of the floating gate 15 and the LOCOS oxide film 17.
Is performed such that the gate insulating film 18 and the second gate insulating film 10 on the silicon substrate 1 are exposed. By this anisotropic etching, a spacer 19 is formed on the side of the floating gate 15 (see FIG. 3).

After the formation of the spacer 19, the control gate 9 is formed so as to extend from the upper part to the side part of the floating gate 15 via the second gate insulating film 10. Further, using the floating gate 8 and the control gate 9 as a mask, impurities are implanted into the semiconductor substrate to form a source region 11 and a drain region. A split gate flash memory as shown in FIG. 4 is formed.

In the manufacturing method of the present invention, since the projection 16 is formed so as to be exposed, the second gate oxide film 18 and the control gate 9 are formed so as to cover the projection 16. That is, the second portion is formed so as to surround the protrusion of the protrusion 16.
The gate oxide film 18 and the control gate 9 are formed. As a result, the distance between the protrusion of the floating gate 15 and the control gate 9 becomes shorter and the protrusion of the protrusion 16 becomes sharper than in the conventional FIG.
The distance between the lines of electric force generated at the control gate 9 from the tip of the protruding portion 16 is reduced, and the electric field concentration is more likely to occur. Therefore, when 0 V is applied to the source and 15 V is applied to the control gate 9 at the time of the erase operation, a tunnel current is easily generated due to a larger electric field concentration. Therefore, electrons can be easily extracted from the floating gate 15 to the control gate 9, and a more stable erase operation can be performed.

Further, by forming the spacers 19 on the side surfaces of the floating gate 15, a malfunction in which electrons move from the control gate 8 to the floating gate 9, that is, a reverse tunneling phenomenon can be prevented. That is, in FIG. 2, in the portion where the first gate insulating film 2 is shaved below the floating gate 15 (the portion surrounded by the dotted line), the second gate insulating film 18 is formed.
Are formed. If the control gate is formed directly on this, a projection with a sharp tip is generated in a part of the control gate, and an electric field concentration occurs in the projection, and electrons are transferred from the projection to the floating gate 8. May move. However, in the first embodiment, by forming the spacer, the indented portion in the dotted line in FIG. 2 is filled with the spacer. Therefore, even when the control gate is formed, no projection is generated inside the control gate 9, so that no electric field concentration occurs, and the movement of electrons from the control gate to the floating gate is prevented.

Next, a second embodiment of the present invention will be described. In the same manner as in the first embodiment, the process of forming the first gate oxide film 2 on the semiconductor substrate 1 will be described with reference to FIG.
Since the steps up to the step of etching the polysilicon film 3 according to the expected shape of the floating gate as described above are the same as the conventional steps, the description is omitted. LOCOS oxide film 7 formed by etching as shown in FIG.
After the step of etching the polysilicon oxide film 3 to form the floating gate 8 using the mask as a mask, the exposed first gate insulating film 2 and the exposed LOCOS oxide film 7 are anisotropically etched. First anisotropic etching
Is removed, and the LOCOS oxide film 7 is removed so that its width is smaller than the width of the floating gate 8. In addition, the floating gate shaved as described above, its protruding portion and LO
Since the COS oxide film is different from the conventional shape, it is referred to as a floating gate 20, a protrusion 21, and a LOCOS oxide film 22 (refer to FIG. 5).

Subsequently, hydrofluoric acid (for example, HF: H 2 O =
1:25), the first gate insulating film 2 other than immediately below the floating gate 7 is etched to remove damage caused by the anisotropic etching in the previous step.
A silicon oxide film is formed on the entire surface by the VD method, and a second gate insulating film 23 is formed. Finally, a 1500 ° doped polysilicon film and a 1500 ° WSix film are sequentially formed (see FIG. 6).

Next, after the formation of the second gate insulating film 23, the control gate 9 is formed so as to extend from the upper portion to the side portion of the floating gate 8 via the second gate insulating film 23. Further, using the floating gate 20 and the control gate 9 as a mask, impurities are implanted into the semiconductor substrate to form a source region 11 and a drain region, thereby forming a split gate flash memory as shown in FIG.

Also in the second embodiment, since the projection 21 is formed so as to be exposed, the second gate oxide film 2 is formed.
3 and the control gate 9 are formed so as to surround and cover the protrusion 21. As a result, the protrusions 2 can be formed more than before.
Since the electric field concentration is likely to occur at the tip of 1, the tunnel current from the floating gate 20 to the control gate 9 is easily generated. Therefore, electrons can be easily extracted from the floating gate 20 to the control gate, and a more stable erase operation can be performed.

In the second embodiment, the LOCOS oxide film 2
In the step of shaving the first gate insulating film 2 under the floating gate 20 for anisotropic etching,
Is not etched. Therefore, the second gate insulating film 18 does not enter the lower part of the floating gate 15 as shown in FIG. As a result, even if the control gate 9 is formed directly on the second gate insulating film 20, electric field concentration occurs and the reverse tunneling phenomenon can be suppressed. Therefore, the formation of the spacer can be omitted. In this case, the step of forming the spacer can be omitted, and the process can be simplified.

[0023]

According to the present invention, the LOCOS oxide film is formed so as to be smaller than the floating gate, so that the upper outer projection of the floating gate enters the control gate and is surrounded by the control gate. Electric field concentration is more likely to occur at the tip of the protrusion. Therefore, a tunneling current is more easily generated, and electrons are more easily extracted from the floating gate to the control gate. Therefore, the erasing operation can be stably performed, and the erasing characteristics can be improved. Further, since the electric field concentration is more likely to occur, the voltage applied to the control gate during erasing can be reduced, and the withstand voltage characteristics of the semiconductor memory device can be improved.

Further, since the spacer is formed on the side of the floating gate, the reverse tunneling phenomenon can be prevented. Further, by simply introducing a step of making the LOCOS oxide film smaller than the floating gate, the projection can be easily formed so as to enter the control gate, and the above-mentioned effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment.

FIG. 2 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment;

FIG. 3 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 4 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 5 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 6 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 7 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 8 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 9 is a sectional view illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 10 is a sectional view illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 11 is a cross-sectional view illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

Claims (7)

[Claims] A floating gate formed of a silicon film formed on a gate insulating film on a semiconductor substrate of one conductivity type; and a LOC formed on the floating gate.
An OS oxide film, a control gate overlapping part of the floating gate and extending downward, and formed on the semiconductor substrate so as to overlap an end of the control gate and an end of the floating gate. A nonvolatile semiconductor memory device having a diffusion region of a reverse conductivity type, wherein a protrusion formed on an upper outer side of the floating gate is formed so as to be surrounded by the control gate. . 2. The nonvolatile semiconductor memory device according to claim 1, wherein a spacer is formed on a side surface of said control gate. 3. The floating gate according to claim 1, wherein said LOCOS film is smaller in size than said floating gate.
Or the nonvolatile semiconductor memory device according to 2. 4. A step of forming a gate insulating film on a semiconductor substrate of one conductivity type; a step of forming a first silicon film on the gate insulating film; and the first silicon corresponding to a predetermined floating gate Forming an oxidation-resistant film with the film exposed; and oxidizing the first silicon film through the oxidation-resistant film to reduce
Forming an OCOS oxide film; etching the first silicon film using the LOCOS oxide film as a mask to form a floating gate; and making the shape of the LOCOS oxide film smaller than the shape of the floating gate An etching step, a step of forming a second gate insulating film on the entire surface, and a step of forming a control gate that extends downward by overlapping with the floating gate via the second gate insulating film; Forming the semiconductor substrate diffusion region so as to overlap an end of the control gate and an end of the floating gate. 5. The method according to claim 4, further comprising a step of forming a spacer after forming the second gate insulating film. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein said etching step performs anisotropic etching. 7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein said etching step is isotropically etching.