JPH117334A - Computer system, device and method for controlling operation frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain power management with excellent balance between usability and power saving by increasing the operation frequency of CPU when the prescribed action of a device in a computer system, which occurs without an interval being more than the first prescribed time, is continued for more than the second prescribed time. SOLUTION: CPU 1 is provided with few data to be processed in a normal state so that a proportion for asserting an STPCLK# signal 31 is increased in a support circuit 2(7) in order to save power. The STPCLK# signal 31 is inputted to a control circuit 13. The control circuit 13 monitors the bus cycle of a PCI bus 5 and a DASP# signal 35 which is outputted by an HDD controller 15. When it becomes clear that an event to be executed correspondence occurs by the result of the monitoring, an STPCLK2# signal 33 obtained by correcting the STPCLK# signal 31 from the support circuit 2(7) is inputted to CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to computer system power management, and more particularly, to CPU clock throttling.
ttling) using CPU power management.

[0002]

2. Description of the Related Art CPU clock throttling is described in U.S. Pat. No. 5,546,568.
A first time interval at which the CPU operates at a predetermined frequency and a second time interval at which the CPU does not operate at all are provided alternately, and the ratio of the sum of the two time intervals to the first time interval is determined by the predetermined frequency , The actual operating frequency of the CPU is determined. For example, if the predetermined frequency is 1
At 00 MHz, if the first time interval is 1 and the second time interval is 7, the actual operating frequency is 12.5 MHz
z. Such CPU clock throttling technology is based on Intel's Pentium CPU.
It is actually used in processors (trademarks of Intel Corporation) and the like.

On the other hand, in power management in software, APM (Advanced Power Management)
That is used. The APM executes code to handle power events by using a special processor mode called the system management mode. The APM defines a normal state, a standby state, a suspend state, and an off state, and transitions to an appropriate state when a predetermined event occurs. The APM driver executes processing related to the state transition and system maintenance related to the state transition. For more information, see Advanced Power Management (APM) BIOS
Interface Specification Revision1.2, Feb. 1996, I
See ntel Corporation, Microsoft Corporation. Even in such APM-compliant software, the CPU is often occupied for a certain period of time regardless of whether there is any work to be actually processed. For example, APM
Windows95 (a trademark of Microsoft Corporation) compliant with Microsoft
Even with such an operating system, the device driver of the hard disk drive occupies the CPU during the waiting time. Therefore, it cannot be said that effective power management is performed only by APM.

Japanese Patent Application Laid-Open No. 3-296119 discloses a detecting means for detecting an access of an input / output device by a central processing unit, a measuring means for measuring a frequency or a cycle of the access,
There is disclosed an apparatus having a switching means for switching at least one of a central processing unit and an accessed input / output device from an operation state to a low power consumption state in accordance with a measurement result of the measurement means. In this embodiment, the number of times the software accesses the keyboard buffer within a predetermined time is counted, and the CPU is stopped when the number reaches a certain number. A case is described in which it is detected whether or not access has been made, and if access to the VRAM has not been made within a certain period of time after the access has been made, the display controller is stopped, the display is turned off, and a low power consumption state is set.

[0005] Japanese Patent Application Laid-Open No. 2-243412 discloses a communication device having a communication means, which is usually mounted internally for low power consumption.
This is a low power consumption portable information device that stops the PU clock and oscillates only when operation is necessary. It has a DMA function and a function to determine the start and end of a transfer block on the circuit, Discloses that the clock of the CPU is stopped to reduce power consumption.

Japanese Patent Application Laid-Open No. 4-238517 has a power control unit for turning on and off power to peripheral hardware. The power control unit includes an input / output interval to peripheral hardware and an input / output per unit time. It discloses a control method for monitoring the number and controlling the power on / off of peripheral hardware so as to minimize the power consumption of the battery based on the monitoring result. In this embodiment, the power control means sets the minimum processing time with the most power-saving effect in the processing from power-on, input / output, and power-off to the minimum non-communication time for power-off, as a unit time for peripheral hardware. Monitor the number of I / Os per unit time.If the number of I / Os per unit time is smaller than the value of the immediately preceding unit time, increase the non-communication monitoring time. It describes that, after a certain input / output, if the continuous input / output is not performed even after the elapse of the non-communication monitoring time, the peripheral hardware 6 is powered off.

Japanese Patent Application Laid-Open No. 4-195316 discloses a CPU.
By monitoring the signal between the device and the device, the access detection circuit detects that the device is operating, that is, that the device has been accessed from the CPU, and provides an instruction signal to the control circuit based on the detection. It is disclosed that power supply or clock supply to the device is started. In addition, the access detection circuit detects that the CPU
Alternatively, it is also disclosed that a signal is output for each specific area by detecting that a plurality of specific areas have been read.

Japanese Patent Application Laid-Open No. Hei 5-11897 discloses a technique in which the clock frequency is increased for a certain period only when an I / O access that requires an operation with a high-speed clock occurs.

Japanese Patent Application Laid-Open No. 8-83133 discloses that, when a CPU accesses a relatively low-speed I / O unit such as a magneto-optical disk device, an I / O controller is provided with an I / O controller.
It discloses that an O access request (IORQ) is output, and the I / O controller outputs a WAIT signal for instructing the CPU to wait for a predetermined period after receiving the IORQ. This predetermined period is set based on the response time from the I / O unit.

Investigation of a commercially available product reveals that a method of increasing the substantial operating frequency of the CPU for a certain period of time of 4 ms to 8 ms after a command is issued to the hard disk for several seconds or an event such as an interrupt from the hard disk is generated. Was. As a result of measuring and examining the actual power consumption, this method was used in Windows
The following issues became apparent when running on s95 (a trademark of Microsoft Corporation). (1) While the CPU waits for a response from the hard disk, the CPU remains accelerated, and during this period, several percent of the entire power consumption is wasted. (2) In Windows 95, a time slice of 13.7 ms is used for switching timing of a thread in which a hardware timer periodically generates an interrupt to a scheduler of an operating system. Therefore, in the case of a device that employs a method of operating the CPU at high speed for 8 ms for each interrupt, 13.
Since the 8 ms CPU is operated at a high speed every 7 ms, the CPU operates at a high speed for most of the time.

Although a method for solving only such a problem may be able to be solved by the above-mentioned prior art, there is no method which provides a balance with usability.

[0012]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of power management that balances usability and power saving.

[0013]

In a first aspect of the SUMMARY OF THE INVENTION The present invention arises not placed between the predetermined time t ₁ or more, the predetermined activity of the device in the computer system, the predetermined time t
_{When two} or more are continued, the configuration is such that the substantial operating frequency of the central processing unit is increased. For example, the CPU clock throttling usually lowers the actual operating frequency of the CPU, and access to the frame buffer of the graphics device for image correction (or the CPU) occurs within 100 μs. (Indirect access to the graphics device and / or the frame buffer, or access to the graphics device) lasts 1 ms, so as to increase the substantial operating frequency of the CPU. In this way, if the screen modification is small and does not require much computational power of the CPU, access to the frame buffer for the purpose of image modification does not satisfy the above condition. CP
The U clock throttling keeps the effective operating frequency of the CPU low. Even in this case, the usability does not decrease and the power consumption does not increase. On the other hand, if a large amount of screen correction is being performed and access to the frame buffer for the purpose of image correction is continuously occurring, the CPU must be operated at a high speed and the processing result must be presented to the user promptly. Feel stress. Thus, the usability is prioritized over the power consumption, and the substantial operating frequency of the CPU is increased.

In such a case, after a predetermined activity of a device in the computer system, which occurs within a predetermined time t ₁ or more, and after a predetermined time t _{3 has} elapsed, a substantial operation of the central processing unit is performed. The frequency may be reduced.

In another aspect of the invention, after the access to the disk device, raise the substantial operating frequency of the central processing unit, then within the predetermined time t _4, the predetermined activity of the device other than the disk device when that occurs after the predetermined activity completed, after the predetermined time t ₃ has elapsed, it configured to reduce the substantial operating frequency of the central processing unit. After the access to a disk device such as a hard disk drive or a CD-ROM drive is completed, data which is usually processed by the CPU is often read into the memory, so that the substantial operating frequency of the CPU is increased. Thus after reading data from the disk apparatus, since in many cases to implement the processing related to the display device such as a graphics device to access image correction purposes into the frame buffer, the disk device access end after a predetermined time t ₄ within, when the activities of non-disk access occurs, to leave the activity raised a substantial operating frequency of the CPU until after the predetermined time t ₃ has elapsed after completion. In this way, it is possible to cope with necessary processing after disk access, so that usability is not reduced and the CPU is accessed during disk access.
Has been lowered by the CPU clock throttling, thereby saving power.

Further, within a predetermined time t _4, when the predetermined activity of the device other than the disk device does not occur, after the predetermined time t ₄ has elapsed, that the lower the substantial operating frequency of the central processing unit Can also be considered. This is because when processing that has a particular impact on the user does not occur, only data read from the disk device is processed at high speed, and the rest is to save power.

[0017] In another aspect of the invention described above, the processing is shown when the predetermined activity of the device other than the disk device occurs, the predetermined activity is not placed between the predetermined time t ₁ or more May occur as a device activity other than the disk device. This is the same as in the first embodiment of the invention. When there is not much processing such as screen rewriting, the substantial operating frequency of the CPU is increased after accessing the disk device. This is because there is a case where it is not necessary to take measures for the sake of example.

According to the first aspect of the present invention, for example, each time a device in a computer system performs a predetermined activity, a first counter which starts counting a first predetermined value from an initial state; A second counter that initializes when one counter has finished counting the first predetermined value, and counts a second predetermined value when the first counter has counted the first predetermined value; When the two counters have counted the second predetermined value, they may be constituted by a device or an apparatus including control means for commanding to increase the substantial operating frequency of the central processing unit.
The second counter can be replaced with, for example, the following counter. That is, when the first counter has finished counting the first predetermined value, initialization is performed, and after the first counter has finished counting the first predetermined value, the first counter is reset to an initial state by a predetermined activity of the device. This is a counter which starts counting the second predetermined value when the first counter starts counting from the initial state before the first counter finishes counting the first predetermined value after counting from.
In other words, when counting is started from the initial value while the first counter is not counting, and when the second counting is started from the initial value before the end of the counting, the second counting is started when the second counting is started. This is a counter which starts counting the value of.

Further, after the second counter has finished counting the second predetermined value, and in response to the first counter having finished counting the first predetermined value, the third predetermined value is calculated. It is conceivable to further comprise a third counter which starts counting, wherein the control means instructs to lower the substantial operating frequency of the central processing unit when the third counter has finished counting the third predetermined value. .

The first to third counters count
It may be down or count up. Also, access to a frame buffer for image correction of a graphics device has been described above as an example, but the present invention is not limited to this. For example, a device that performs compression / expansion processing of MPEG may be used for compression / expansion. A combination such as access to a device storing a processing target, a combination such as access to a device storing communication data of a communication device, and the like can be considered.

According to another aspect of the present invention, for example, in response to completion of access to a disk device, the fourth state is changed from the initial state to the fourth state.
A fourth counter for starting to count a predetermined value of the above, control means for instructing to increase the substantial operating frequency of the central processing unit in response to the end of the access to the disk device;
If a predetermined activity of a device other than a disk drive occurs before the counter has finished counting the fourth predetermined value,
In response to the end of the activity, a third
A third counter that counts a predetermined value of the control signal, wherein the control means instructs to lower the substantial operating frequency of the central processing unit in response to the third counter finishing counting the third predetermined value. It can also be configured.

Each time a device other than the disk device performs a predetermined activity, the first counter loads a first predetermined value and counts down the value, and the count of the first counter becomes zero. And a second counter that loads a second predetermined value when the count is not 0, and counts down when the count of the first counter is not 0.
The counter is configured to start counting in response to the count of the first counter becoming zero when the second counter becomes zero before the fourth counter finishes counting the fourth predetermined value. It is also conceivable to configure. This is an example of predetermined activity of the device within a predetermined time period t ₄ is also caused, when it can be associated with first raise substantial operating frequency of the CPU processing is not performed any more Action Corresponding.

In some cases, the count of the first counter becomes 0 within the predetermined time t ₄ , in which case the substantial operating frequency of the CPU can be increased during t ₄ . Although it is assumed that CPU clock throttling is used, the actual input frequency may be increased or decreased as long as the CPU can operate at a plurality of types of clock frequencies.

Although the configuration of the present invention has been described above, the aspect of the present invention is not limited to a device, an apparatus, or a computer system, but may be in the form of computer software or a storage medium storing the same. Is also feasible.

In general, there is software that requires a great deal of CPU power without accessing the hard disk or the screen at all, but such software is a current personal computer, especially Not a major piece of software on a notebook computer. Therefore, the present invention assumes a state in which such an application does not exist.

[0026]

FIG. 1 shows a configuration example of the present invention. C
PU1 is a control circuit 13 that performs control related to the present invention.
And the support circuit 1 (3). The control circuit 13, the support circuit 1 (3), and the support circuit 2
(7) and the graphics device 11
(Peripheral Component Interconnect) bus 5. The graphics device 11 is connected so as to access the frame buffer 9, and is also connected to an LCD (liquid crystal display) 19.
The control circuit 13 is connected to an HDD controller 15, and the HDD controller 15 is connected so as to control an HDD (hard disk drive) 17. The support circuit 2 (7) and the control circuit 13 are connected. For example, the CPU 1 executes the above-mentioned Pentiu
m, and the support circuit 1 (3) and the support circuit 2 (7) are semiconductor chips included in the 82430TX chip set of Intel Corporation. In particular, the support circuit 2 (7) corresponds to a chip called PIIX4. PC
The I bus 5 is an example, and other types of buses may be used. H
In this embodiment, the DD controller 15 uses IDE (Inte
(Ligent Drive Electronics) interface, but may have other interfaces. However, the period from when the Read / Write command is issued to the HDD controller 15 to when the final data transfer is completed is determined by the control circuit 13.
If the control circuit 13 outputs a signal that can be detected, the configuration of the control circuit 13 is simplified.

FIG. 1 shows a state in which the HDD 17 is connected to the HDD controller 15, but not only the HDD 17 but also a CD-ROM drive or an M-disk drive.
A disk device that is a large-capacity storage device such as an O drive may be connected. Further, not only one device but also two or more devices may be connected. Whether two or more devices can be connected depends on the capability of the HDD controller 15 (or the disk device controller).
The graphics device 11 executes a process for displaying data on a display device such as the LCD 19. Here, the LCD 19 is used, but a CRT display may be used. Further, the frame buffer 9 may be a part of a main memory (not shown) or may be provided separately.

The control circuit 13 is connected to the support circuit 2
Although shown in FIG. 1 as a separate device from (7), the control circuit 13 can be included in the support circuit 2 (7).

Next, the operation of the circuit of FIG. 1 will be described. The support circuit 2 (7) is a circuit that instructs to execute CPU clock throttling, and
The signal (31) is output. This STPCLK # signal (3
1) is a signal that does not operate the CPU during the assertion, but operates the CPU during the deassertion. For example, when the support circuit 2 (7) is the PIIX4 described above, if the TDP (Throttle Duty Programming) bit is set to 001b, the time during which the CPU operates and the time during which the CPU does not operate become 1: 7. Therefore, the throttle duty (Throttle Duty) becomes 12.5%. When 244 μs is defined as one unit, S is set for 30.5 μs.
The TPCLK # signal is deasserted and the CPU operates,
For the remaining 213.5 μs, the STPCLK # signal is asserted and the CPU is inactive.

In the normal state, since the CPU 1 has little data to process, the support circuit 2 (7)
The ratio of asserting the PCLK # signal is increased. This is because it saves power. This signal 31 is input to the control circuit 2. The control circuit 13 determines the bus cycle of the PCI bus 5 and the DAS output from the HDD controller 15.
The P # signal 35 is monitored. As a result of this monitoring, if it is determined that an event to be handled has occurred, an STPCLK2 # signal 33 obtained by modifying the STPCLK # signal 31 from the support circuit 2 (7) is input to the CPU. The meaning of the STPCLK2 # signal 33 is the same as that of the STPCLK # signal 31.

The support circuit 1 (3), the graphics device 11, the HDD controller 15, and the HD
D17 performs a normal operation. That is, the graphics device 11 performs data processing necessary for changing the display of the LCD 19 when necessary, and the HDD controller 15 accesses the HDD 17 when necessary. The description of the support circuit 1 (3) is omitted because it is not directly related to the present invention.

Next, the details of the control circuit 13 of FIG. 1 are shown in FIG. The detector 101 that monitors the PCI bus 5 has the first configuration.
It is connected to the counter 103 and the first state machine circuit 107. The first counter 103 is connected to the first state machine circuit 107. 1st state machine 1
07 is the second counter 105 and the second state machine 1
09. The second counter 105 is connected to the signal generator 115. This signal generator 115
, The STPCLK # signal 31 is input. In addition,
From the first state machine circuit 107 to the second counter 105
A signal line for inputting a signal to the second state machine circuit 109 to the second state machine circuit 109; a signal line for inputting a signal from the second counter 105 to the signal generator 115 to the second state machine circuit 109;
A signal line for inputting the output of the detector 101 to the second state machine 109 can be selected from these three, and may be all connected. The first and second state machine circuits are connected to the third counter 113. The third counter 113 is connected to the signal generator 115. H
The DASP # signal from the DD controller 15 is input to the fourth counter 111, and the fourth counter 111 is connected to the second state machine circuit 109. DAS
The P # signal is also input to the second state machine circuit 109.

The operation of FIG. 2 will be described. First, operations related to the first state machine circuit 107 will be mainly described. The detector 101 monitors the PCI bus 5 and, for example,
A state where the PU 1 is indirectly accessing the graphics device 11 and / or the frame buffer 9 is detected. For example, in the address phase of the bus cycle of the PCI bus 5, a memory range allocated to the graphics device (eg, 0800_0000 to 08
3F_FFFF) (eg, 0801_234)
If 5) is detected in AD [31: 0] (address / data bus), it is determined that the access is to the frame buffer 9. If graphics by CPU1
When the access to the device 11 and / or the frame buffer 9 is detected, the detector 101
And outputs a signal to the first state machine circuit 107.
The first counter 103 loads a predetermined first value and starts counting down. This first counter 1
The count value of 03 is output to the first state machine circuit 107. The first counter 103 includes a detector 101
Detects the access to the frame buffer 9 by the graphics device 11 and outputs a signal, and loads the first value and counts down.

The first state machine circuit 107 has a state as shown in FIG. 3 or FIG. 4 and performs a state transition. In FIG. 3, there are an initial state 501, a first_counting state 503, and a continuous_counting state 505. Initially, it starts from the initial state 501.
At this time, the second counter 105 is loaded with a predetermined second value, but does not count down.
First, a detection signal from the detector 101 is received (transition 5).
11) and the first state machine circuit 503
Transition to the ting state 503 is made. In this state, the first counter 103 counts down the first value. If the first counter 103 has counted down to count 0 in the first_counting state 503, the process returns to the initial state 501 (transition 5).
13). In this case, since the access to the graphics device 11 and / or the frame buffer 9 is not continuous, there is no need to increase the substantial operating frequency of the special CPU. If the detection signal is received again before the count of the first counter 103 reaches 0 in the first_counting state 503 (transition 515), the first state machine 107 transitions to the continuous_counting state 505. At the time of this transition 515, the countdown of the second counter 105 is started. First counter 103
Starts the countdown by loading the first value again as described above.

In the continuous_counting state 505, the detection signal is received unless the counts of the first and second counters are both 0 or the count of the first counter 103 is 0 and the count of the second counter 105 is not 0. (Transition 517).
This represents a state where the graphics device 11 and / or the frame buffer 9 are frequently accessed.
Therefore, the count of the second counter 105 counts down smoothly. On the other hand, when the count of the second counter 105 is not 0 but the count of the first counter 103 has become 0 (transition 521), the countdown of the second counter 105 is stopped, and the initial state 5
Return to 01. Since we return to the initial state 501, the second
The counter 105 is loaded with the second value to stop the countdown. This represents a state in which the graphics device 11 and / or the frame buffer 9 are not continuously accessed for a sufficiently long time (while the second value is being counted down), and in such a case, the substantial operation of the CPU is performed. There is no need to increase the frequency. In addition, for an event in which the counts of the first and second counters are both 0, the third counter 113 is loaded with a predetermined third value and instructed to start the countdown. Such a state may occur if the graphics device 11 and / or the frame buffer 9 has been accessed for a sufficiently long time (while counting down the second value),
Although the actual operating frequency of U was increased, the first counter 1
The fact that the count of zero has become zero means that the period in which this substantial operating frequency is raised may soon be over. Note that the count of the second counter 105 is input to the signal generator 115. If the count of the second counter 105 becomes 0, the signal generator 115 increases the substantial operating frequency of the CPU.
Deassert the STPCLK2 # signal.

The third counter 113 counts down the third value. Since the count of the third counter 113 is input to the signal generator 115, the signal generator 1
15 until the count becomes 0, STPCLK2 #
Is deasserted, and when the count reaches 0, STP
The CLK # signal is output as it is.

The above operation will be described with reference to the time charts of FIGS. FIG. 5A shows a time when the detector 101 detects an indirect access to the frame buffer and outputs a detection signal. When the detection signal is input to the first counter 103 again while the first counter 103 counts down the first value (period T ₁ ) after the first access, it is determined that the detection signal is continuous, and FIG. (B) becomes "high". Since during the last detection signal of the period T ₁ not input the detection signal, first
The count of the counter 103 becomes 0, and a signal (in this case, “low”) indicating the discontinuity of access appears in FIG. 5B. As described above, it is determined that continuous access is being performed in FIG.
In the continuous_counting state 505 in FIG.

In FIG. 5A, it is determined that the access is continuous in the periods A and B. However, in the period C, even if the state transits to the first_counting state 503 in FIG.
Since the count of the counter 103 becomes 0 without the first value being loaded again (transition 513), the process returns to the initial state 501 and is determined to be discontinuous.

Referring to FIG. 6, (a) shows STPCLK #
Represents a signal. # Means low active.
This (a) represents 1/8 CPU clock throttling, which activates the CPU when deasserted and deactivates the CPU when asserted. The invention of the present application is not limited to 1/8, and a throttling of another ratio may be used. In FIG. 6B, the co shown in FIG.
The period during which the state is in the utinuous_counting state 505 is expressed as “high”, and the other period is expressed as “low”. After being recognized as a continuous access as shown above,
When the second counter 105 starts counting down the second value and the count of the second counter 105 becomes 0, the signal generator 115 outputs the STPCLK2 # signal ((c) in FIG. 6).
Is deasserted (here, "high"). That is, the CPU is brought into the operating state. This prevents usability degradation. The second value is the time to count down to 0 is the period T _2. Then, the second counter 10
When the count of the first counter 103 becomes 0 after the count of 5 becomes 0, the third counter 113 starts counting down the third value (transition 519 in FIG. 3). The time until the third value is counted down to zero and the period T _3. As in (c) of FIG. 6, during the period T ₃ from the continuous access to be completed, CPU activates, then STPC
The LK # signal is output as it is, and operates with CPU clock throttling.

In FIG. 7, the signals represented by (a) and (b) are the same as in FIG. However, a period of continuous access as seen in (b) is shorter than T _2. Therefore, the second
By the time the counter 105 reaches the count 0, the count of the first counter 103 becomes 0 ((transition 521) in FIG. 3). In such a state, signal generator 115 outputs the STPCLK # signal as it is. This is because there is no need to extend the period during which the CPU operates.

The first state machine 107 may have a state as shown in FIG. 4 and perform a state transition. 3 and 4
Is whether or not the first_couting state 503 exists. In the case of FIG. 4, the counting of the second counter starts even if the detection signal is output once. However,
If the count of the first counter 103 immediately becomes 0, the state returns to the initial state at the transition 617, so that no particular problem occurs.
Other processes are the same, and the description is omitted.

The above is a description of the processing when the DASP # signal is not input. Next, processing when the DASP # signal is deasserted will be described. DASP
While the # signal is asserted, access to the disk device is being performed, so that the actual operating frequency of the CPU is not increased. When the DASP # signal is deasserted, the fourth counter 111 that has detected the DASP # signal loads a predetermined fourth value and starts counting down. On the other hand, the deassertion of the DASP # signal is also detected by the second state machine circuit 109. Hereinafter, the operation of the second state machine circuit 109 will be described with reference to the state transition diagram of FIG.

The second state machine circuit 109 has an initia
l state 701, couting state 703 and extensio
It has an n state 705 state. As described above, the second state machine circuit 109 detects the deassertion of the DASP # signal, and changes the state of the initial state 701 to the couting.
The state transits to the state 703 (transition 711). At this time, the second state machine circuit 109 supplies the signal generator 115 with ST
Outputs a signal instructing PCLK2 # to be deasserted. Here, at least the fourth counter 111
During the time period (period T ₄ ) for counting down the value of. If, later described action is not generated during the period T _4, if the count of the fourth counter 111 becomes 0, counting state 703
To the initial state 701 (transition 713). This means that since no specific activity has occurred after accessing the disk device, it is sufficient to increase the substantial operating frequency of the CPU by the amount of processing required for accessing the disk device.

If a specific action occurs while the fourth counter 111 is counting down, a transition is made to the extension state 705 (transition 71).
5). This specific action means that when a detection signal from the detector 101 is received, the detection signal is input to the first counter 103 twice consecutively, and the second counter 105
May be started, or the count of the second counter 105 may become zero.
In the example described below, a case where the second counter 105 starts counting down the second value will be described. Thus, when a specific action occurs during the period T ₄ is to extend the period of increasing the substantial operating frequency of the CPU. In this embodiment, the count of the first counter 103 becomes 0 (transition 717), until the period T ₃ has elapsed CP
Increase the effective operating frequency of U. That is, when the counter of the first counter 103 becomes 0, the process returns to the initial state 701. Then, it instructs the third counter 113 to count down the third value. Signal generator 115
Monitors the count of the third counter 113,
Stops deasserting the STPCLK2 # signal when it reaches 0,
It operates so as to transmit the STPCLK # signal to the CPU as it is.

Note that the initialization state 705
The transition to the al state 701 is not an event that the count of the first counter 103 has become zero as described above, but the count of the first counter 103 becomes zero and the value of the fourth counter 111 becomes zero. Sometimes, such a transition occurs, and even if the count of the first counter 103 becomes 0,
If the value of the fourth counter 111 is not 0, extension
It is also possible to stay in the state 705.

The operation described above will be examined with reference to a time chart (FIG. 9). FIG. 9A shows the STPCLK described above.
# Signal. (B) shows a DASP # signal, in which a disk access is present at first, but no disk access is made thereafter. At this time, the second state machine circuit 109 supplies the signal generator 115 with STPCLK
A signal instructing to deassert the 2 # signal is output (FIG. 9 (d)). (C) indicates the existence of the above-mentioned action, and here, when it is determined that the access to the graphics device 11 and / or the frame buffer 9 is continuous, “high” is set. Become. This action occurs after the DASP # signal is deasserted
Since occurred before the period T ₄ passes, the second state machine circuit 109 enters the extension state 705. Therefore, until the count of the first counter 103 becomes 0,
Deassert the STPCLK2 # signal. When the count of the first counter 103 becomes 0, the third counter 1
13 begins to count down the third value, asserting STPCLK2 # signal where the period T ₃ has elapsed.

If the action shown in FIG. 9C does not occur, the STPCLK2 # signal is deasserted until the count of the fourth counter 111 becomes zero, and when the count becomes zero, the second state machine circuit 109 generates a signal. Container 115
Output a de-assertion instruction to the signal generator 1
15 asserts the STPCLK2 # signal.

By performing the processing related to the second state machine circuit 109, while the DASP # signal is asserted, the substantial operating frequency of the CPU is not increased and D
Since the substantial operating frequency of the CPU is increased while the ASP # signal is deasserted, the peak of the power consumption due to the spin-up of the hard disk is the peak of the power consumption increased by increasing the substantial operating frequency of the CPU. It can be prevented from overlapping.

Although the control circuit 13 has been described above, this is merely an example and is not limited to the above description. In particular, the connection relationship between the first to fourth counters, the first and second state machine circuits, and the signal generator 115 shown in FIG. 2 is an example, and the state machines of the first and second state machine circuits (FIGS. In addition to FIGS. 4 and 8), the circuit can be modified into a circuit that can draw the time charts of FIGS. 5 to 7 and 9. The first and second state machine circuits can be formed into a single module, or can be integrated into the signal generator 115.

3 and 4, and FIG. 8, the STPC
Although the LK2 # signal is kept deasserted for a designated period, it is also possible to set a state in which the period of deassertion is longer than that of the STPCLK # signal. For example, while the STPCLK # signal is deasserted by 1/8, the STPCLK2 # signal in the designated period may be deasserted by 7/8.

Also, when the access to the graphics device 11 and / or the frame buffer 9 occurs after the deassertion of the DASP # signal, as described above, when each activity occurs in the reverse order, The processing in the first state machine circuit 107 may be prioritized, or another processing may be performed.

In the above embodiment, the detector 101 includes the graphics device 11 and / or the frame buffer 9.
However, it is also possible to detect the operation belonging to the group and output the detection signal by detecting the operation belonging to the group as one group. it can. Further, T _{1 to} T ₄ can be fixed or can be adaptively changed according to other conditions. If the detector 115 can identify a plurality of types of operations, it is possible to output different T _{1 to} T ₄ depending on the type of the detected operation. Also, an example has been described in which access is detected by monitoring the PCI bus 5, but any method of directly monitoring access from the graphics device 11 may be used.

In response to the interrupt of the data transfer request of the HDD 17 which frequently occurs while the DASP # signal is asserted, the substantial operating frequency of the CPU is increased for a short period of time of about 100 μs to improve the data transfer performance. Do not drop. Further, it is monitored whether or not the APM has entered the idle state, and the effective operating frequency is reduced immediately when the STPCLK # signal is asserted by the APM.

Although the above has been a detailed description of the hardware implementation, the present invention can also be implemented by software. For example, when there is a hierarchical structure in which the OS 803 exists under the applications A to D as shown in FIG. 10 and the BIOS 804 exists under the OS 803, a program for performing the same processing as the control circuit 13 in FIG. Provided in the OS 803;
However, if the OS 803 receives a screen rewrite request or a hard disk access request from the applications A to D, and the OS 803 matches the above-described conditions, B
CPU clock throttling can also be controlled via IOS 804. Note that application A
If the actions such as continuous screen rewriting are notified to the OS 803 in steps D to D, the processing required by the OS 803 can be reduced.

FIG. 10 is an example, the number of applications is arbitrary, and the control circuit 13 shown in FIG.
The processing program included in the
Which one of the S and the BIOS is provided and in what combination is provided is arbitrary including other conditions.

[0056]

[Effect] It is possible to provide a method of power management that balances usability and power saving.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a hardware configuration of the present invention.

FIG. 2 is a block diagram showing a configuration example of a control circuit 13 shown in FIG.

FIG. 3 is a diagram illustrating a state transition of a first state machine circuit 107 in FIG. 2;

FIG. 4 is a diagram illustrating a state transition of a first state machine circuit 109 in FIG. 2;

FIG. 5 is a time flowchart related to the first state machine circuit 107; (A) is a waveform diagram showing access to a frame buffer, and (b) is a waveform diagram showing detection of continuous access.

FIG. 6 is a time flowchart related to the first state machine circuit 107; (A) STPCLK # signal, (b) continuous access detection, (c) STPCL
FIG. 9 is a waveform chart showing a K2 # signal.

FIG. 7 is a time flowchart related to the first state machine circuit 107; (A) STPCLK # signal, (b) continuous access detection, (c) STPCL
FIG. 9 is a waveform chart showing a K2 # signal.

8 is a diagram illustrating a state transition of a second state machine circuit 109 in FIG.

FIG. 9 is a time flowchart related to the second state machine circuit 107; (A) is a waveform diagram showing an STPCLK # signal, (b) is a DASP # signal, (c) is a continuous access detection (detection of an action), and (d) is a waveform diagram showing an STPCLK2 # signal.

FIG. 10 is a diagram showing an example of an implementation in software.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 3 Support circuit 1 5 PCI bus 7 Support circuit 2 9 Frame buffer 11 Graphics device 13 Control circuit 15 HDD controller 17 HDD 19 LCD 31 STPCLK # signal 33 DAPS # signal 35 STPCLK2 # signal 101 Detector 103 First counter 105 second counter 107 first state machine 109 second state machine 111 fourth counter 113 third counter 115 signal generator

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuo Sekiya 1623-14 Shimotsuruma, Yamato-shi, Yamato Kanagawa, Japan

Claims (23)

[Claims] 1. A computer system having a central processing unit, generated without placing between a predetermined time t ₁ or more, predetermined activity devices in the computer system, the predetermined time t
A computer system for increasing the substantial operating frequency of the central processing unit when _two or more operations are continued. 2. A generated without placing between the predetermined time t ₁ or more, after a predetermined activity of the devices in the computer system has been completed, after the predetermined time t ₃ has elapsed, the substantial operation of the central processing unit The computer system of claim 1, wherein the frequency is reduced. 3. The computer system of claim 1, wherein said device is a graphics device and said predetermined activity is an access to a predetermined memory address. 4. A computer system having a disk device and a central processing unit, after the end access to the disk device, raise the substantial operating frequency of said central processing unit, thereafter within the predetermined time t _4, the If the predetermined activity of the device other than the disk device occurs, the computer system characterized in that after the predetermined activity completed, after the predetermined time t ₃ has elapsed, reducing the substantial operating frequency of said central processing unit. 5. A within the predetermined time t _4, when the predetermined activity of the device other than the disk device does not occur, after the predetermined time t ₄ has elapsed, reducing the substantial operating frequency of said central processing unit 5. The computer system according to claim 4, wherein: 6. A predetermined activity of the device other than the disk device occurs without placing between a predetermined time t ₁ or more, according to claim 4, characterized in that the activities of a device other than the disk device computer ·system. 7. The computer system according to claim 4, wherein the device other than the disk device is a graphic device, and the predetermined activity is an access to a predetermined memory address. 8. A device for controlling a substantial operating frequency of a central processing unit of a computer system, wherein each time a device in the computer system performs a predetermined activity, a first predetermined value is set from an initial state. A first counter to start counting, and initialization when the first counter has finished counting the first predetermined value, and when the first counter is counting the first predetermined value, A second counter for counting a second predetermined value, and control means for commanding to increase a substantial operating frequency of the central processing unit when the second counter has finished counting the second predetermined value, Including devices. 9. A device for controlling a substantial operating frequency of a central processing unit of a computer system, wherein each time a device in the computer system performs a predetermined activity, a first predetermined value is set from an initial state. A first counter to start counting, and, when the first counter has finished counting the first predetermined value, initialize the counter, and from a state in which the first counter has finished counting the first predetermined value, When the first counter starts counting from the initial state after the first counter starts counting from the initial state due to a predetermined activity of the device and before the first counter finishes counting the first predetermined value. A second counter that starts counting a second predetermined value; and a second counter that is used by the central processing unit when the second counter finishes counting the second predetermined value. Device and a control unit to order to raise the qualitative operating frequency. 10. After the second counter has finished counting the second predetermined value, and in response to the first counter having finished counting the first predetermined value, the third counter.
A third counter that starts counting a predetermined value of the third processing unit. When the third counter finishes counting the third predetermined value, the control unit decreases the substantial operating frequency of the central processing unit. 9. The method of claim 8, wherein the order is given.
Or the device according to 9. 11. The device according to claim 8, wherein the device in the computer system is a graphics device, and the predetermined activity is an access to a predetermined memory address. 12. A means for outputting a signal each time the first counter detects a predetermined activity of the device, and loading the first predetermined value in response to the signal, and counting the value. 10. The device according to claim 8 or 9, comprising: a down counter. 13. A device for controlling a substantial operating frequency of a central processing unit of a computer system including a disk drive, wherein a fourth predetermined value is changed from an initial state in response to termination of access to the disk drive. A fourth counter which starts counting the number of times, control means for instructing to increase the substantial operating frequency of the central processing unit in response to the end of the access to the disk device, and wherein the fourth counter has the fourth predetermined value. If the predetermined activity of a device other than the disk device has occurred before finishing the counting, in response to the end of the activity,
A third counter for counting a third predetermined value from an initial state, wherein the control means responds to the completion of the third counter counting the third predetermined value, A device characterized by ordering a substantial operating frequency to be reduced. 14. A first counter which loads a first predetermined value and counts down the value each time a device other than the disk device performs a predetermined activity, and wherein the count of the first counter is 0. The second if
Is loaded, and the count of the first counter becomes 0
And a second counter that counts down if not, wherein the third counter has reached zero before the fourth counter has finished counting the fourth predetermined value. 14. The device of claim 13, wherein in such a case, counting starts in response to the count of the first counter reaching zero. 15. The control means according to claim 4, wherein when the predetermined activity of a device other than the disk device does not occur before the fourth counter finishes counting the fourth predetermined value, the fourth counter is activated. 14. The device of claim 13, wherein after the fourth predetermined value has been counted, a command is issued to lower the substantial operating frequency of the central processing unit. 16. The device according to claim 13, wherein the device other than the disk device is a graphics device, and the predetermined activity is an access to a predetermined memory address. 17. The device according to claim 13, further comprising means for detecting completion of access to said disk device. 18. A computer system having a central processing unit, wherein a method of controlling a substantial operating frequency of the central processing unit, generated without placing between a predetermined time t ₁ or more, in the computer system A given activity of the device at a given time t
_An operating frequency control method, comprising: a determining step of determining whether or not _two or more operations have been performed; and, if it is determined that the operation is continued, increasing a substantial operating frequency of the central processing unit. 19. occur without placing between the predetermined time t ₁ or more, and a second determination step of predetermined activity devices in the computer system determines whether completed, terminated by the second determination step There after the lapse confirmed and the predetermined time t _3, the operating frequency control method according to claim 18, further comprising the steps of: lowering a substantial operating frequency of said central processing unit. 20. A method for controlling a substantial operating frequency of a central processing unit in a computer system having a disk unit and a central processing unit, the method comprising: specifically a step of increasing the operating frequency, the access end after a predetermined time t ₄ within to the disk device, a determination step of determining whether a predetermined activity of the device other than the disk device occurs, when the predetermined activity occurs If it is determined after the predetermined activity completed, after the predetermined time t ₃ has elapsed, the step of lowering the substantial operating frequency of said central processing unit, the operating frequency control method comprising. 21. wherein said predetermined activity, the operating frequency control method according to claim 20, wherein the predetermined time occurs without placing between t ₁ or more, an activity of the device other than the disk device. 22. wherein said predetermined activity, said the occurring without placing between a predetermined time t ₁ or more, the a active device other than the disk device, and those followed predetermined time t ₂ or more 21. The operating frequency control method according to claim 20, wherein 23. In a computer system having a disk device and a central processing unit, a method for controlling a substantial operating frequency of the central processing unit, the method comprising: specifically a step of increasing the operating frequency, the access end after a predetermined time t ₄ within to the disk device, a determination step of determining whether a predetermined activity of the device other than the disk device occurs, when the predetermined activity occurs When it is determined, after a predetermined time t ₃ after the end of the predetermined activity or the predetermined time t ₄ , whichever is later, a step of lowering the substantial operating frequency of the central processing unit; Operating frequency control method including: