JP2001022337A - Power saving monitor controller and power saving monitor control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power saving monitor control method and a power saving monitor controller performing the power saving control of a display device by judging the inactive state of electronic equipment not by the presence or absence of an input to an input device but by the operation state of a CPU. SOLUTION: The power control of a display device is performed by judging the detection of the inactive state of a computer by judging whether a CPU is executing prescribed instructions for a fixed period or not. The instruction executing state of the CPU is monitored at fixed time intervals and when the CPU executes the prescribed instructions, the counter of operations of the CPU is counted up and when the value of the counter exceeds a prescribed threshold during a fixed time, the computer is judged to be in an inactive period and a monitor is shifted to a power saving mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power saving control method and a power saving control device for a monitor of a personal computer.

[0002]

2. Description of the Related Art Conventionally, in an electronic device such as a personal computer, as a power control method of a display monitor, a CPU, a BIOS, or the like is used when an input device of a personal computer is not input for a certain period of time.
Generates a control signal for the monitor by combining the HSYNC signal and the VSYNC signal to shift to the power saving mode, and the monitor receiving the control signal shifts to the power saving mode and saves the power until the input device is again input. A method of maintaining the power mode has been adopted.

[0003]

However, in the above method, when the CPU is operating but there is no input from the input / output device, the DVD title is reproduced by a computer having a built-in DVD drive, for example. In the case of watching, for example, a computer is used, but an input device is not used. Therefore, there is no input from the input device for a predetermined time even though the user is watching an image on the display device. Based on this determination, the display device shifts to the power saving mode, and the display of the display device disappears.

Therefore, in the present invention, the inactivity period of the computer is detected by determining whether or not a predetermined command is being executed from the CPU, thereby reducing the power consumption of the display device. It is an object to provide a power monitor control method and a power saving monitor control device.

[0005]

In order to achieve the above object, according to the present invention, a CPU, a memory, a monitor, a system timer for periodically interrupting the CPU, and power saving of the monitor are provided. A display controller having a function of performing control; and
In accordance with the instruction routine stored in the memory, when an interrupt is given to the CPU by the system timer, the CPU counts by the CPU when the predetermined instruction is executed, and is counted by the CPU operation counting means. If the measured value exceeds a predetermined threshold, the CPU determines that the monitor is inactive. If the inactive period determiner determines that the monitor is inactive, the CPU saves power. It is characterized by shifting to an operation mode.

With such a configuration, it is possible to perform power saving control of the monitor reflecting the operation state of the computer.

Further, in the invention according to claim 4, the CPU
, A memory, a monitor, a system timer for periodically interrupting the CPU, and a display controller having a function of performing power saving control of the monitor. A power monitoring control method, comprising: a CPU operation counting step for counting when a predetermined instruction is executed by the CPU when an interrupt is applied to the CPU by a system timer according to an instruction routine stored in a memory; When the value counted by the CPU operation counting step exceeds a predetermined threshold value, an inactive period determining step of determining inactive, and a case in which the inactive period determining means determines inactive. Transitioning the monitor to the power-saving operation mode. And wherein the door.

With such a configuration, it is possible to perform power saving control of the monitor reflecting the operation state of the computer.

[0009]

Embodiments of the present invention will be described below.
This will be described with reference to the drawings.

FIGS. 1 and 2 show an embodiment according to the present invention. FIG. 1 is a block diagram of a computer system according to the present invention.

The electronic apparatus is, for example, a notebook or laptop portable computer driven by a battery or an AC power supply, and has a CPU local bus 3, a PCI bus 4, and an ISA bus 5 on a system board thereof. It is arranged.

In the computer main body, a CPU 11, a host / PCI bridge device 12, a main memory 13, a display controller 14, a PCI / ISA bridge device 17, an HDD 18, a BIOS-ROM 19, an interrupt controller 20, a system timer 21, an embedded controller ( The power supply controller 24, the AC adapter 25, the battery pack 26,
It comprises a counter 28 and the like.

The CPU 11 controls the operation of the entire system and executes data processing. This CPU
The CPU local bus 3 directly connected to the 11 input / output pins has a 64-bit data bus.

The main memory 13 is a memory device for storing an operating system, a device driver, an application program to be executed, processing data, and the like, and includes a plurality of DRAMs. This main memory is connected to the host / PCI bridge device 12 via a dedicated memory bus. As a data bus of the memory bus, a CPU local bus 3
Can also be used. In this case, the memory bus includes an address bus and various memory control signal lines.

The host / PCI bridge device 12 has a CP
A bridge LSI connecting the U local bus 3 and the PCI bus 4, and one of the bus master devices of the PCI bus 4
Function as one. This host / PCI bridge device 1
2 is between the CPU local bus 3 and the PCI bus 4
It has a function of bidirectionally converting bus cycles including data and addresses, and a function of controlling access to the main memory 13 via a memory bus.

The PCI bus 4 is a clock synchronous type input / output bus, and all the cycles on the PCI bus 4
This is performed in synchronization with the bus clock. The PCI bus 4 has an address / data bus used in a time-division manner. This address / data bus is 32 bits wide.

The display controller 14 is one of the bus master devices of the PCI bus 4 like the host / PCI bridge device 12, and controls an LCD provided as standard in a computer and an external CRT display connected to an RGB connector. It is for controlling.
The image data of the video memory (VRAM) 15 is stored in the LCD 1
6 is displayed. In addition, it has a function of performing power saving control of a CRT or LCD.

The PCI / ISA bridge device 17 is a PC
This is a bridge LSI that connects the I bus 4 and the ISA bus 5. HDD 1 used as data storage / playback device
Also, an IDE controller for performing the control of Step 8 is built in. PC
The HDD 18 is connected to the I / ISA bridge device 17. The ISA bus 5 has a BIOS-ROM 19, an interrupt controller 20, a system timer 21, an EC2
2, a counter 28 and the like are connected.

The BIOS-ROM 19 stores a system BIOS.
This is for storing S (Basic I / O System), and is constituted by a flash memory so that a program can be rewritten. System BIOS
Is a systematization of function execution routines for accessing various hardware in this system.
The BIOS-ROM 19 stores a power saving transition routine of the present invention. Also, a hardware control program for reading / writing the CMOS memory 29 for setting / changing the system configuration information stored in the CMOS memory 29 is stored.
The power saving shift threshold value for determining that the CPU 11 is the inactive period and the monitoring period value for setting the period for monitoring the instruction execution status of the CPU 11 are the CMOS memory 2.
9 is stored. These values can be arbitrarily set by the user.

The counter 28 includes an interrupt counter for counting the observation time (number of interrupts),
A CPU operation counter for counting the number of ALT instructions is provided.

The EC 22 comprises an ISA bus 5 and an I2C bus 6
And a plurality of register groups that can be read / written by the CPU 11.
By using these register groups, communication between the CPU 11 and devices on the I2C bus 6 becomes possible. The EC 22 also has a function as a keyboard controller (hereinafter referred to as KBC), and a keyboard / mouse 23 is connected to the EC 22.

The I2C bus 6 is used for communication between the EC 22 and the power controller 24.

An AC adapter 25 for connecting a commercial power supply to the computer main body is connected to the power supply controller 24. Thus, the computer main body can be driven by the commercial power supply via the AC adapter 25. Also,
The power controller 24 is a controller that controls operation power such as turning on / off the power of the computer system, and controls charging of the secondary battery of the battery pack 26 and the like.

The interrupt controller 20 includes a system timer 21, an EC 22, and other I / O devices 2.
7 and receives the interrupt request signals (IRQ0 to IRQ15) from the CPU 7 according to the priority order of the interrupt signals.
11 is controlled by an interrupt signal. In this case, status information indicating the generated interrupt request signal is held in a register in the interrupt controller 20. The interrupt signal INTR is a hardware interrupt request signal (IR
Q0 to IRQ15) are generated when any one of them is generated.

Here, IRQ0 is a timer interrupt request signal generated by the system timer 21. IRQ0
Can be set programmably. IR
Q1 is a keyboard interrupt signal generated from the EC 22 at the time of key input. The interrupt signal from the EC 22 includes an interrupt signal IR generated when the mouse is operated.
There is also Q12. IRQ2 to IRQ11, IRQ13 to IRQ
RQ15 is an interrupt request signal from other various I / O devices (for example, a floppy disk controller or the like) in the system.

In the present embodiment, a power saving transition routine stored in the BIOS-ROM is executed. This means that the CPU 11 is interrupted at regular time intervals, and the CPU operation counter is incremented according to the instruction execution status of the CPU 11 at that time. When the CPU operation counter exceeds a predetermined threshold, the mode shifts to the power saving mode.

FIG. 2 shows a flowchart of a power saving transition routine according to the present invention.

At a certain time interval, the timer is interrupted (IR
When (Q0) occurs (step S102), the interrupt counter is counted up (step S103). This interrupt counter indicates the number of interrupts (the number of samples of the CPU instruction execution status) and is cleared at regular intervals (for example, every five minutes). In the present embodiment,
For example, the interrupt time interval is set to occur every 50 ms. This interruption time interval can be changed by the user as appropriate. If the period for monitoring the inactivity state of the CPU 11 is set to 5 minutes, the monitoring period value is set to 6000. Therefore, the interrupt counter is reset to “0” every time the value reaches 6000. You.

When a timer interrupt occurs, the CPU 1
1 judges that the HALT instruction has been executed (step S104: YES).
The CPU operation counter for determining the inactive state of the CPU 11 is counted up (step S105).

When the CPU operation counter is counted up, the value of the CPU operation counter is compared with a power saving shift threshold value (step S106). The power saving shift threshold is set to a value of about 90% to 90% of the monitoring period value. This value can be arbitrarily set by the user.

As a result of the comparison, when the power saving threshold has been exceeded (YES in step S106), the values of the interrupt counter and the CPU operation counter are reset (step S107). Sends a power transfer command (step S
108).

As a result of comparing the value of the CPU operation counter with the power saving shift threshold, if the value does not exceed the power saving shift threshold (NO in step S106), the interrupt counter is compared with the monitoring period value (step S106). S11
0).

Here, when the value of the interrupt counter becomes equal to the monitoring period value (step S109)
YES), indicating that the monitoring period has ended, the interrupt counter and the CPU operation counter are reset.

If the value of the interrupt counter does not exceed the value of the monitoring period value (N in step S109)
O), until the interrupt counter is reset to 0,
The remaining number of interrupts (monitoring period value−interrupt counter) is compared with the number of remaining CPU operation counters (power saving shift threshold−CPU operation counter) required to shift to the power saving mode (step S111).

As a result of the comparison, if the remaining number of interrupts is small (YES in step S111), the interrupt counter and the CPU operation counter are reset to zero. This means that the CPU 1
Even if 1 executes the HALT command, the power saving transition threshold is not reached, so that a new monitoring period is started.

As a result of the comparison, if the number of remaining interrupts is large (NO in step S111), the process returns to the timer interrupt waiting state (step S101).

If the CPU 11 has executed an instruction other than the HALT instruction, the CPU 11 compares the interrupt counter with the monitoring period value in the processing of step S104 (step S109). The processing of step S109 and subsequent steps are the same as those described above, and will not be described.

The display controller 14 which has received the power saving shift command controls the vertical synchronizing signal and the horizontal synchronizing signal by DPMS control, for example, so that the display shifts to the power saving mode. Alternatively, in the case of a liquid crystal display or the like, the backlight may be turned off.

During the operation of this routine, EC2
2 or when an interrupt from another I / O device 27 occurs, the interrupt counter and C
The PU operation counter is reset to “0”, and step S1
01 may be returned.

Note that the return from the power saving mode to the normal operation mode may be performed when an interrupt other than the system timer interrupt occurs.

As described above, according to the present invention, the power control of the display device can be performed by detecting the inactive period of the computer and determining whether or not the CPU is executing a predetermined instruction. become.

[0042]

According to the invention described in detail above, the inactivity period of the computer is detected by judging whether or not the CPU is executing a predetermined instruction, thereby saving the monitor reflecting the operation state of the computer. It is possible to perform power control.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computer system according to the present invention.

FIG. 2 is a flowchart of a power saving mode transition routine according to the present invention.

[Explanation of symbols]

 3 CPU local bus 4 PCI bus 5 ISA bus 6 I2C bus 11 CPU 12 Host / PCI bridge device 13 Main memory 14 Display controller 15 Video memory 16 LCD 17 PCI / ISA bridge device 18 ... HDD 19 ... BIOS-ROM 20 ... Interrupt controller 21 ... System timer 22 ... Embedded controller 23 ... Keyboard / mouse 24 ... Power supply controller 25 ... AC adapter 26 ... Battery

Claims (4)

[Claims] A CPU, a memory, a monitor, and the CP;
In an electronic device including a system timer that periodically interrupts U and a display controller having a function of performing power saving control of the monitor, the system timer uses the system timer according to an instruction routine stored in the memory. A CPU operation counting means for counting when a predetermined instruction is executed in the CPU when the CPU is interrupted, and a case where a value counted by the CPU operation counting means exceeds a predetermined threshold value. The inactive period determining means for determining that the CPU is inactive, and the inactive period determining means,
A power-saving monitor control device, wherein, when it is determined that the monitor is inactive, the monitor is shifted to a power-saving operation mode. 2. The power-saving monitor control device according to claim 1, wherein said memory comprises a rewritable flash memory in which said instruction routine is stored. 3. The power-saving monitor control device includes input detection means for detecting an input from an input device of the electronic device, and operates when the input detection means detects an input. 3. The power saving monitor control device according to claim 1, wherein a value counted by the counting means is initialized. 4. A CPU, a memory, a monitor, and the CP
A power saving monitor control method having a plurality of different power consumption operation modes in an electronic device having a system timer that periodically interrupts U and a display controller having a function of performing power saving control of the monitor. A CPU operation counting step for counting when a predetermined instruction is executed by the CPU when the system timer interrupts the CPU according to an instruction routine stored in the memory; When the value counted by the operation counting step exceeds a predetermined threshold, an inactive period determining step of determining inactive, and when the inactive period determining means determines that the inactive state, Shifting the monitor to a power saving operation mode. Saving power monitor control method according to Rukoto features.