JPH1173340A - Logical circuit and method for controlling logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of malfunction due to the occurrence of conflict and the occurrence of device deterioration by providing an input-output control means of data of a bidirectional bus between the bidirectional bus and a control register. SOLUTION: An OR gate 20 is inserted into a control signal line 221 that controls a bidirectional bus which is connected to a bidirectional control pin of an output side buffer 22 of a bidirectional buffer, and one input is connected to a bidirectional control signal that is an output of an FF 19 on the side of a system. A control scan register 21 of input space is inserted into the other input side of the gate 20, and its output signal is connected. It is possible to perform scan in setting of optional '0' or '1' to the controlling scan register and to set the bidirectional bus to an input mode by inserting the control scan register into the control signal line that controls the bidirectional bus and making its output signal and a control signal which controls the bidirectional bus an OR.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a configuration of a logic circuit for controlling a bidirectional bus of a logic circuit device used in electronic equipment and a control method therefor. In particular, the present invention relates to a configuration of a logic circuit which does not cause a malfunction due to occurrence of a conflict of a bidirectional bus of a device in a test of a real device and does not cause device deterioration due to a conflict, and a control method thereof. .

[0002]

2. Description of the Related Art In a normal system operation of a logic circuit including a bidirectional bus, the bidirectional bus is switched between an input mode and an output mode by controlling the bidirectional bus inside the logic circuit. It is configured so that the output is output in the input and output modes. In the actual device test of this logic circuit, the maximum frequency of the measuring device, the number of timing sets that can be set (the type of timing (waveform)), the timing resolution (at least how finely, for example, 1 ns unit, 500 PS unit, etc. Due to restrictions on whether a waveform can be generated, etc.), the control of the bidirectional bus cannot be operated in the same way as the actual operation.
There was a problem that a bus input / output conflict occurred. For this reason, in the actual device test, unlike the actual operation, it is necessary to perform the test so that no conflict occurs. Further, when performing a function / logic verification of a logic circuit including a bidirectional bus using a simulator or the like, test data is created and simulation is performed without being conscious of a conflict that occurs in an actual device. In the simulator, simulation can be performed in consideration of timing not by real time but by a time unit. Specifically, the number of timing sets can be set as many as the number of signals, and the timing resolution can be arbitrarily determined depending on the number of ns per time unit.
Therefore, on the simulator, there is no problem even if test data is created without being aware of conflicts. However, the test data for the simulator cannot be used as it is for a test of an actual device, and thus requires modification and the like.

[0003] To solve the above problems, conventionally, a pattern which meets restrictions such as the maximum frequency of a measuring device, the number of timing sets that can be set, and the timing resolution has been prepared. Based on the above, a method of modifying the constraints so as to satisfy the constraints and performing a re-simulation is employed. Further, in a logic circuit employing a test facilitation design such as a scan design, a test pattern can be automatically generated. However, the automatic test pattern generation tool performs a back trace and a forward trace from a topological circuit configuration, and generates a pattern capable of statically detecting a failure. Therefore, it is not possible to generate a pattern in consideration of bidirectional control (considering the timing of switching input / output). Regarding the bidirectional bus of the real device, it recognizes which signal of the circuit is a bidirectional switching (control) signal and what the sequence for controlling it should be, and sometimes it is an input and sometimes it is an output Used (with timing) as designed to operate the system. Therefore, measures such as masking a pattern in which a conflict occurs with an automatically generated pattern are taken.

FIGS. 10 and 11 are diagrams for explaining the prior art, its control method, and problems. FIG.
Is a block diagram showing a configuration of a conventional logic circuit. In the figure, 1 is a system circuit, and 2 is a flip-flop (Flip-F) for controlling bidirectional input / output in a system operation.
loop, hereinafter also referred to as FF), 3 is an output side buffer (with input / output control) of a bidirectional buffer, 4 is a system circuit,
Reference numeral 5 denotes INOUT, which is an external input / output terminal of the bidirectional bus, and 6
Is an input buffer of a bidirectional buffer, 7 is a flip-flop (Flip-Flop, FF), 8 is a system circuit, and 9 is a system clock CLK. FIG. 11 is a diagram showing a timing chart of the conventional logic circuit shown in FIG. In the figure, reference numerals 10 to 17 indicate periods (each cycle). In the example of the timing chart of FIG. 11, for example, in period 15, when CLK enters FF2, the output of FF2 changes from H to L, and the bidirectional buffer changes from input mode to output mode. At this time, when this logic circuit is tested on, for example, an LSI tester, the input pattern is applied (driven) from INOUT during the first half of the cycle 15 because the input mode is used. On the tester, the input pattern operates on a cycle basis.
It is supplied from OUT and driven, resulting in a conflict. In the actual operation of the system, the CLK is stopped or controlled by the control circuit so that no conflict occurs. However, such control cannot be performed on the tester, and the test pattern is automatically generated by the test pattern automatic generation tool. Since the generated pattern cannot be generated in consideration of timing, a conflict occurs during a test.

[0005]

In a conventional method, in testing a real device of a logic circuit including a bidirectional bus,
When creating a pattern that satisfies constraints such as the maximum frequency of the measurement device, the number of timing sets that can be set, and the timing resolution, or when using a logic / function verification pattern, it is necessary to modify the pattern to satisfy these constraints. In particular, a large-scale logic circuit requires a great deal of time and labor. In particular, recently, in a large-scale logic circuit, automatic generation of a test pattern by adopting a testability design technique such as scan design performs a test with a high detection rate (guarantees product quality). ) Is becoming essential. The scan design is a testability design for a widely and commonly used logic circuit. Register in logic circuit (Flip
−Flop) All of them are connected as scan registers by a scan chain, whereby a value in a register in the circuit can be set freely and a value of the register can be read out. Since the inside of the logic circuit is a combination of a scan register and a combinational circuit, the test can be performed for each combinational circuit. However, it is difficult to generate test patterns and test sequences with a test pattern generation tool for circuits that employ testability design techniques such as scan design in consideration of the occurrence of conflicts on bidirectional buses. ,
It is necessary to take measures such as masking a pattern in which a conflict occurs on an automatically generated pattern, which requires a great deal of time and effort for simulation confirmation, manual confirmation, pattern correction, and the like. Further, as shown in FIG. 12, there is a method of adopting a corresponding method such as providing a test mode pin so that the bidirectional bus can be fixed to the input mode at the time of a test. However, this method requires a dedicated pin for that purpose. There are problems such as an increase in pin overhead and a failure in testing the output side of the bidirectional bus.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems.
An object of the present invention is to provide a logic circuit capable of performing a test without causing a malfunction due to a conflict of a bidirectional bus of a device and performing a test without causing a device degradation due to a conflict, and a control method thereof.
It is also an object of the present invention to realize a logic circuit and its control (test sequence) that minimizes the overhead in terms of pins / circuits / timings that can be handled in both the input mode and the input mode / output mode of the bidirectional bus. Aim.

[0007]

A logic circuit according to the present invention comprises:
In a logic circuit including a bidirectional bus for inputting / outputting data and a bus control register for outputting a signal for controlling the bidirectional bus, data of the bidirectional bus is interposed between the bidirectional bus and the bus control register. A control means for controlling input / output is provided.

The control means includes a control scan register capable of setting an arbitrary value, an output signal of the control scan register, and a signal for controlling the bidirectional bus output from the bus control register. And outputs a logical sum of the two as a signal for controlling the bidirectional bus.

The control means includes first and second input terminals for inputting different signals, and a selector signal for inputting a selector signal for selecting one of the signals input from the first and second input terminals. Selection means having an input terminal and an output terminal for outputting a signal selected by the selector signal, wherein a signal for controlling the bidirectional bus output from the bus control register is connected to the first input terminal. An arbitrary value is input to the second input terminal.

The control means includes at least one of a scan register capable of setting an arbitrary value and an external input terminal capable of inputting an arbitrary value, and the selecting means includes: a scan register connected to the second input terminal. It is characterized in that one of a value set in a register and a value input from the external input terminal is input.

The control means includes at least one of a scan register capable of setting an arbitrary value and an external input terminal capable of inputting an arbitrary value, and the selection means includes a scan register connected to the select signal input terminal. And the value input from the external input terminal.

The logic circuit further extracts a signal for controlling the bidirectional bus output from the bus control register and inputs the signal to a monitor scan register.

A method of controlling a logic circuit according to the present invention is a method of controlling a logic circuit including a bidirectional bus for inputting / outputting data and a bus control register for outputting a bus control signal for controlling the bidirectional bus. Inputting the bus control signal output from the bus control register to a bus control unit provided between the directing bus and the bus control register, and inputting an arbitrary value to the bus control unit; A bus control step of controlling the bidirectional bus to be set to the input mode based on the input bus control signal and an arbitrary value.

The logic circuit control method further includes a select signal input step of inputting a select signal of an arbitrary value to the bus control unit, wherein the bus control step is input by the select signal input step. Any one of the bus control signal and an arbitrary value input according to a select signal is selected and output as a bus control signal.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a logic circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing a timing chart of the logic circuit shown in FIG. This circuit configuration is a control circuit 221 for controlling a bidirectional bus connected to a bidirectional control pin of an output buffer 22 of a bidirectional buffer in a logic circuit including a bidirectional bus.
The OR gate 20 is connected to the other end, and one input of the OR gate 20 is connected to a bidirectional control signal output from the FF 19 on the system side. On the other input side of the OR gate 20, a control scan register 21 (in this case, a scan flip-flop) having an empty input is inserted, and its output signal is connected. An input empty control scan register means that the data input used in the system is empty (normally at 0 level). However, there are inputs and outputs for the scan operation. Thus, during normal system operation, the control scan register is always “0” after the initial setting because the input is empty, and the output value of the OR gate 20 is always the bidirectional output which is the output of the FF 19 on the system side. When the control signal is selected, the output side buffer 2 of the bidirectional buffer is
2 is controlled. Reference numerals 29 to 36 indicate periods (each cycle). On the other hand, at the time of testing, by setting scan-in to “1” in the control scan register by the input / output for the scan operation, the output buffer 2 of the bidirectional buffer is output via the OR gate 20 in an arbitrary test cycle.
2 can be set to set the bidirectional bus INOUT24 to the input mode. As shown in the timing chart of FIG. 2, the bidirectional bus is controlled by the control signal output from the FF 19 which is a control register. Therefore, during the test, when the value of the FF 19 is “1”, the control scan F
'1' is also entered in F21. Even when the value of the FF 19 changes when the CLK is input and the data is taken into the FF 26 as shown in the cycle 34, the control scan FF 21 is set to "1", so that during the cycle 34, the INOUT 24 is output.
Can be set to the input mode, and the test can be performed without conflict. Therefore, at the time of testing the actual device, it is possible to forcibly set the bidirectional bus to the input mode in a cycle in which the input is driven to the bidirectional bus INOUT24 so that a conflict of the bidirectional bus does not occur. . Further, since the control scan register sets the bidirectional bus to the input mode, there is no need to provide an external input terminal, and it is possible to reduce pin overhead. Since the control scan register is used, 0 and 1 can be freely set in the scan operation, so that the bidirectional bus can be controlled to the input mode independently of the actual operation of the system.

As described above, in this embodiment, in a logic circuit including a bidirectional bus, the control scan register is inserted into the control signal line for controlling the bidirectional bus, and the output signal of the control scan register is output. By ORing the control signal for controlling the bidirectional bus with an arbitrary value “0” or “1” in the control scan register, the bidirectional bus can be set to the input mode. The logic circuit that can be used has been described.

Embodiment 2 FIG. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing the configuration of the logic circuit according to this embodiment. In this embodiment, 2-to-1 selector (hereinafter referred to as MU) is used as a selecting means for selecting a signal for controlling a bidirectional bus.
X) will be described. In the logic circuit including the bidirectional bus, the circuit configuration includes a control signal line 391 that controls a bidirectional bus connected to a bidirectional control pin of an output buffer 41 of the bidirectional buffer.
The MUX 39 is inserted, and one input of the MUX 39 connects a bidirectional control signal which is an output of the FF 38 on the system side. A control scan register 40 (in this case, a scan flip-flop) having an empty input is inserted into the other input side of the MUX 39, and its output signal is connected.
A selector external input terminal 48 is provided for the select signal of the MUX 39. As a result, during normal system operation,
When “0” is set to the selector external input terminal 48, the MU
As the output value of X39, a bidirectional control signal that is always the output of the FF 38 on the system side is selected, and the output buffer 41 of the bidirectional buffer is controlled. On the other hand, during the test, “1” is set to the MUX select external input terminal 48, and the output value of the MUX 39 is selected from the value of the control scan register 40. The control scan register 40 is arbitrarily set to “0”. Alternatively, since the scan-in setting of “1” can be performed, the bidirectional bus can be independently controlled in the input mode and the output mode, and the actual device of the logic circuit is tested so that no bidirectional conflict occurs. It becomes possible.

FIG. 4 is a block diagram showing another example of the configuration of the logic circuit of this embodiment. 4, the control scan register 40 shown in FIG. 3 is replaced with a control external input terminal 140, and the same operation as the configuration shown in FIG. 3 can be performed.

FIG. 5 is a block diagram showing another example of the configuration of the logic circuit of this embodiment. In FIG.
Instead of the selector external input terminal 48 shown in FIG.
It is replaced by the X select scan register 148, and can perform the same operation as the configuration shown in FIG. Also, as shown in FIG. 6, the control scan register 40 of FIG. 5 may be replaced with a control external input terminal 140.

As described above, in this embodiment, in the logic circuit including the bidirectional bus, the MUX (2-to-1 s) is applied to the control signal line for controlling the bidirectional bus.
and a control scan register is inserted into the other input side of the MUX, and a signal for controlling the bidirectional bus is connected to one input side of the inserted MUX.
The X selector signal can be controlled from an external input terminal. This allows the control scan register to be set to "0" or "1" for scan-in, and the value on the control scan register side to be selected from the MUX selector signal. The logic circuit that can be arbitrarily set has been described.

In a logic circuit including a bidirectional bus, a control signal line for controlling the bidirectional bus includes MUX.
(2-to-1 selector), a signal for controlling a bidirectional bus is connected to one input side of the inserted MUX, and a signal from an external input terminal is connected to the other input side of the MUX. Are controlled from an external input terminal. As a result, it is possible to set '0' or '1' to the external input terminal connected to one input side of the MUX, and to select the value set for this external input terminal from the selector signal of the MUX, The logic circuit that can arbitrarily set the bidirectional bus to the input mode or the output mode has been described.

In a logic circuit including a bidirectional bus, a control signal line for controlling the bidirectional bus includes MUX.
(2-to-1 selector), a signal for controlling the bidirectional bus is connected to one input side of the inserted MUX, a control scan register is inserted to the other input side of the MUX, and a MUX selector is inserted. A MUX select scan register is inserted into the signal so that it can be controlled. As a result, "0" or "1" is set to scan-in to the control scan register, "0" or "1" is set to scan-in to the MUX select scan register, and the value on the control scan register is selected. Thus, a logic circuit has been described that can set a bidirectional bus to an input mode or an output mode arbitrarily.

Embodiment 3 FIG. Next, a control method of the logic circuit will be described with reference to FIG. According to the control method of a logic circuit of this embodiment, in a logic circuit configuration including a bidirectional bus having the configuration of the above-described logic circuit, the bidirectional bus is switched from the output mode to the input mode by a control signal for controlling the bidirectional bus. In the switching cycle and the cycle in which the bidirectional bus is in the input mode state due to the control signal for controlling the bidirectional bus, the control for controlling the bidirectional bus is always set to “1” in the control scan register. The input mode can always be set during the switching cycle in which the signal switches the bidirectional bus from the output mode to the input mode and the cycle in which the bidirectional bus is in the input mode state by the control signal controlling the bidirectional bus. A test sequence that allows testing to be performed without any bidirectional bus conflicts,
This is a method for controlling a bidirectional bus. The period 34 of FIG.
Now, the bidirectional bus changes from input to output,
During an actual device test, the input is driven during this period, so that the control scan register 21 of FIG. 1 forcibly sets the bidirectional bus to the input mode so that this conflict does not occur. . This control method and test sequence can be applied even when the control scan register 21 in FIG. 1 is a control external input terminal. FIG. 7 shows a flow for automatically editing a pattern automatically generated by automatic test pattern generation by adopting an existing function / logic verification pattern and testability design into the above-described control method and test sequence. In the search of the input mode cycle (S10), the cycle in which the bidirectional bus is in the input mode is searched. In the search method, the value of the control signal of the bidirectional bus is checked from the simulation result, and the periods in which the input mode is controlled are listed. Next, in the switching period search for switching from the input mode to the output mode (S20), the periods for changing from the input mode to the output mode are listed in the same manner as in S10. Next, the searched cycle is set to the input mode (S3
In the case of 0), a sequence is set so that the searched cycle is forcibly set to the input mode by the control scan register (embedded in the simulation result). Thus, when the input mode is set at the beginning of each cycle of the test pattern, the bidirectional bus is set to the input mode so that no conflict occurs in that cycle.

Next, the case where both buses are controlled to the input mode and the output mode will be described with reference to FIG. In the logic circuit configuration including the bidirectional bus shown in FIGS. 3 to 6, the bidirectional bus is arbitrarily controlled independently of the input mode and the output mode so that a bidirectional conflict is not generated at all. The control method and test sequence for testing in two modes. FIG.
FIG. 9 shows a control flow for performing tests independently in an input mode and an output mode, and a flow of generating a test sequence. First, the input mode is set (S51), and then the pattern is generated under the set conditions (S53). Next, after setting the output mode (S55), under the conditions,
A test pattern is generated (S57). Thus, in the test pattern generation, the bidirectional bus is always fixed to the input or the output, so that no conflict occurs.

As described above, in this embodiment, in the logic circuit configuration including the bidirectional bus, the switching cycle in which the bidirectional bus is switched from the output mode to the input mode by the control signal for controlling the bidirectional bus, and both In a cycle in which the bidirectional bus is in the input mode state by the control signal for controlling the bidirectional bus, the control signal for controlling the bidirectional bus is always set to '1' in the control scan register. The input mode can always be set during the switching period in which the output mode is switched to the input mode and the period in which the bidirectional bus is in the input mode state by the control signal for controlling the bidirectional bus. Test sequence and bi-directional bus control to enable testing to avoid any conflicts It is. As another control method, a control method has been described in which a test is performed by always setting the bidirectional bus to the input mode by setting "1" in the scan register for control scan-in.

In a logic circuit configuration including a bidirectional bus, a MUX (2-to-1 selector) inserted into a control signal line for controlling the bidirectional bus and an MUX controllable from an external terminal or a MUX select scan register are provided. The bidirectional bus can be set in the input mode and the output mode by using the selector signal of the MUX and an external input terminal connected to the control scan register on one input side of the MUX or one input of the MUX. Thus, the test sequence and the control method of the bidirectional bus in which the test can be performed independently in the two modes (input mode and output mode) so that no conflict of the bidirectional bus occurs at all have been described.

Embodiment 4 Next, another embodiment of the present invention will be described with reference to FIG. In the configuration of the logic circuit shown in FIG. 9, in a logic circuit configuration including a bidirectional bus, in order to control bidirectionally in an input mode and an output mode independently from a control scan register or a control external input terminal, for example, FIG. At 9, the circuit from the FF 50 that controls the bidirectional bus on the system side to the system circuit (combination circuit) 61 and the input of the MUX 51 cannot be tested. Therefore, as shown in FIG. 9, a monitor register (monitor for monitoring in FIG. 9) is provided so that circuits from the FF 50 for controlling the bidirectional bus on the system side to the system circuit (combination circuit) 61 and the input of the MUX 51 can be monitored during the test. By providing the scan FF 62), it is possible to cover with a test.

As described above, in this embodiment, a signal for controlling the bidirectional bus of the system which is one input side of the inserted MUX is extracted and a monitor scan register is provided, so that the bidirectional bus is connected. The logic circuit capable of constantly monitoring the signal value of the signal to be controlled has been described.

[0029]

According to the present invention, in a logic circuit including a bidirectional bus, a test can be performed without causing a malfunction due to occurrence of a conflict of a bidirectional bus of a device, and a test can be performed without causing device deterioration due to a conflict. Can be.

According to the present invention, in a logic circuit including a bidirectional bus, the control scan register inserted into the control signal line for controlling the bidirectional bus is set to scan-in with “1” to thereby enable bidirectional bus control. The bus can be set to input mode.

According to the present invention, in a logic circuit including a bidirectional bus, the bidirectional bus is arbitrarily set to the input mode or the output mode by the selection means inserted into the control signal line for controlling the bidirectional bus. Can be.

According to the present invention, in a logic circuit including a bidirectional bus, by inputting an arbitrary value to a selection means inserted into a control signal line for controlling the bidirectional bus by a scan register or an external input terminal, The bidirectional bus can be arbitrarily set to input mode or output mode.

According to the present invention, in a logic circuit including a bidirectional bus, a selection means inserted into a control signal line for controlling the bidirectional bus receives an arbitrary value as a select signal from a scan register or an external input terminal. Then, by controlling, the bidirectional bus can be arbitrarily set to the input mode or the output mode.

According to the present invention, in a logic circuit configuration including a bidirectional bus, a signal for controlling a bidirectional bus of a system on one input side of the inserted MUX is extracted,
By providing the monitor scan register, the signal value of the signal for controlling the bidirectional bus can be constantly monitored.

According to the present invention, in a logic circuit including a bidirectional bus, a switching cycle for switching the bidirectional bus from the output mode to the input mode by a control signal for controlling the bidirectional bus, and a control signal for controlling the bidirectional bus are provided. In the cycle in which the bidirectional bus is in the input mode state, the bidirectional bus is switched from the output mode to the input mode by the control signal for controlling the bidirectional bus by always setting “1” in the control scan register. During the switching period and the period in which the bidirectional bus is in the input mode state due to the control signal for controlling the bidirectional bus, the input mode can always be set to the input mode, and the test is performed so that no conflict occurs in the bidirectional bus. It can be performed.
Thus, when a test is performed using a simulation pattern that does not consider the control of the bidirectional bus, a test that does not cause a conflict can be performed. As another control method, a test can be performed by always setting the bidirectional bus to the input mode by setting “1” in the control scan register.

According to the present invention, in a logic circuit including a bidirectional bus, in the bus control step of controlling the bidirectional bus, the bus control signal can be switched according to an arbitrary value input in the select signal input step, The bidirectional bus can be independently set in the input mode and the output mode, and a test can be performed independently in two modes (input mode and output mode) so that no conflict of the bidirectional bus occurs at all. .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a logic circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a timing chart of control according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a logic circuit according to a second embodiment of the present invention;

FIG. 4 is a diagram showing a configuration of a logic circuit according to a second embodiment of the present invention;

FIG. 5 is a diagram illustrating a configuration of a logic circuit according to a second embodiment of the present invention;

FIG. 6 is a diagram illustrating a configuration of a logic circuit according to a second embodiment of the present invention;

FIG. 7 is a diagram showing a generation flow of the control method of the present invention.

FIG. 8 is a diagram showing a generation flow of the control method of the present invention.

FIG. 9 is a diagram illustrating a configuration of a logic circuit according to a fourth embodiment of the present invention;

FIG. 10 is an explanatory diagram of a conventional logic circuit.

FIG. 11 is an explanatory diagram of a timing chart of a conventional logic circuit.

FIG. 12 is an explanatory diagram of a conventional logic circuit.

[Explanation of symbols]

Reference Signs List 18 system circuit, 19 FF for controlling bidirectional input / output by system operation, 20 OR gate, 21 control scan register, 22 output buffer of bidirectional buffer (with input / output control), 23 system circuit, 24
External input / output terminal of bidirectional bus, 25 Input buffer of bidirectional buffer, 26 FF, 27 system circuit, 2
8 system clock, 29 to 36 cycles (each cycle), 37 system circuits, 38 FF for controlling bidirectional input / output by system operation, 39MUX, 40 scan register for control, 41 output buffer of bidirectional buffer (input / output) 42 system circuit, 43 bidirectional bus external input / output terminal, 44 bidirectional buffer input buffer, 45 FF, 46 system circuit, 4
7 system clock, 48 MUX external input terminal for selector, 49 system circuit, 50 FF for controlling bidirectional input / output by system operation, 51 OR gate, 52
Control scan register, 53 bidirectional buffer output buffer (with input / output control), 54 system circuit, 55 bidirectional bus external input / output terminal, 56 bidirectional buffer input buffer, 57 FF, 58 system circuit , 59 system clock, 60 MUX external input terminal for selector, 61 system circuit (combination circuit), 62 monitor scan FF.

Continued on the front page (72) Inventor Kazuo Chiba 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (8)

[Claims] 1. A logic circuit comprising a bidirectional bus for inputting and outputting data and a bus control register for outputting a signal for controlling the bidirectional bus, wherein the logic circuit includes a bus control register between the bidirectional bus and the bus control register. A logic circuit comprising control means for controlling input / output of data for a directional bus. 2. The control means controls a control scan register capable of setting an arbitrary value, an output signal of the control scan register, and the bidirectional bus output from the bus control register. 2. The logic circuit according to claim 1, further comprising: a logical sum circuit that inputs a signal and outputs a logical sum of the two as a signal for controlling the bidirectional bus. 3. The control means inputs first and second input terminals for inputting different signals and a selector signal for selecting one of the signals input from the first and second input terminals. Selection means having a selector signal input terminal and an output terminal for outputting a signal selected by the selector signal, wherein a signal for controlling the bidirectional bus output from the bus control register is provided to the first input terminal. 2. The logic circuit according to claim 1, wherein the logic circuit is connected to and inputs an arbitrary value to the second input terminal. 4. The control means includes at least one of a scan register capable of setting an arbitrary value and an external input terminal capable of inputting an arbitrary value. 4. The method according to claim 3, wherein one of a value set in the scan register and a value input from the external input terminal is input.
The logic circuit according to the above. 5. The control means includes at least one of a scan register capable of setting an arbitrary value and an external input terminal capable of inputting an arbitrary value, and the selecting means includes: 5. The logic circuit according to claim 3, wherein one of a value set in a scan register and a value input from the external input terminal is input. 6. The logic circuit according to claim 3, wherein the logic circuit further extracts a signal for controlling the bidirectional bus output from the bus control register and inputs the signal to a monitor scan register. The logic circuit according to any one of the above. 7. A control method for a logic circuit including a bidirectional bus for inputting / outputting data and a bus control register for outputting a bus control signal for controlling the bidirectional bus, wherein the bidirectional bus, the bus control register, A step of inputting the bus control signal output from the bus control register to a bus control unit provided between; a step of inputting an arbitrary value to the bus control unit; A bus control step of controlling the bidirectional bus to be set to an input mode by an arbitrary value. 8. The logic circuit control method further includes a select signal input step of inputting a select signal of an arbitrary value to the bus control unit, wherein the bus control step is performed by the select signal input step. 8. The method according to claim 7, wherein one of the bus control signal and an arbitrary value input according to the selected select signal is selected and output as a bus control signal.